JPS616834A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS616834A
JPS616834A JP59127825A JP12782584A JPS616834A JP S616834 A JPS616834 A JP S616834A JP 59127825 A JP59127825 A JP 59127825A JP 12782584 A JP12782584 A JP 12782584A JP S616834 A JPS616834 A JP S616834A
Authority
JP
Japan
Prior art keywords
substrate
pattern
bonding
reinforcing
reinforcing pattern
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP59127825A
Other languages
Japanese (ja)
Inventor
Tadanobu Terui
照井　忠信
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP59127825A priority Critical patent/JPS616834A/en
Publication of JPS616834A publication Critical patent/JPS616834A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49175—Parallel arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/852—Applying energy for connecting
    • H01L2224/85201—Compression bonding
    • H01L2224/85203—Thermocompression bonding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/852—Applying energy for connecting
    • H01L2224/85201—Compression bonding
    • H01L2224/85205—Ultrasonic bonding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]

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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)

Abstract

PURPOSE:To raise a substrate temperature up to about 200 deg.C and give sufficient bonding strength to the substrate by previously forming a reinforcing pattern covering the leads at the rear surface of lead pattern of circuit substrate and executing the wire bonding thereto. CONSTITUTION:Bonding strength can be improved by providing previously a reinforcing pattern 8 indicated by the broken line to the rear surface position corresponding to the lead portion 6 prior to thermally-pressurized joint by ultrasonic wave. Here, the reinforcing pattern 8 can usually be formed simultaneously with ordinary pattern by the photo etching technique and if there is other pattern in the relevant position, it may be used in place of such reinforcing pattern. The bonding can be realized with high efficiency even in case the substrate is thin and soft by enhancing the substrate strength.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明はワイヤボンディング効率を改良した半導体装置
の製造方法に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method of manufacturing a semiconductor device with improved wire bonding efficiency.

半導体チップ（以下略してチップ）はセラミック基板上
に形成された厚膜または薄膜パターン或いはプリント配
線基板上に形成された微細パターン上にワイヤポンディ
ング、フェイスダウンボンディング、ビームリードボン
ディングなどの方法で回路接続されている。A semiconductor chip (hereinafter referred to as a chip) is a circuit formed on a thick or thin film pattern formed on a ceramic substrate or a fine pattern formed on a printed wiring board using methods such as wire bonding, face-down bonding, and beam lead bonding. It is connected.

ここでビームリードボンディングはダイオードやトラン
ジスタのように端子数の少ないチップに対して適用され
ているが、ＩＣのように構成素子数が増し、従って端子
数が増加すると製作が困難となる。Here, beam lead bonding is applied to chips with a small number of terminals, such as diodes and transistors, but as the number of constituent elements and therefore the number of terminals increases, as in ICs, manufacturing becomes difficult.

そこでＩＣの回路接続にはワイヤボンディング或いはフ
ェイスダウンポンディングが使用されている。Therefore, wire bonding or face-down bonding is used to connect IC circuits.

また更に構成素子数の多いＬＳＩやＶＬＳ　Ｉになると
端子数が数百にも達するのでワイヤボンディングは工数
が掛り過ぎて無理であり、効率の良いフェイスダウンボ
ンディング法が普及しつつある。Furthermore, when LSIs and VLSIs have a large number of constituent elements, the number of terminals reaches several hundreds, making wire bonding impossible as it requires too much man-hours, and the highly efficient face-down bonding method is becoming popular.

本発明はプリント配線基板（以下略して基板）の上にチ
ップを装着してワイヤボンディング法により回路接続を
行う場合の装着方法に関するものである。The present invention relates to a mounting method for mounting a chip on a printed wiring board (hereinafter simply referred to as a board) and making circuit connections using a wire bonding method.

〔従来の技術〕[Conventional technology]

第２図はチップ１を基板２の上のステージ３に接着固定
した後にチップ１の周辺に設けられているパッド４と導
体パターン５の先端に形成されているリード部６とを金
線などのワイヤ７を用いてワイヤボンディングした状態
を示している。FIG. 2 shows that after the chip 1 is adhesively fixed to the stage 3 on the substrate 2, the pads 4 provided around the chip 1 and the lead portion 6 formed at the tip of the conductor pattern 5 are connected using gold wire or the like. A state in which wire bonding is performed using wire 7 is shown.

ここでワイヤボンディングには常温で超音波熔接する場
合と加熱しながら超音波熔接する場合とがあるが、金線
＜Ａｕ　）を用いる場合は後者の方法がとられている。Here, wire bonding can be carried out by ultrasonic welding at room temperature or by ultrasonic welding while heating, and the latter method is used when gold wire <Au 2 ) is used.

すなわち溶融して丸くなった金線の先端をチップのパッ
ド４に超音波熱圧着した後に機械的に比較的安定な導体
パターンのリード部６にまで金線を引き、超音波熱圧着
することにより第２図に示すようなワイヤ接続が行われ
ている。That is, by ultrasonic thermocompression bonding the tip of the molten and rounded gold wire to the pad 4 of the chip, the gold wire is drawn to the lead portion 6 of the mechanically relatively stable conductor pattern, and ultrasonic thermocompression bonding is performed. Wire connections are made as shown in FIG.

なお図においては一個所のみのボンディングを示し、他
は省略しである。Note that the figure shows bonding at only one location, and the other locations are omitted.

ここで従来は基板の厚さが充分あるためボンディング不
良は発生しなかったが、使用する基板が薄くなるに従っ
てボンディング不良が発生すると云う問題が生してきた
。Here, in the past, bonding defects did not occur because the substrate was sufficiently thick, but as the substrate used became thinner, bonding defects occurred, which became a problem.

すなわち基板の材料としてガラスエポキシが使用される
ことが多いが、フレキシブルプリント板のような用途の
場合は厚さが０．１１程度のものが使用されており、こ
の上に厚さが２０μｍの銅箔（Ｃｕ）を接着して基板が
作られている。In other words, glass epoxy is often used as the substrate material, but for applications such as flexible printed boards, a material with a thickness of about 0.11 is used, and on top of this glass epoxy with a thickness of 20 μm is used. The substrate is made by bonding foil (Cu).

このように薄い基板２のステージ３にチップ１を接着剤
により固定したのち、ワイヤボンディングを行うために
基板を２００℃以上にまで加熱すると基板２が薄いこと
に加え、基板の成分であるエポキシが軟化するので超音
波熱圧着に際して超音波の減衰が甚だしく、所定の接着
力を得ることができない。そこで基板加熱温度を成るべ
く低い温度例えば１５０　’Ｃにまで下げて熱圧着を行
っているが、基板が柔らかいために良好な接着を得には
充分な注意を必要としている。After fixing the chip 1 to the stage 3 of the thin substrate 2 with adhesive, when the substrate is heated to 200°C or higher to perform wire bonding, not only the substrate 2 is thin, but the epoxy component of the substrate is also damaged. Since it is softened, the ultrasonic waves are attenuated significantly during ultrasonic thermocompression bonding, making it impossible to obtain a predetermined adhesive force. Therefore, thermocompression bonding is performed by lowering the heating temperature of the substrate to as low as possible, for example, 150'C, but since the substrate is soft, sufficient care is required to obtain good adhesion.

また図に示すようにリード部６の裏面に導体パターン５
が存在しない場合は熱圧着に当たって基板２が沈み込み
、ボンディング装置からの超音波振動が充分に伝わらな
い問題があった。Also, as shown in the figure, a conductor pattern 5 is provided on the back side of the lead part 6.
If there is no bonding, there is a problem that the substrate 2 sinks during thermocompression bonding, and the ultrasonic vibrations from the bonding device are not sufficiently transmitted.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

本発明に係る問題点は厚さが数１００μｍのように薄い
合成樹脂製の基板上の配線パターンに充分な接着力を持
つワイヤボンディングを行う方法を開発することである
。The problem with the present invention is to develop a method for wire bonding with sufficient adhesion to a wiring pattern on a synthetic resin substrate as thin as several 100 μm in thickness.

〔問題点を解決するだめの手段〕[Failure to solve the problem]

−Ｆ記の問題点は半導体チップを回路基板に接着したる
のち該回路基板上にパターン形成してなるリード部と半
導体チップのパッド部とを回路接続するに当たり、前記
回路基板のり一ト部パターンの裏面位置に予め該リード
部を覆う補強用パターンを形成しておきワイヤボンディ
ングを行うことにより解決することができる。- The problem described in F is that when a semiconductor chip is bonded to a circuit board and then a pattern is formed on the circuit board to make a circuit connection between the lead part and the pad part of the semiconductor chip, the pattern of the adhesive part of the circuit board is This problem can be solved by forming a reinforcing pattern to cover the lead part in advance on the back side of the lead part and then performing wire bonding.

〔作用〕[Effect]

本発明は現在殆どの基板が両面基板であることから、ワ
イヤボンディングを行う導体パターン５のリード部６が
設けられている基板の裏面部にもしもなんらかのパター
ンが存在してない場合、この位置に補強用のダミーパタ
ーンを形成することによって実効的に超音波熱圧着が行
われる基板の硬度を高めるものである。Since most of the current boards are double-sided boards, if there is no pattern on the back side of the board where the lead part 6 of the conductor pattern 5 for wire bonding is provided, reinforcement will be required at this position. By forming a dummy pattern for this purpose, the hardness of the substrate on which ultrasonic thermocompression bonding is effectively performed is increased.

〔実施例〕〔Example〕

第１図は本発明に係る装着構造を示すもので同図（Ａ）
は平面図また（Ｂ）は側面図である。FIG. 1 shows the mounting structure according to the present invention, and FIG.
is a plan view, and (B) is a side view.

すなわちチップ１に設けられている複数個のパッド４と
基板２の上のリード部６とをワイヤ７により超音波熱圧
着した状態を示している。That is, a state in which a plurality of pads 4 provided on a chip 1 and a lead portion 6 on a substrate 2 are bonded by ultrasonic thermocompression using a wire 7 is shown.

本発明はかかる超音波熱圧着を行うに先立ち、予めリー
ド部６に相当する裏面位置に破線で示す補強用パターン
８を設けておくことにより接着強度を向上するものであ
る。The present invention improves the adhesive strength by providing a reinforcing pattern 8 indicated by a broken line on the back side corresponding to the lead portion 6 before performing such ultrasonic thermocompression bonding.

ここで補強用パターン８は通常のパターン形成と同時に
写真食刻技術を用いて作ればよく、またその位置に他の
パターンがあればそれで代用できる。Here, the reinforcing pattern 8 may be formed using photolithography at the same time as normal pattern formation, and if there is another pattern at that position, it can be used instead.

このようにして基板の強度を補強すると基板の厚さが薄
＜、また軟らかな場合であっても効率よくボンディング
を行うことができる。By reinforcing the strength of the substrate in this way, efficient bonding can be performed even when the substrate is thin or soft.

〔発明の効果〕〔Effect of the invention〕

以上述べたように本発明の実施により基板強度を補強す
ることができ、そのため金線を使用してワイヤボンディ
ングを行う場合、従来の方法では基板温度を１５０°Ｃ
以下に下げてホンディングを行う必要があったが、本発
明の実施により２００°Ｃ程度にあげることが可能とな
り、充分な接着強度を持たせることが可能となった。As described above, by carrying out the present invention, the substrate strength can be reinforced. Therefore, when wire bonding is performed using gold wire, the substrate temperature is lowered to 150°C in the conventional method.
Although it was necessary to perform honding at a temperature below 200°C, by implementing the present invention, it has become possible to raise the temperature to about 200°C, and it has become possible to provide sufficient adhesive strength.

【図面の簡単な説明】[Brief explanation of drawings]

第１図は本発明を実施して半導体チップのボンディング
を行う状態を示す説明図で、同図（Ａ）は平面図、同図
（Ｂ）は側面図。 第２図は従来法を説明する側面図である。 図において １はチップ、　　　　　　２はプリント配線基板、４は
パッド、　　　　　　６はリード部、７ばワイヤ、　　
　　　　８は補強パターン、である。 第１図 美２１に プリント曹乙Ｃ艮渥４旦FIG. 1 is an explanatory diagram showing a state in which semiconductor chips are bonded by implementing the present invention, in which FIG. 1A is a plan view and FIG. 1B is a side view. FIG. 2 is a side view illustrating the conventional method. In the figure, 1 is a chip, 2 is a printed wiring board, 4 is a pad, 6 is a lead part, 7 is a wire,
8 is a reinforcement pattern. Figure 1: Mei 21 printed on Cao E C Ai Yu 4 Dan

Claims (1)

【特許請求の範囲】[Claims] 半導体チップを回路基板に接着したるのち、該回路基板
上にパターン形成した配線パターンのリード部と半導体
チップのパッド部とを回路接続するに当たり、前記回路
基板のリード部パターンの裏面位置に予め該リード部を
覆う補強用パターンを形成しておきワイヤボンディング
を行うことを特徴とする半導体装置の製造方法。After bonding a semiconductor chip to a circuit board, in order to make a circuit connection between the lead part of the wiring pattern formed on the circuit board and the pad part of the semiconductor chip. A method of manufacturing a semiconductor device, comprising forming a reinforcing pattern covering a lead portion and then performing wire bonding.
JP59127825A 1984-06-21 1984-06-21 Manufacture of semiconductor device Pending JPS616834A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP59127825A JPS616834A (en) 1984-06-21 1984-06-21 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59127825A JPS616834A (en) 1984-06-21 1984-06-21 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPS616834A true JPS616834A (en) 1986-01-13

Family

ID=14969598

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59127825A Pending JPS616834A (en) 1984-06-21 1984-06-21 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS616834A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02120868U (en) * 1989-03-15 1990-09-28
JPH03102768U (en) * 1990-02-09 1991-10-25
JPH05118936A (en) * 1991-10-25 1993-05-14 Yamatake Honeywell Co Ltd Thin film diaphragm

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02120868U (en) * 1989-03-15 1990-09-28
JPH03102768U (en) * 1990-02-09 1991-10-25
JPH05118936A (en) * 1991-10-25 1993-05-14 Yamatake Honeywell Co Ltd Thin film diaphragm

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