JPS6167346A - Receiving circuit of high-impedance bus - Google Patents

Abstract

PURPOSE:To prevent wrong reception of a false signal, by shifting a gate which transmits binary signals from a conducted condition to inhibited condition by putting off the shifting from the terminating time of reception permissible time and inhibiting gate output signals. CONSTITUTION:When switch controlling section (SWC) gives a setting command of a channel to a required network (NW), a timing circuit (TMG) inputs a wake-up signal in a monostable multivibrator (MV). The MV transmits a signal (w) of high level of a delay circuit (DL) and gate (G3) during reception permissible time (T) only. Simultaneously, the MV supplies another signal whose level is opposite to the signal (w) to an FF2. The circuit DL delays the signal (w) by a delaying time Td and transmits the delayed signal (w) to the G3 and sets a gate (G1) to a conducted condition by giving a high-level signal W1 to the G1 during the time T+Td. The FF2 gives a signal f2 which changes from high level to low level when the time T is completed to a gate (G4)so as to inhibit the input of the output signal g1 of the G1 in an FF1 and absorbs false signals produced during the period.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an improvement in a receiving circuit for a high impedance bus.

When transmitting binary signals defined by levels H and L transmitted from a plurality of devices to a set of receiving circuits via a bus, if each of the devices does not transmit a binary signal, the output to the bus is The impedance is often set to a high impedance state so as not to affect the binary signal sent out by any one device. In a state where all such devices do not send out binary signals, unless the receiving circuit has a bias circuit for level guarantee at the input section from the bus, it cannot be determined whether level H or L is received, and the receiving circuit It is determined that any level has been received according to the characteristics of the signal.

[Conventional technology]

FIG. 3 is a diagram showing an example of a conventional high-impedance lotus receiving circuit, and FIG. 4 is a diagram showing an example of output signals of each part in FIG. 3. In FIG. 3, a network NW of electronic exchanges serves as a plurality of devices that send binary signals to the bus, and a switch control unit SWC of the network NW serves as a device that has a circuit that receives binary signals arriving from the bus. It is shown. Furthermore, the binary signals sent from each network NW are sent to the switch control unit S.
When the WC transmits an instruction to set up a communication path to a required network NW, this is a response signal sent back from the network NW. Note that network NW is bus B1.
When sending out a response signal via bus B2, a condition code (3 bits) indicating the state within the network NW is also sent out via bus B2. Each bit constituting the condition code is also indicated by two values, level H and level L. For example, each bit of the condition code indicating that the state within the network NW is normal is set to level L, level L, and level H, respectively.

In FIG. 3, each network NW sends a response signal to the bus B1 via the cable driver CDI, and also sends a condition code to the bus B2 via the cable driver CD2. The switch control unit SWC is connected to bus B.
A binary signal arriving from bus B2 is received by cable receiver CR1, and a binary signal arriving from bus B2 is received by cable receiver CR2. Note that when the cable drivers CDI and CD2 do not send out a response signal or condition code, they enter a high impedance state with respect to the lotus B1 or B2.

In FIGS. 3 and 4, when the switch control unit SWC transmits the setting instruction for the communication path to the required network NW at time t1, the timing circuit TMG inputs an activation signal to the terminal C of the monostable multi-pie break MV. do. The monostable multi-high break MV that has received the activation signal sets the output signal W at the terminal Q to level H for a reception allowable time T after time L1, and makes the gate G1 conductive. On the other hand, the network NW that has received the instruction sets the communication path based on the instruction, and then puts the cable drivers CDI and CD2 into a high impedance state. Next, when the startup conditions are met and the gates of cable drivers CDI and CD2 are enabled, the cable driver CDI
After setting the signal to a ringing state, the cable driver CD2 sends out a response signal by changing the level to the H state for a short time, and the cable driver CD2 quickly outputs fixed data indicating a normal state. When the response signal is normally transmitted to the switch control unit SWC, the output signal a of the cable receiver CR1
changes as shown by the dotted line in FIG. 4 between time points t2 and t5, and is transmitted to the gate G1. If the response signal is not sent from the network NW for some reason, the cable driver CDI maintains the high impedance state during the reception/reception allowable time T. In such a case, the cable receiver CRI maintains the output signal a at the level H muff', :HA level L according to its own characteristics. now cable receiver C
If the output signal a of RI is maintained at level H, the output signal g of game 1-G1 which is normally maintained at level H
1 is set to level L during the reception permissible time T, and time t6
Return to level H. The output signal g1 is input to the terminal C of the flip-flop FFI. flip flop FF
When the input signal to the terminal C changes from the level L to the level H, the output signal f1 from the terminal Q, which is normally set to the low level, is set to the high level input to the terminal Q. The output signal f1 is transmitted to the signal detection circuit C.HK via the gate G2, which is set to a conductive state when the cable receiver CR2 receives a condition code indicating a normal state of the network NW. When the transmitted output signal f1 changes from level L to level H, the signal detection circuit CHK determines that the operation based on the instruction received by the network NW has been successfully completed, and resets the timing circuit TMG.

[Problem that the invention seeks to solve]

As is clear from the above explanation, in the conventional bi-impedance bus receiving circuit, there is a swivel.

Even if the network NW that has received the instruction from the channel control unit SWC does not send out a response signal and maintains the cable driver CDI in a high impedance state, if the output signal a of the cable receiver CRI is maintained at level H, , when the gate G1 changes from the conductive state to the blocked state at the end point t6 of the permissible reception time T, the output signal gl goes to the level L.
to level I] and change the output signal r1 of the flip-flop FFI from level L to level H, there was a risk that the signal detection circuit CHK would erroneously determine that the response signal was sent normally.

[Means for solving problems]

The present invention is a circuit that receives a binary signal transmitted via a lotus from a device whose output impedance becomes high impedance when not transmitting a signal, via a gate that becomes conductive only for a predetermined reception allowable time. means for delaying the point at which the gate transitions from a conductive state to a blocking state from the end of the permissible reception time, and means for blocking an output signal of the gate after the end time, and the gate is in a conductive state. This problem is solved by absorbing the pseudo signal of the binary signal that is output when transitioning from the state to the blocking state.

[Effect]

That is, according to the present invention, a gate that transmits a binary signal shifts from a conductive state to a blocked state with a delay from the end of an allowable reception time, and the output signal of the gate is blocked after the end of an allowable reception time. This prevents false signals from being erroneously received, which may occur when the gate shifts from the pass state to the block state.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a diagram showing a high impedance bus receiving circuit according to an embodiment of the present invention, and FIG. 2 is a diagram showing an example of output signals of each part in FIG. 1. Note that the same reference numerals indicate the same objects throughout the figures. In Figure 1,
A delay circuit DL that gives a delay time "Td" to the output signal W of the monostable multi-high break MV, and a flip-flop that blocks the input of the output signal g1 of the gate Gl to the flip-flop FFI after the end time t6 of the allowable reception time T. FF
2 and a gate G4 are provided.

In FIGS. 1 and 2, when the switch control unit SWC transmits the setting instruction for the communication path to the required network NW at time t1, the timing circuit TMG inputs an activation signal to the terminal C of the monostable multi-bi break MV. . The monostable multi-high break MV that has received the activation signal sets the output signal W at the terminal Q to the level H for the reception allowable time T after time t1, transmits it to the delay circuit DL and gate 03, and outputs the output signal from the terminal Q°. The signal W° is set to the opposite level to the output signal W, and is input to the terminal C of the flip-flow knob FF2. The delay circuit DL delays the received output signal W of the monostable multi-bibreak MV by a delay time Td and transmits the delayed signal to the gate G3.

As a result, gate G3 transmits output signal W1 set at level H to gate G1 from time t1 to time t7, which is a delay time Td after time t6, and makes gate G1 conductive. Furthermore, the flip-flop FF2 has a terminal C
The output signal W which is input manually.

At time t6 when the level changes from the level L to the level H, the output signal r2 of the terminal Q', which is normally set to the level H, is changed to a low level. The output signal f2 is transmitted to the gate G4 and sets the gate G4 in a conductive state until time t6.
After time t6, the state is blocked, and the output signal g of gate G1 is
'l is prevented from being transmitted to flip-flop FFI. On the other hand, if the network NW that has received the instruction does not send out a response signal for some reason, the cable driver CDI maintains the high impedance state during the reception allowable time T. In such a case, the cable receiver CRI maintains the output signal a at level H or level L depending on its own characteristics. Now cable receiver CRI output signal a
is maintained at level H, the output signal g1 of gate Gl, which is normally maintained at level H, is set at level L from time t1 for reception allowable time T and delay time Td, and returns to level H at time t7. . The output signal g1 is input to the gate G4. Since the gate G4 is in a conductive state until time t6, the output signal gl of the gate G1 is input to the terminal C of the flip-flop FFI, but after the time t6, it is in a blocked state and the output signal g2 is maintained at level L. Therefore, the transition of the output signal g1 from level L to level H at time t7 is not input to terminal C of flip-flop FFI. Therefore, the flip-flop FFI maintains that the input signal to the terminal C changes from the level L to the level H during the reception allowable time T.
Since it does not change, the output signal r1 from terminal Q is set to level L.
to be maintained. The output signal f1 is transmitted to the cable receiver CR
Gate G that is set to a conductive state when Gate 2 receives a condition code indicating a normal state of the network NW.
2 to the signal detection circuit CHK. The signal detection circuit CHK determines that the network NW does not normally complete the operation based on the received instruction because the transmitted output signal f1 does not change from level L to level H.

As is clear from the above description, according to this embodiment, the network NW does not normally send out a response signal, the cable driver CDI is maintained at high impedance, and the output signal a of the cable receiver CRI of the switch control unit SWC is Even when the level H is maintained during the reception allowable time T, there is no possibility that the signal detection circuit CHK will erroneously determine that the response signal has been sent normally.

Note that FIGS. 1 and 2 are only one embodiment of the present invention, and for example, the output signals of each part are not limited to those shown, and many other modifications may be considered. In either case, the effects of the present invention remain the same. It goes without saying that the object of the present invention is not limited to the path connecting the network NW of the electronic exchange and the switch control unit SWC.

〔Effect of the invention〕

As described above, according to the present invention, it is possible to realize a receiving circuit in which binary signals are not received erroneously even when the bus is in a high impedance state.

[Brief explanation of drawings]

FIG. 1 is a diagram showing a high impedance bus receiving circuit according to an embodiment of the present invention, FIG. 2 is a diagram showing an example of output signals of each part in FIG. 1, and FIG. 3 is a diagram showing a conventional high impedance bus receiving circuit. A diagram showing an example of the circuit, Figure 4 is the third
It is a figure which shows an example of the output signal of each part in a figure. In the figure, a, fl, f2, gl, B2, W, wl and wl are output signals, B1 and B2 are Hashus, CDI and CD2 are cable drivers, CR1 and CR2 are cable receivers, DL is a delay circuit, FFI and FF
2 is a flip-flop, G1 to G4 are gates, H and L are levels, M is a monostable multipipe lake, NW
is the network, SWC is the switch control unit, T is the reception allowable time, tl to tl are the time points, Td is the delay time, TMG
indicates a timing circuit. 22 poles 42 fl'L

Claims (1)

[Claims] In a circuit that receives a binary signal transmitted via a bus from a device whose output impedance becomes high impedance when not transmitting a signal, through a gate that becomes conductive only for a predetermined reception allowable time, the gate means for delaying the time when the gate shifts from a conductive state to a blocked state from the end of the permissible reception time, and means for blocking an output signal of the gate after the end time, and the gate changes from a conductive state to a blocked state. A receiving circuit for a high impedance bus, characterized in that it absorbs a pseudo signal of the binary signal outputted during transition.