JPH0317428B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an improvement in a receiving circuit for a high impedance bus.

When transmitting binary signals defined by levels H and L transmitted from a plurality of devices to a set of receiving circuits via a bus, if each of the devices does not transmit a binary signal, the output to the bus is The impedance is often set to a high impedance state so as not to affect the binary signal sent out by any one device. In a state where all such devices do not send out binary signals, unless the receiving circuit has a bias circuit for level guarantee at the input section from the bus, it cannot be determined whether level H or L is received, and the receiving circuit It is determined that any level has been received according to the characteristics of the signal.

[Conventional technology]

FIG. 3 is a diagram showing an example of a conventional high-impedance bus receiving circuit, and FIG. 4 is a diagram showing an example of output signals of each part in FIG. 3. In Figure 3, a network NW of electronic exchanges is used as a plurality of devices that send binary signals to the bus.
Further, a switch control unit SWC of the network NW is shown as a device having a circuit for receiving a binary signal arriving from the bus. Furthermore, the binary signal sent from each network NW is a response signal sent back from the network NW when the switch control unit SWC transmits an instruction to set up a communication path to one required network NW. . Note that when the network NW sends a response signal via bus B1, it sends a condition code (3) indicating the state within the network NW via bus B2.
bits) are also sent. Each bit constituting the condition code also has level H and level L.
It is indicated by the binary value of . For example, network NW
The respective bits of the condition code indicating that the condition within is normal are set to level L, level L, and level H, respectively.

In Figure 3, each network NW sends a response signal to bus B1 via cable driver CD1, and also sends a response signal to bus B via cable driver CD2.
Sends a condition code to 2. The switch control unit SWC receives a binary signal arriving from bus B1 by cable receiver CR1, and receives a binary signal arriving from bus B2 by cable receiver CR1.
Received by CR2. . In addition, the cable driver
When CD1 and CD2 do not send out a response signal or condition code, they are in a high impedance state with respect to bus B1 or bus B2.

In FIGS. 3 and 4, the switch control section
When the SWC transmits the communication path setting instruction to the required network NW at time t1, the timing circuit TMG inputs an activation signal to the terminal C of the monostable multivibrator MV. The monostable multivibrator MV, which has received the activation signal, keeps the output signal w at the terminal Q at the level H for the reception allowable time T after time t1.
, and the NAND gate (hereinafter referred to as gate G1) is made conductive. On the other hand, the network NW that has received the instruction sets the communication path based on the instruction, and then puts the cable driver CD1 and the cable driver CD2 into a high impedance state. Next, when the start-up conditions are set and the gates of cable drivers CD1 and CD2 are enabled, cable driver CD1 will temporarily go to level L.
After the cable driver CD2 is set to the state, a response signal is sent by changing the level to the H state for a short time, and the cable driver CD2 also sends out fixed data indicating the normal state. The response signal is normally switched to the control unit
Cable receiver if communicated to SWC
The output signal a of CR1 changes as shown by the dotted line in FIG. 4 between time points t2 and t5, and is transmitted to the gate G1. If a response signal is not sent from the network NW for some reason, the cable driver
CD1 maintains a high impedance state during the reception allowable time T. In such a case, the cable receiver CR1 maintains the output signal a at level H or level L depending on its own characteristics. Assuming that the output signal a of the cable receiver CR1 is now maintained at level H, the output signal g1 of gate G1, which is normally maintained at level H, is set to level L for the reception allowable time T, and becomes level H at time t6. return. The output signal g1 is input to the terminal C of the flip-flop FF1. Flip-flop FF1 changes when the input signal to terminal C changes from level L to level H.
The output signal f1 from terminal Q, which is normally set to level L, is set to level H, which is input to terminal D. The output signal f1 is sent to the cable receiver CR2
The signal is transmitted to the signal detection circuit CHK via the gate G2, which is set to a conductive state when the condition code indicating the normal state of the network NW is received. When the transmitted output signal f1 changes from level L to level H, the signal detection circuit CHK determines that the operation based on the instruction received by the network NW has been successfully completed, and the timing circuit TMG
to reset.

[Problems solved by the invention]

As is clear from the above explanation, in conventional high-impedance bus receiving circuits, the network that receives instructions from the switch control unit SWC
NW does not send response signal and cable driver
Even when CD1 is maintained in a high impedance state, if the output signal a of the cable receiver CR1 is maintained at level H, the gate G1 changes from the conductive state to the blocking state at the end of the reception allowable time T, t6. When the output signal g1 changes from level L to level H
Since the output signal f1 of the flip-flop FF1 changes from level L to level H, there is a possibility that the signal detection circuit CHK may erroneously determine that the response signal has been sent normally.

[Means for solving problems]

The present invention maintains a high level when no significant signal arrives from a high-impedance bus, changes to a low level for a short time, and then returns to a high level again when a significant signal arrives from the high-impedance bus. input to one input terminal, changes from a low level to a high level at the start of the reception permissible time period of a significant signal arriving from the high impedance bus, and becomes high level after a predetermined time from the end of the reception permissible time period. Input a signal that changes from to low level to the second input terminal.
A NAND gate, and an output signal from the NAND gate is input to a first input terminal, and the signal is maintained at a high level before the end of the permissible reception time period and changes from high level to low level at the end of the permissible reception time period. input to the second input terminal
and a determination circuit that determines that a significant signal has arrived from the high-impedance bus when the input signal changes from a low level to a high level during the reception permissible time period. The above problem is solved by inputting it as an input signal.

[Effect]

That is, according to the present invention, since the signal input to the second input terminal of the AND gate changes from a high level to a low level at the end of the reception permissible time period,
Even if the output signal from the NAND gate changes from low level to high level after the end of the permissible reception time period, the output signal from the AND gate will not change from low level to high level and will be input to the judgment circuit. The signal is prevented from changing from a low level to a high level at the end of the permissible reception time period.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a diagram showing a high impedance bus receiving circuit according to an embodiment of the present invention, and FIG. 2 is a diagram showing an example of output signals of each part in FIG. 1. Note that the same reference numerals indicate the same objects throughout the figures. In FIG. 1, there is a delay circuit DL that gives a delay time Td to the output signal w of the monostable multivibrator MV, and a flip-flop circuit that transmits the output signal g1 of the gate G1 from point 6 onwards at the end of the permissible reception time T.
A flip-flop FF2 and an AND gate (hereinafter referred to as gate G4) are provided to block input to FF1.

In Figures 1 and 2, the switch control section
When the SWC transmits the communication path setting instruction to the required network NW at time t1, the timing circuit
TMG is terminal C of monostable multivibrator MV
Input the start signal to. The monostable multivibrator MV that has received the activation signal sets the output signal w at the terminal Q to the level H for the reception allowable time T after time t1, transmits it to the delay circuit DL and the gate G3, and at the same time sets the output signal w at the terminal Q' to the level H. The signal w' is set to the opposite level to the output signal w, and is input to the terminal C of the flip-flop FF2. The delay circuit DL converts the received output signal w of the monostable multivibrator MV to a delay time Td.
, and then transmits it to gate G3. As a result, gate G3 has a delay time Td from time t1 to time t6.
The output signal w1, which is set at level H, is transmitted to the gate G1 until a time point t7 later, and the gate G1 is rendered conductive. Also, flip-flop FF2 has terminal C
At time t6 when the output signal w' inputted to the terminal changes from the level L to the level H, the output signal f2 of the terminal Q', which is normally set to the level H, is changed to the level L. The output signal f2 is transmitted to the gate G4, and at the time t6
Until then, gate G4 is set to conductive state, but at time t6
Thereafter, it is set in a blocking state, and the output signal g1 of gate G1 is prevented from being transmitted to flip-flop FF1. On the other hand, the network NW that received the above instruction
However, if the response signal is not sent for some reason, the cable driver CD1 maintains a high impedance state even during the reception allowable time T. In such a case, the cable receiver CR1 maintains the output signal a at level H or level L depending on its own characteristics. Assuming that the output signal of the cable receiver CR1 is now maintained at level H, the output signal g1 of gate G1, which is normally maintained at level H, is set at level L for the reception allowable time T and delay time Td from time t1, Returns to level H at time t7. The output signal g1 is
Input to gate G4. Since gate G4 is in a conductive state until time t6, the output signal g1 of gate G1 is input to terminal C of flip-flop FF1, but after time t6, it is in a blocked state, and in order to maintain the output signal g2 at level L, The transition of the output signal g1 from level L to level H at time t7 is caused by a flip-flop.
It is not input to terminal C of FF1. Therefore, flip-flop FF1 maintains the output signal f1 from terminal Q at level L because the input signal to terminal C does not change from level L to level H during the reception allowable time T. The output signal f1 is transmitted to the signal detection circuit CHK via a gate G2 which is set to a conductive state when the cable receiver CR2 receives a condition code indicating a normal state of the network NW. The signal detection circuit CHK detects the transmitted output signal
Since f1 does not change from level L to level H, it is determined that the network NW will not normally complete the operation based on the received instruction.

As is clear from the above description, according to this embodiment, the network NW does not normally send out a response signal, and the cable driver CD1 is maintained at high impedance, and the output signal a of the cable receiver CR1 of the switch control unit SWC is Even if CHK is maintained at level H during the reception allowable time T, the signal detection circuit CHK
This eliminates the possibility that the response signal will be mistakenly determined to have been sent normally.

Note that FIGS. 1 and 2 are only one embodiment of the present invention, and for example, the output signals of each part are not limited to those shown, and many other modifications may be considered. In either case, the effects of the present invention remain the same. It goes without saying that the object of the present invention is not limited to the bus that connects the network NW of an electronic exchange and the switch control unit SWC.

[Effects of the Invention] As described above, according to the present invention, it is possible to realize a receiving circuit in which binary signals are not received erroneously even when the bus is in a high impedance state.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing a high-impedance bus receiving circuit according to an embodiment of the present invention, FIG. 2 is a diagram showing an example of output signals of each part in FIG. 1, and FIG. 3 is a diagram showing a conventional high-impedance bus reception circuit. FIG. 4 is a diagram showing an example of the circuit, and FIG. 4 is a diagram showing an example of output signals of each part in FIG. 3. In the figure, a, f1, f2, g1, g2, w, w' and w1 are output signals, B1 and B2 are buses, CD1 and CD2 are cable drivers, CR1 and CR2 are cable receivers, DL is delay circuit FF1 and
FF2 is a flip-flop, G1 to G4 are gates,
H and L are levels, MV is a monostable multivibrator, NW is a network, SWC is a switch control unit, T is a reception allowable time, t1 to t7 are time points,
Td indicates delay time and TMG indicates timing circuit.

Claims (1)

[Claims] 1 A first input signal that is maintained at a high level when no significant signal arrives from the high-impedance bus, changes to a low level for a short time, and then returns to a high level again when a significant signal arrives from the high-impedance bus. A significant signal that is input to a terminal and arrives from the high impedance bus changes from a low level to a high level at the start of a reception permissible time period, and from a high level to a low level after a predetermined time from the end of the reception permissible time period. a NAND gate that inputs a signal that changes to a second input terminal, and an output signal from the NAND gate that is input to a first input terminal, and is maintained at a high level before the end of the reception permissible time period; an AND gate that inputs a signal that changes from a high level to a low level at the end point to a second input terminal; 1. A receiving circuit for a high-impedance bus, characterized in that the input signal is inputted as an input signal to a determination circuit that determines that a significant signal has arrived from the high-impedance bus when the level changes.