JPS6167321A - Josephson ad converter circuit - Google Patents

Abstract

PURPOSE:To perform A/D conversion at a high speed, by connecting Josephson gate circuits, each of which is equipped with a control line, to the outputs of (n) pieces of control-line-equipped Josephson gate circuits and supplying a pulse bias to a bias current line. CONSTITUTION:Control-line-equipped Josephson gate circuits Q1-Qn, each of which has a bias current line 1 and control current lines 2 and 3 and takes a zero-voltage or voltage-existing condition at its output terminal in accordance with the '1' or '0' supplied to the current line 2, are respectively connected with outputs of control-line-equipped Josephson gate circuits M1-Mn. Analog input currents Is are supplied to input current lines 12 of the circuits M1-Mn and a narrow-width pulse bias current Ib is supplied to a bias current line 11 from a pulse bias current generating circuit D. Digital outputs corresponding to the values of the currents Is are obtained as the outputs of the circuit M1-Mn and the output digital signals are supplied to the circuits Q1-Qn through the current lines 2. AC bias currents Ia are supplied to the current lines 1 of the circuits Q1-Qn and digital signals corresponding to the input signals of the current lines 2 are supplied to output loads L1-Ln of the circuits Q1-Qn.

Description

DETAILED DESCRIPTION OF THE INVENTION The industrial application field of the present invention (1.
This invention relates to a Josephson gate circuit constructed by i'+.

0 is a Josephson gate circuit constructed using a Josephson junction element. Conventionally, a construction similar to that described below with reference to FIG. 1 has been proposed.

i7 has a bias current line 1 and 2+ control current lines 2 and 3; Depending on the supplied bias current 1t+, a zero voltage state or a voltage state is taken between the C1 outputs 4 and 4', and the VJA value characteristic that takes that zero voltage state or a voltage state is A control line with a plurality of n control lines constructed using di-1 Hifson junction elements having mutually different periodicities for the value of the control current IC supplied to the current line 2.
Josephson gate circuit ~1, M2...Mo.

In this case, Josephson gate circuit with control line M, M2.
...M, G, as mentioned above, depending on the value of the control current IC supplied to the control current line 2 and the value of the bias current 11) supplied to the bias current line 1, the output terminal 4 and 4', the control current or A1 voltage state is taken, and the threshold characteristic that takes the zero voltage state or A1 voltage state is such that the control current IC supplied to the current line 2 is immediately connected to J Now, the control 21I line I, Jji, Ref Song-1-Circuit M,
(r=1゜2...n) The period of the threshold characteristic described above is 1
゜, the period Ji is, as shown in Figure 2,
2(il)X [has a period of 1.

Also, 1ilIiIII with line ]t? The above-mentioned period 1 (=2””X
■ The periodicity with [,) is shown in the limiting current line 3 (go, (9
As described above, since the current 1f from the bias current line 131 is supplied at IiQ I (', J is 1 of the current 16 for limiting i, as shown in FIG.
If 1r1 is 1r1, the bias current 1b is lin I
It has a phase of l+'.

In this way, the structure with 41 control lines is a fuson gate circuit ~1. As an example, the configuration shown in FIG.

71, 1, the JJ Lefson junction 6 is inserted in the bias current line 5, and the control voltage 2J'ii Yl!
7 and 8 are magnetically coupled and the three control 211 lines that make the result 1 are Joseph Song-1 circuit', F2 and F.

However, those Joreno Song 1-Circuit F1 ~ "3
The bias current line 5 is connected to 11 CITV11 as 1,
The column circuit is applied to the bias current line 1 mentioned above.

In addition, the control current lines 7 of Seal Leno Song-1~Circuit ``~''3 are connected in series to
It is inserted into the current line 2.

Furthermore, Josephson gate circuit r1-F3's 11+
11:11 current line 8 is connected in series to control current line 3 via 1ir+.

/@a3 Furthermore, the Josephson gate circuit “1~”・
The above-mentioned output terminals 4 and 4' are led out from both ends of the parallel circuit of the bias current line 5.

The above is Joseph Song Gour l-circuit fvl with control line.

-111I configuration.

The bias voltage of the control line bone Josephson gate circuit M1 to M, such as
As shown in the figure, the bias current line 1 is connected in series.
1 is inserted.

Also, 111111flll line to Jji] Kefuson game j.
The control current lines 2 of the circuits M1 to M1o are connected in series and inserted into the input current line 12.

Furthermore, the control current line 3 of the Joseph Song 1 circuit M with a control line is inserted into the control current line B.

In addition, the control line f, Jjikosefsonge-1・times Vif N
0 load is connected between both ends 4 and 1' of 4.

The above is the configuration of the Josephson conversion circuit that has been proposed so far.

According to the ΔD converter circuit having such a 4T configuration, the bias current line 11 (the bias current f
If b is supplied, Joseph Song 1-Circuit M with control line
A bias current Ib is supplied to the bias current line 1 of , at that value.

In addition, if analog input upstream I3 is supplied to input current line 12, analog input terminal IS is applied to control current line 2 of control circuit (Jicosef Song-1-Circuit M with 2Il line). It is supplied through other means.

Furthermore, if the &+J control current I is supplied to the control current lines B and +J, the control current (') is applied to the control line 3 of the Joseph Song circuit Mi with the control line II. Supplied by

For this reason, the bias current 1 to be supplied to the bias current line 11 is selected to be the above-mentioned 1st shift l', and b
b, control current line Bit 8, control current j1
J, and i
, upper j of Joseph Song gate circuit M with li 6tl line
The threshold characteristic described above has the same periodicity as described above in FIG. 2 for the analog input current I3 supplied to the input flow line 12.

That is, the axis of the control current IC in FIG.

Therefore, 1,'2 (7
) 1 shift 1. Also, if the 1st shift of the 7 log input current [,
slo S2' S, >...l
I'm sobbing.

2n O≦I, 1<I.

l ≦ 182 < 2XI.

2Xl sl S3<3Xl! 7 3　X　　　　≦1. <4XI.

4× 1g ≧ls5<5X[Q (21> ×f ≦I 〈2 XI g(l
s2' In that case, the Josephson gate circuit M1 with control line has an analog [1 input horn current 1] between its output terminals 1 and 4'.
But, f+rfl 1S sl・s3・
'S5°°゛°°.

...'S(2'A>, it assumes a zero voltage state, but 1 shift's2.'s4...1 is 16
When the voltage is 2n, the voltage is applied as shown by the X mark in FIG. 2A.

In addition, the control 2T+A equipped Jiwhite Sefsong-1・Circuit~・1
2 (between its output terminals 4 and 4', the analog flow rate t is fin I?kU?, 2. I3
571U I 36゜S sl ``'``'''''' s (2 days - 31 and ' s (2 row 2) TlL - (if there is, '7. Voltage state is taken, but l17i 1 and IS, + s4・ 's7 and '38°''”'”'”' ”
” If you have S(2ro -1) and 132o,
The voltage state is indicated by the x mark in Figure 2B.

In addition, the T3 reflex song game with control line - 1- circuit ~ 131
The analog input current I between output terminals 4 and 1' (T) is 1,1~'s4.'s9~1,12...
``'''s(2n-7) If s(2'-4) is on the right - ■, it takes a zero voltage state, but 's5~'sL'sl~I
...' Take s(2"・3)~r 3
sl6 s2
In the case of τ, the voltage state is returned to as shown by the X mark in FIG. 2C.

In this way, the Joseph Song-1 circuit Mi with powder control has a non-non-analog input current of 1.
But 'slゝrs2+++-++ ' 5(2x2 `` ''' +11 5(3x
2"-th) If it has a value of 1, it assumes a zero voltage state.

In addition, a, the control powder-equipped jacket 1/circuit ~1° has an analog human horn current Is between its output terminals 4 and 4'.
However, [S(2+・"+11~'5(2x2 ""
)・〜 ■ '! ;(3x2 ” 111 5(4x2 ”
” ) ~ 1 ' 5 (5x2 ” '■ +1) 5 (GX2
"" ), if you have 11r1, a electric 1
Takes 1 state.

Therefore, now, the control l line (= J register - 1? Fusonge 1
When ~circuit M1・~~1o assumes the zero-voltage H- state, a blue undulating voltage (zero voltage) is generated between their output terminals 4 and 4'.
Directly displayed rOJ, and when returning to the voltage state, between output terminals 4 and 4' (voltage that cannot be obtained (voltage) is 2't3
When the display shows "1", analog input terminal 1 is Il.
l U...S Sl'S2' S,)
, ■ The place where you are (taking) Nosaki”’ ”” s(2”i) s2
'Go, υI lit ii! (= As shown in FIG. 4, digital outputs rOJ, rlJ, rOJ . . . rOJ, rl, 1 are obtained between output terminals 1 and 4' of the J Josephson gate circuit M1.

Also, ai control S! 114-1 Joseph Song Gate Circuit M2 rOJ, rOJ between output terminals 4 and 4'.

NJ, NJ, rOJ, rOJ... "0].

Digital outputs of rOJ, Ml, and rIJ are obtained.

Furthermore, rOJ and rob are connected between the output terminals 4 and 4' of the Jollefson gate circuit M3 with υJ111 line.

rOJ, rOJ, rlJ, rlJ, N
J.

rlJ, rOJ, rOJ, rOJ, r
OJ・・・ro, J, rOJ, rO
J, rOJ, NJ.

Digital outputs of rlJ, rlJ, and rlJ are obtained.

In this way, the control line is connected to the control line
The analog input current ■5 is applied between the output terminals 4 and 4' of i as follows:
21 i -11> to I' 5 (4x 2"-th 41) 5 (5x 2"
-口）〜■ (C5 is being turned on) (If it is, the digital output of "O" is 1!?).

Also, a11ηII I! (=J Jikosef Song Goo 1
- Between the output terminals 4 and 4' of the circuit M, there is a 77 log input current 1 s /JN.
1 ' 5 (3x2'・mouth +1) 5 (4x2'・-1
・)~] 13 (5x21 i-port +1) 5 (6X2 ”
- ■ ) ~ If the value of I is yes, the digital output of [1J is iq
It will be done.

Therefore, from n loads, L2...f,o, if the analog input current 1 is equal to the value of I,1, as shown in Figure 4, (rOJ, rOJ...[ The n-bit digital output of 0() is output.

Also, the input current I of the anode []
If so, (r'+I, rOJ, r(')l...
・・Digital output of r) pin 1- of "O]) or i+'7
Let it go.

Furthermore, when the analog input terminal I is set to the value of 'S3, (rOJ, rlJ, rOJ "0"..."0"
)'s n-pi 1 digital output is 1'1? It will be done.

In this way, from 1 to Lo, the analog input terminal I
An n-bit digital output representing the 1st division of 3 can be obtained.

E'A,! Decay, -VI? i7.1flL-woo-L
-+l-4+ 179 S'j'j j:, 1 place C
, In the case of the conventional Josephson pulse AD converter circuit shown in FIG.
By supplying f::, the bias current 1b is supplied with the same waveform to the bias current line 1 of the control M ('I diode') to the node start circuit N11.

However, in order to ensure the above-mentioned function, the bias current supplied to the bias current line 1 of the control line f1 Joseph Song 1 and the circuit N11 to Mo must be an alternating current bias current, especially a narrow pulse bias current. Preferably it is an electric current.

However, in the case of the conventional Josephson pulse AD converter circuit shown in FIG. 1, such consideration has not been taken into consideration. FIJ 1ffi had malfunctions in both the cow and rru d5. In particular, f = small octagon -
When running at high speed, such J'3 (which was large).

Therefore, the conventional Jopifson pulse AD' shown in FIG.
D. Use of converter circuit;
It has 11.

Furthermore, in the case of the conventional Josephson At') conversion circuit shown in FIG. II i2D line 1 = J Zikolev song -
1. The ri11+Q characteristic with the above-mentioned periodicity of the circuit M is the same as the first, second...th cycle! The maximum value of the bias current 11) taken at 1 (I, but decreases depending on the number of cycles) is used to determine the value characteristic.

For this reason, Joseph Song with control glue 1~Circuit M・D
When taking 1st shift of 11r4 or more which requires 1111 current 1° supplied to til1 stock 11' market Q line 2, all
(II FA f dimension stain (Hifuson gout circuit M is 4
It was a mistake to not change the voltage state even though it should be in the single voltage state! r! It produces IJflT.

Accordingly, C1 control with i11 line "Ref song - 1 - Hi control of circuit M1 "control supply to flow line 2" 1 current 1° maximum 1 + l'i, f, L, analog input';'h rR
,I 8 maximum (limited to 11°i, also 7'P11G J) current l, &P11Q II in the range '11
Finished the 1st shift early - 1 noru male father, Lee fwamo n values ai
Receive l + limit and go 4 times.

Therefore, in the case of the conventional Jorenoson ΔD conversion circuit shown in FIG. 1, it is difficult to convert the analog input terminal 14 into a digital output with a large number of pitches within a wide range of 1+c. That shortcoming was right.

One object of the present invention is to convert an input current into a digital output at a higher speed than in the case of a conventional digital non-pulse generating circuit. A novel Josephson pulse A D'P<1 moxibustion circuit is used as the prophylaxis U.

Furthermore, the purpose of the present invention is to control the above-mentioned 7-noise input current over a wider range of values than in the case of the conventional diode, I-fuson, ΔD-variant circuit. I would like to refer to the Kami-Ki/Iji1 Cefson AD conversion circuit as γ11, which can be used as a ``digital believer''.

The first invention of this application is J, Ruji 10 Non-Pulse Δ
The D conversion circuit then converts (11 to 0.j).

La/nie) also high-nos current line and il'l 171
1 C71 and 4 I'-C, [1] of the control current supplied to the above-mentioned Lurie current line (11, 1), and 110 of the bias current supplied to the above-mentioned bias current line, A voltage state or n voltage state is taken between the output terminals of , and a threshold characteristic that takes a voltage state of a or (j voltage state) is -
The control current supplied to the F fertilizer control current line tJ4 has a different cycle or the same cycle for each bean for 11C1] and is constructed using a bamboo junction element. Josephson gate circuit M with control line of n cage (n72),
M2. ... Contains Mo.

It has a 3L bias current line and a control current line, and the control current is supplied to the 1-indication 121I current line depending on whether it is supplied with 21"lj or rOJ with "1" in 1-indication. , a pair of output terminals are in a voltage state or (1 voltage state 4). What should I do with a Josephson gate circuit Q1, Q2, .

Furthermore, the above-mentioned 1Ill I20 line 1 generates a pulse bias current narrower than the current from the AC bias current.
・1shi white? -Nosungoo 1-Circuit N11 ~\11, Nimushi 11 common Bershino' ward electric i,;j R;1
The circuit is C1 - However, the output terminal of the pair of control lines 1, 1 Joseph Song 1 - Circuit 0, (i = 1.2...n) and the pair of current lines: is, open. The control fa line is connected to the output terminal of the Josephson gate circuit M1 to N111, and the above pulse is connected to the bias current line of the Josephson gate circuit M1 to N111. A pulse bias current of 19 is supplied from the bias current generation circuit, and an alternating current bias current is supplied to the bias current lines of the V fertilizer line 1-inch Jorefusonoge-1 circuits 01 to Q, and the alternating current bias current is supplied to the L fertilizer line A-1. Girno Song 1~Circuit fv1.M2...Mo's 1ill ill current line
H.I.B.

By supplying it with a bribe,
1 Schoref Song Gate Circuit Q1. Q2,...Q.

An n-bit digital output representing the input current of the above-mentioned analog is output from the output terminal of the .

Yo, I go, the second request? Jollefson pulse ΔD conversion circuit according to the rrth invention (31, in the above-mentioned Josephson pulse ADt conversion circuit according to the first invention of the present application, 0 cycle control 21I line) −
・The pulse bias current generating circuit common to 1 except that the pulse bias current from the bias voltage generation circuit is supplied to the via of the Josephson gate circuit M with the 1Ill and 1O lines.
It has the same configuration as the Josephson pulse ΔD conversion circuit according to the first invention of the present application.

In addition, the Josephson Δr) conversion circuit according to the third invention by Mizuyori (the f+'ls configuration described next) is n.

・By connecting the bias current line and the control current line, calculate the value of the control current supplied to the control current line and the value of the bias current supplied to the bias current line. Depending on the value of the voltage, the voltage level r or 1. −
is the right electric current part 14, and the decoy ffi characteristic ↑1 which takes the zero voltage state or the voltage state is different from each other or The same Kaimei period! III Fi Z +z, Ji1
1? n-ml[
71 (n≧2.m≧2) control 611 Line f-1 Jokefu Song-1・To circuit M11, 1v11□;~121~M
21Il;..."+rl'~Mollin by 1° to the right. Also, bias current line and rr+lpH control iil
Current line (~1-1) to the right i+'l III current line 1-11, even number of Ri control current lines (control current 1) in 1m is supplied with roJ>-c-at, or the limiting σ0 current 'fAH,~1-III]6r M'z
It) J Noir+l 1711 Current line 1(-i, 1
The li20 current is displayed as 2Ili'i [01 (Matgo is "
1), the Shorefson Ig takes a voltage state or a voltage state between the pair of output terminals, depending on whether it is supplied with a
Q +I ill! 2 f=J C=+L? Fusonge-1 - Move circuits Q1 to Q to the right.

Furthermore, from the alternating current bias current, it is possible to generate a pulse bias current with a narrower width compared to the pulse bias current light l]
(i) the circuit.

However, the control of the current line 1 and 1. (j・1,2
・・Both ends of m)j are the 1st and 11th glands.
It is connected to the output terminal of S1 of εj1 to 1 (i=1.2...n), and then to the circuit 11. lI,, ~M11Il1M21~・~12m,
...~'r+1~M 1'? A pulse bias current is supplied to the circuits 01 to 1 of the Doi control line 1 inch.

Supply the above AC bias current to the bias current line of
Circuit 1V111 to Johifu Song-1 with the above control line
~'1m' ~121~M2m knee...M, 1~M11
11(7) By supplying the analog input current to the Irll i2o current line in the same or different 1st shift, the circuit Q, :Q
An n-bit digital output representing the value of the above-mentioned analog input current is outputted from the pair of output terminals of 2, . . . On.

Further, the conversion circuit to the Gilbertson pulse according to the fourth invention of the present application is as follows:
明(go・1)'ifi, n-rTlnll's system 611
Sai', i! fl jorefsonge~1・Circuit~111・
~N, 1111I, 1~121・to,・′V/1211
1. ... 11 common 41-pulse bias current generating circuits for Mll and Mom are multiple pulse bias current generating circuits with multiple pulse biases similar to those of TEL, D2...D.

, and the pulse bias current from the pulse bias current generating circuit D is connected to the control wire I.
1t? It is supplied to the non-nongoo 1-circuit Mi1-N.'im. The circuit has the same configuration as the third Cefson pulse Δ() variable 1φ circuit of the present application, except that it is configured as ``,'').

Furthermore, the di1t? according to the fifth invention of the present application? In the third invention of the present application mentioned above, the Fuson pulse △D conversion circuit has a control line 1;
-Circuit M11-M, l, l, M2. =:\・1,1゜... Mo1 to Mo4 have a plurality of n-m pulse bias current generating circuits D ~ 1 where the IJZ and Sumy current generating circuits are similar to each other. , one 11
m 21~D2IIl...Dnl~Dnun, and at the same time, the pulse bias current from the pulse bias current generation circuit D1j is converted to the Joseph Song 1 with control line.
~Circuit M
J. The third Johifson pulse Ar)
It has the same configuration as the conversion circuit.

Operation According to the above-mentioned Jiko Sefson pulse AD conversion circuit according to the first and second inventions of the present application, the drawing line with ili control line +
Ill? Fuson gate circuit M, to 12...M
By supplying the analog input terminals to the control current lines of n in the same or different channels, the output terminals of the analog input terminals from the output terminals of the circuits Q1 to Qn to the control line resistor group An n-bit digital output representing the ship is output.

In this case, the control line (-rji3) Hifusong-1-Circuit M
By supplying the narrow width<r pulse bias current to the bias current lines 1 to M, the analog input current is converted to an n-bit digital output, so the operation can be performed at high speed C1j. II can.

In addition, to the Josephson pulse according to the invention of No. 3 and No. 5 of the present application.
11. -Fuson gout circuit~111~M1m;1\12
Go to 1-fVI2IIl: ・・・ ・・・ ・・・
M 111~・”n111’s 3+11 former 11
Electricity 7.1D Song Dynasty (by supplying all log input terminals with the same, upper or lower direct connection)
From the output terminals of the pair of circuits Q, .

This obvious, Joref Song with control line 1-Circuit~111
To Mlm, ~121'~M2m...MmlN et al.□
By supplying a narrow pulse bias current to the bias current line of (1), the input terminal of
Since it is converted to the radial output of P1~, (:(
7) %h PI' (? +:”q ;! (line r
) l! Luko (!: KaI゛6ru,.

Further, in the case of the J, 1 Cefson pulse ΔD conversion circuit according to the third to fifth inventions of the present application, 1i'l 1211 line f=
-1 Ji-1e Fuson gate circuit M period number 0 zero I
J Agony 1 Direct #, i M IJ, t mentioned above in Figure 1, /j t
Since it) i+1'On R,'I'1 Same as 1 of Jopifunong gate circuit N・11+, 11. , 2, ε's 1st, 2nd... number [1's opening/(special) maximum bias current (or target, C decreases as the number of openings increases by 4j) 1 ."4111+'lL"r character 5",
do.

For this reason, when the control current supplied to the control current line of the Johfson gate circuit Mij with control P2 is changed to the value of Box 1-, the conventional control line 1 inch Josephson as described in FIG. The same is true for circuit M to goo 1. Malfunction will occur.

For this reason, the 11th lined Johifusong gate circuit N = +
The maximum direct current of the control current supplied to the control current line of , therefore,
A maximum of 1 of the analog input current is subject to the Hill limit at the same ti as in the case of FIGS.
I received a limit of 11 on the IC.

However, in the case of the Josephson AD conversion circuits according to the third to fifth inventions of the present application, in the case of the ii+I 1211 line-equipped Zikolev song one-to-one circuit N11ij, a) Kaimei no 2'! 4. Within the range of the same iI'l in current, the conventional G Refson AD shown in FIG.
By the change 1 arrow circuit, it can be made 1/m of the control line 1, 1, 10, 1 to 1/m of the circuit M.・Circuit M
・The maximum (1
f1.
(This is what is written in 8.

According to the effects of the present invention, according to the present invention, the Sefson pulse A/D converter circuit according to the present invention has a 7-log input current as shown in FIG. , and can be converted to digital output at high speed.

Furthermore, according to the Josephson A I) conversion circuit according to the present invention, the analog input current is m (Q
It has the characteristic of being able to convert from one to several large digital outputs in a wide range of applications.

FIG. 5 shows a first embodiment of the first invention of the present application,
Similar to the conventional Josephson pulse AD conversion circuit described above in FIG.

Also, set bias current 1, control current lines 2 and 3 to the right,
Control I lightning current 2110 is displayed on control current line 2 [1J (
or [OJ), or the control current line 2 is supplied with the control unit 1
Depending on whether the 1゛ street current is supplied with 21 direct display ``1'' or rOJ, the output 3;, looking between 1 and 4'', will be in zero voltage state or (, L (T voltage condition) , using Josephson junction elements (14) and a plurality of n control lines 11 Josephson circuits Q, Q2...Q,
(I'm looking forward to it.)

The control line G1JOPIFSONG gate circuit Q uses a circuit that has a well-known second h°11 configuration, but the control line A1G3L! Fusongoo 1
To circuit ~11 and Fj, look at the composition of the hill.

It also eliminates the pulse bias current generation circuit.

This pulse bias current generating circuit D let, - As an example, a 1 (((via the resistor 42, Josephson junction The cord 43 is inserted, part 1
Mr. 18 112 and C.P. 13, E., from 81° 1 in connection with child 43, C.I. Reflan 18, (.

The bias valve 11 has a configuration in which the bias valve 11 is led 11'1 through the child 44.

However, with control 1, II? Fusong-1/Circuit M1
~M, bias current l! i! 1 or connect PR in series.

Then, the bias current Pi! 11 is inserted.

In addition, the control line 1 inch G + piston game 1 - circuit N・1
1.~M0 control current lines 2 are inserted in series with the input current line 12.

In addition, control, gland to1jiqL! Fusongoo 1 ~Circuit~・
The control current line 3 of 1. is inserted into the control current line B.

Also, Joseph Song with 1 line 1/2) 101~
The bias current line 1 of Q11 is inserted into the above-mentioned bias current line 41 via the resistor 45.

In addition, the control 2Il line f' Johifusonggoo 1~circuit Q
Both ends of the current line 2 are connected to a through a resistor ri.
lll I Glued Jollefson gate circuit M1 output end 4
and 4'.

In addition, the control of the Josephson gate circuit Q with control rlJ line
A current line 3 is inserted between the control line and the current line G.

Furthermore, a control line (=wire between the output terminals 4 and 4' of the circuit Qi) is connected.

1. of the first embodiment of the first invention of the present application. °
It is four generations. According to such a configuration, the control line (=J
The configuration related to the Johifuson gate circuit M, ~~1 is converted to the conventional Jicofuson pulse circuit described above in FIG.
1-The configuration regarding circuit M is the same as 〇, panono current! i! 12, as in the case of FIG.
From the pulse bias current generation circuit, the bias current 1
Since b is supplied, the Joff Song with control line-1 circuit~'11-1~1. output ends 4 and 4' of
In the meantime, as in the case of FIG. 1 and 1i'il, a fugital output 19 is generated according to lii:j of the input current IS.

By the way, in this case, the sine wave 1 (31 trapezoidal wave AC bias) supplied to the bias current line 41 is applied to the bus (7 bus current line 11) derived from the pulse piecing current generating circuit. The cardiac flow Ia is equal to 6, and a narrow pulse bias current is supplied from the pulse bias current R1-circuit as the bias current 1b.

Therefore, the control I line 11 Jikosefsonge-1-circuit M1~
If the fugital output rl between the output terminals 4 and 4' of Mo is supplied to the control current line 11 and the control current line 41, it will be the same sine wave or trapezoidal wave AC bias current. Compared to the case C,1, it is possible to iq at a much higher speed.

Furthermore, as mentioned above, if a digital output is provided between the output terminals 4 and 4' of the Josephson gate circuit M with a control line, it is sent to the ml lit line I' and the circuit Q's 1li (I fil). Since the current is supplied to line 2, all 1211 wires of Josephson gate 1 - output terminals 4 and 4' of circuit Q, therefore, the load is 1.11171 A (= J Josephson gate circuit M
A digital output corresponding to the digital output obtained with 1 is obtained.

Therefore, the load L1-. As in the case of FIG. 1, a digital output representing the field of analog input current 13 is obtained from il:;.

Embodiment 2 FIGS. 6(t) and 6(L) show a second embodiment of the Cefson pulse ΔD conversion circuit according to the first invention of the present application.

9] In Figure 6, j5 corresponds to λ1 in Figure 5, the same symbol g is used as r-ILU.Detailed explanation will be omitted.

In the configuration described above in FIG. 5, the pulse bias current [1 CIJf- is supplied to the bias current line 1 of the control line 6t Joseph Song 1 to the circuit M through the resistor r', and il+
IIn! A sine wave or trapezoidal wave bias current 1a is supplied from the current line 41, or C, 11 is input via a resistor r.
The line f = 1 Silfzosig - 1 - The bias current line 1 of the circuit Q. According to the Lefson pulse AI') conversion circuit according to the present invention, since this is the same as in the case of FIG. 5 except for the above-mentioned white, the same effect as in the case of FIG. , 1r11.

Assignment 19j3 FIG. 7 shows a third embodiment of the 1-line circuit with 1 line and 1 line with ΔD variation according to the first invention of the present application.

In Fig. 7, the corresponding part with Fig. 5)
4 mouths 1・l l, T shown・J.

No. 1 of the present application shown in FIG. I; invention of r, l +, l
, J, logi 1 senosocipulse AD conversion circuit (3L, the same (y(1') configuration as in the case of FIG. 5 except for the next small knee''!) is fl.

Sui 1, with control line Di: 1 ke Fuson gate circuit M1-
I:Q l1fi with N'In is the 8th
The figure shows J,) (I met N the same month in January.)

In addition, resistors R6, R4, etc. are connected to the input current line 12.
II are connected in series and interposed, and in this case, one end of the input current line 12 is grounded,
Control current line 2 of Jorefson game h circuit M with control line
One end of the curve is resisted through the resistor R1' by the +R core of the resistor R(i-1) and R, and the curved end is grounded.

The above constitutes part 1 of the third embodiment of the zicocefson pulse conversion circuit according to the first invention of the present application. Except for this, it has the same t7u configuration as the case in Figure 5, so
Next J, perform the U-like motion, and make the += conjunction and +z in Figure 5.
+x )+′+ River 1. J+'l! ga i'7 rah
le t.

1 F) I) , 8 J Current
1 2 (I) - I'i If the current is supplied, the analog input to the control current line 2 of the J11 control line f = 1 3, the supply is supplied as iI and IJ current I6 for the field C of stomach 4τ (1'1), (I s・2)...(IS 3-n), respectively. be done. In this case, the analog input current 13 (direct)
Well, [(t ・1M (1, ・2)+...1=(I
-n)], but flE fat R, R+
.

O R...R's 1iTi, tlt anti-R', R2'...2
n +...
・By appropriately selecting the 1st shift of R', it is possible to
-1), 4-2>, (1, -, 3)...S...(1·n) have the following relationship.

・,, (I ・2) , = (+ −1) X
1・2(1-3)=(I 1.1)Xl, ISS (+ -/I)=(7S~1>Xl,'fl([-n
)=lI,-1)xl,/2(Ill) Therefore, control 3
Analog input current], (i-1) (1-1>
be provided.

Now, as in the case of FIG.
2++ wired jikohifusong-1 ~ 1111+ of circuit M1
Analog input current I8 is 1/4 to current line 2.

−1) of its analog input current 13, which is
in <1, -1> as 1. Which relation -G, the above mentioned in Fig. 1(g), then the next value ml -1)
1,, ~1) ... ([・1> ,, take.

2 s 20 pieces: (
1-1) 1-1g l'≦(1-1)2 <2XIg S 2×(≦<l-1) 3 <3 Xl, J! 7S 3XI≦(1-1)4<4XI.

S (2-1)
When the input current t is 1 direct (1, 1>, , (18S 1), 1)...(' I ''' 1 ) (23
If s 5 5n-1) is on the right (), it will be in a non-voltage state or II white cry
-1>, (1-11, (+3
-s 2 s
41) ...([・1>, , , 6 s 2 cases, as shown by the x mark 'C' in Fig. 8), returns to the A1 voltage state.

Also, 11sl2Il! ! A (NJ Ji) Ab 1.1 g is input to the control current line 2 of Senosong gate circuit h-+9/J current [Kir'i (1S-2) r is supplied, Zono A)
1-1q A ship (I 2) with a human horn current I is given by which relation S S IMi (1-2> , (1-2> ,
(IS IS
2S 2) 3...(r ・2> 2n etc. 7)
Ru.

O< (r −2) −71/'
2 X r.

1 ,'' 2 X + <([-2) 2 +-,
l.

S I ≦ (+ -2) 3<37'2XIgg -'
S 3, /2xlq = (Is-2>4 <2xl.

(211'2X[< n IJ(1-2)
. <2 XIg Shirtosa 1. Between the output terminals 4 and 1' of the control line [1 shift] and the non-gate circuit M2, the analog input current I is Ift (1-2) 1 and S (1--2) , ( 1-2) 5 abi (18s 2) ... (I ・2> .. and (IS6
s (23)-2).
If it has, it returns to the zero voltage state, but lii', +
(1-2), 3 and N, -2) 4, (1・2) 7 and (
+8.・2>8...<1 -2). - and (1-
2) n to s (21) s 2
When the voltage is 1, the voltage is applied as shown in q in FIG. 8B.

In addition, analog human power is connected to the control current line 2 of the control line angle 1 to the control current line 2 of the circuit M3 (+3-3>
l+Q of the analog input horn current Is supplied by
(I s -3), in which section (7) of ■9, i><'
ノ fin (1・3) , (1,・3
＞ , ... ・He- (1ζ3) n and city.

0 ′ (1--3) 1 ku, 1 t
l n/I(IS 1.4XI ≦:(+ 3><L・'2×1
, 1g s 2 12×I ≦(1-3)-1/IXI.

S 3/'4XI :;(I -3>・'
Igs A 01
-de' (1-3) <5 /'4
×I nri S 5 (2-1)/'Iku (IS 3) 2n < 2, "I Then, the current I at j'p[] is the value (+ -3)1 to ((-3), ((3
) to g・(I,'-'3)12s 4
S...(1・3) 1.・〜(t ・3)(2s
(27) When s+l-4) is equal to j, the state is zero voltage, but (1-3) ~(
1-3). , (18,-3)S 5
S 13~ ([S・3>16...1lS・3>r2r+
・3) to (13) When moving back to n, a voltage-applied state is assumed, as shown by the x mark in FIG. 8C.

In this way, the analog input current I3 or (1^(+
Iil′4 of the analog input current I, supplied by =>
(1-i), relationship with 19 C13s next I + QII -i), (1-1)2-・
-=-・SI S (l l)n.

n (i-1) (2-1) ×
1 y' 2 X [a≦(ls −')
2 n (i-1) < 2 (S is II −i) to (I i)2+;
+S I S ([!) (2x7+ + -++, 1) ~ ((
-ri(3,2+: +I) (1! >(4x2+ + -++ +1)'~4 -
! ) If the value is (5 x 2 days - 11),
Takes a good voltage state.

/j, ii'1611 k <"J":'Fl Sef'/ When the gate circuit M1 outputs -ε 4 and 4
Between ', the analog input current l is (1-1)(2++day+1)1・(1-ri(2,X2+・1").

(I I) (3×2+: bite (1)・-(1!Z
4x2+t ++ ) (1-1) (5,2+・mouth(1) ”-(1! ) 1 “1 of (6x2+ + ++ )
If j is E, stone ゛ city [1-pay Qi',, (
, doku) 3 follows ℃, now control 2 (!lined shi:]t?fuson)il to circuit~11~1o returns to zero voltage state and 3 between these output terminals 4 and 4' Electric IT
(zero voltage) is set to 2-direction rOJ in the same way as in the case described above in Fig.
The voltage (with voltage) obtained between The control current line 2 is connected to the control wire J]L! The value (i-1) supplied to the control current line 2 of the circuit M1 (l, -1)
Since the footer log input current 1 is directly supplied to the control current 11 of the Josephson gate circuit M1 with control line,
Considering the value supplied to 2, it is (+ ・1)
, (1・1)2...([3s 1 5 -1), , between the output terminals 4 and 4' of the control line (from the control line 1 to the circuit M), Fourth
As shown in the figure, when 1 is mentioned in Figure 1, the -l cycle output horn of 11) is 1! '7 et;ru.

Therefore, f1M'l 1. , 1 = l−n, i′
) n'J input current I, the n-bit digital output can be outputted to lll'I.

Embodiment 4 Example 9 of the Josephson pulse to D conversion circuit according to the second invention of the present application.

In FIG. 9, parts corresponding to those in FIG. 6 are designated by the same reference numerals, and detailed description thereof will be omitted.

In the embodiment of the G-1 Sefson pulse Ar) conversion circuit according to the second invention of the present application shown in FIG. 9, the pulse bias current generating circuit [] of FIG. The same as in the case of Fig. 6 except that the pulse bias current generating circuit D has the same configuration as the corresponding pulse bias current generating circuit C (the configuration of :r is changed to I do it.

According to this J, . 9J+ fruit is fenced.

(Fig. 10 shows Johifson A, the third invention of this condyle.
A first embodiment of the D conversion circuit is shown, and n-m1ll (n
>2. m≧2) control HI! J ('I Johifusungoo1・Circuit M, IV1...IVllm:l'v12
1=M22°""""M2m'"""""nl・"n
2""""'M. In this case, control II line G] SEFF m song gate circuits M11 to M11. Il is the Josephson gate circuit with control line ~1 described above in FIGS. 1 and 3.
The configuration is the same as in the case of .

! Therefore, Josephson gate circuits with control lines M11 to M1
1II, parts corresponding to those in FIG. 1 are designated by the same reference numerals, and detailed description thereof will be omitted.

In addition, J Ref Song-1 with control m line, circuit Mi1~M
When the period of the threshold bTj fi is 11, the period r of that 1m is shown in FIG. 11: )1. :,I improved with Figure 1, I + 111112 ``Ref Song-''
1. Circuit M(il) ・Similarly to the 1st combination of ・, right the circumference 11 of 2
There is.

However, in this case, the serial control line (= r di 11 - 7 song gate circuit M11 - M1 - threshold characteristic cycle II I 1
is shown in FIG.
1-Circuit N・11's agony value ↑! 1 m times the period 11 of 1
The author is C.

In addition, the bias current line 1 and the m-side control σ0 current line) 1
, , l・12,...Hm, and a control current line 3, and to the JIl control current line 11 on the m side, an even number of J1I1 instantaneous current lines in 1-11°. J111ησ current is 2
(In the fj display, "1" (Yoko is [0]) 'c' is supplied, but the control current on the m side (1 current line 111~Ll) is 21ffi display C
r 1j (Maj:=LtroI) Depending on whether the voltage is supplied between the output terminal and 1 and 4' (only τT voltage is in 11 state or 0 voltage state), it is configured using a t: F”i therefore n lp, 117)ir
HII line rJ shi: J b;'So>keh times 1fIQ1
．． 02...I1iJru Qo.

This lll1lillItQ (N1 Jikosef Song-1
The circuit Q(i・1.2...n) can be constructed using various N, i people, etc., which are known in the art.
As shown in Fig. 2, in Fig. 3, the control 12 Il line f'' C 3 reflex song - 1 and the ↑ 1111 composition of the circuit Mi, 13 I (, (11.11 i2 [1 current line 2 is 10
-H to the main control current line 11.

In response to this, the fuson gate circuit F
To [3, the control current line 7 is one, but instead of C, m
Honishi 1, and Ji E + Refson gate circuit ``1 to 1
:1 jth (j=1.2...m) 4-1 Ne11 current line 7 is connected in series, l111Go current line I
(a
do.

``However, Josephson gate circuit with control line M・M
, M ”M , +...Mn1~M, ・114
m 21 2m The bias current lines 1 are connected in series to form a pulse bias current generating circuit D (not shown), as in the case of FIG.
The bias current line 11 is inserted into the bias current line 11 which is led out.

In addition, the circuit M with control fl19
11~I1m, M21.. 〜I 2+n, ・・・M
nl~Mnm I;Qjin cardiac flow lines 2 are connected in series (input voltage 1j: Ltl! 12 is not inserted).

The control current line 3 of the Josephson gate circuit with control line N1 is inserted into the control current line B, IJ.

It's lj.

Also, control line f=IG4t? Circuit 01 to Fusonge-1
The bias current lines 1 of ~Q11 are connected in series and connected to the bar (7λ electric cooling wire 41 (via
11j has been done.

Furthermore, both ends of the control current line F1 of the control line F1 to the circuit Qi are connected to J through the resistor R...
At IJ, 18 outputs of the Josephson gate circuit M with control line are connected to terminals 4 and 4'.

Furthermore, Josephson gate circuit Q with ill tit line
A load 1 is connected between the outputs of 1::4 and 4'.

This is J,'1% formation of the first embodiment of the Gilfson ΔD conversion circuit according to the third and third inventions of the present application.

According to this Josephson Δ' conversion circuit having an M configuration, if a bias current line 11 (, 2 r'? bias current I, is supplied), a Josephson gate circuit with a control line M
The bias current line 1 of . . . is supplied with the bias current 1b at that value.

In addition, if the analog input current ■3 is supplied to the input horn 7U streamline 12, the control line 1q diF + Hifusong-1-circuit M
・The i, lI lit current line 2 has an input current j 1 , and the control current I in that 1 white. Furthermore, 1 lill i2[1 current line B 1j1. :
ill
11 current I[ is supplied across -.

The 15th bias current 1b supplied by the bus (7 bus currents,
l b', and also control current line B.
wo,'a this% 11'T1. , -'M constant L/T
By flowing, the control line fζJji”ref song-1~
The above-mentioned RPI of circuits M, , j is input current line 1
For the horn current I3 supplied with 1 to 2, -C1 L in Fig. 11) is given the same circumference +1 as H).

1t, then the control current [, l11(i, analog 1g) of Fig. 11 is the circumference fl about the axis of the input current 13.
...11, 12 ... Control current υ supplied to B1□ [value of f, subordinate...] C1 control line with control line -1 circuit~'11. "12...
By making the control current l' supplied to the control current line 3 of ~113 different from n, the control i11 is
Gland fJ Zielfson gate circuit M111M12...
・The phase of Ml-open chain characteristic is advantageous to (+'7 finger of IC1 special bamboo) between Josephson gate circuit M11 with control line,
Sequential beans vary.

For example, Johi Fusong Goo 1 with control line ~ circuit\・1
11(7) IM ItD ilo nature, 1+'l r
at current 1 (zero C't,') 6 K4 O, bias mountain flow' The phase where b is on the right is 5 on the neck, and a
+'l till 22 (4 + L -/ / 17+l l direct 1j property 1) of the Ngut circuit M12; 1. ++ Drawing line = J Joseph Song 1- times 3
M, 1(r) PallIri'+i M phase vs. 1.4X +.

Minute 11" / 111;

In this way, the control 2II current lines Mi11M12...N...
1tm, following v, it drawing line f = 1G J ref song -
1. Circuit~4.1. M: 2...~'im's control I 'lTi flow gland, supplied to 3 ¥1-ro control current 1f
By making Tj 'fA l, t', l11111211 line 6 + di' pifson gout circuit M
il,” i2...MIIll threshold 1 straight 1 no 1
The V phase is the control II line 14, the Lefson gate circuit ~ 11
For the phase of the threshold characteristic of 1, the first order becomes y·1.

For example, if the control current between the control line (Jjohifson gate circuit Mi1 is 1° or 44°), the bias current [1° or 44°C], the bias current [1° or °C]
The phase of the 1st shift of the 1-circuit M12 is the Josephson gate circuit N-111 with suburban line.
It has a phase difference of 1·'4×11)×i with respect to the phase of the threshold characteristic.

Therefore, now, one shift of 1/'2 of the period 11 mentioned above is 1
and analog input terminal 1. The value of [in which relation, the following fllII I 1951'3213
3.

0≦IS1<1/2x19 1,,/2 X l Si32kuIQ19≦I
33<3. /2XIg 3・'2 X I 7 rivers 9.42X I,.

2Xl >l, 5・go5," 2
1>, '2XI≦'S2' S・te 2・2 × 1 g only
, 11.1jll till line f=JjiJref song-
1-circuit ~111 has an input current I between its output terminals 4 and 4';'s5 and S sl and'So"'"'"Scream S (2 low 3) and' s
(If it has 2”-21, it will be in a zero voltage state, but
Values I, J and 's4. 's7 and 's8 town old...Is(2IT
i) and 1n case when typing 's2'', Figure 11 Δ
As shown in the middle cross mark C, the voltage is applied.

Also, pictured diary for system i: 1 sef song - 1 circuit N = I +
2, between its output terminals 4 and 4', the analog input current 1 has the value ■ and] 1 and 'S7...S
s2 S3' So“11
°”s(2n -2) and UIS(2n -1)':
When r noshi T, it assumes the zero degree D state, but straight 1sL
ls4 and IS5''...-1s(2IT-4) and's(2n-,'r).

If it has l, mark 2n in Figure 11 Indicated by = j J: Return to the voltage state.

Furthermore, the control 2Vl line [Jji, ]] reflexion 1 to circuit M2 has an analog input terminal 1 between its output terminals 4 and 4' to ITQt, +~'34''!'l!l).
, 12...”' ”” s(2”-7) s(
2”-41 to the right I !l!, the zero voltage state is 1irH ~ I I
S5 S81 ~[,...'s(2"・3) ~1 to sl2
sl5
In the case of s2°, the voltage is applied as shown by the cross mark in FIG. 9C.

In addition, the circuit M22 to the control O line fNJ Joref Song-1
is between its output ends 4 and 4' (ab[]g large input flow 1
but fl(11 and I l -153336
', sN sl3..., the non-voltage state is returned, but iiQ
l and (I ~[...(3(2!11.+2°
s7 sl+ n-1) and l, it assumes a voltage-applied state as shown by the X mark 7J in FIG. 11, 2nD.

Furthermore, al (between control lines) Reno Song-1/Circuit N1
31 iJ, between the output terminals 4 and 4' of the shift) -I
Ig input current 1 is III'Il -I n,
r = -1S sl S
o so If the S24... is turned on, the zero voltage state is 4, but ',9'''・'sl
6. If “□” S32... is taken, then E in Figure 11
Set the voltage state as indicated by the X mark in the middle.

In addition, the control line f" Jirlev Song-1 ~ Circuit N・1
32(, t, between the output terminals 4 and 4', the input terminal I is
s5 Si2 s2+ S28・
..., the zero voltage state is returned, but the value I ~ [1
〜１ ...I11'ruage sl s4・sl
3 In the case of S20, the 11th l r-' takes the (i' voltage state) as indicated by the lJX mark.

In this way, between the output terminals 4 and 4' of the control line II (=) di
[Depending on the value of the 1G input current IS, the zero voltage state rx takes a voltage state.

Therefore, now, control 12 TI line expansion I reflexion game 1~circuit~1 to 1M,~1~N・1. ...11.1n,
・MN In 2+ 2m. □ is zero; [When the state is taken, the electric current Fi that is 17 between the output terminals 1 and 4' of Dah et al. 21+
The voltage ((J voltage)) between the output terminals 4 and 4' when the current status is set is ``0'' and 5 on the f'i display. If it is 1, the analog input current [is I I I . . 1s (2n ・1
s slo S2° S, ) , I between output ends 4 and 4'J of Josephson gate circuit M with tll III line, n=3. When m=2, as shown in Figure 13,
Digital output is output.

It's rL, n-・3, ryl=-3's mission, control 60
As shown in FIG. 14, a digital output is output between the output terminals 4 and 4' of the line A, 1 and I Cefson gate circuit Mij.

From this 1ill n-wired Ji1sefson gate circuit Q1 to Qo, n=3. When m=2, the digital output is output at t3 as shown in FIG.

Also, n=3. When m=3, the digital output is suppressed as shown in FIG.

Therefore, what do you do in 10? So, the analog input current is 1. It is possible to output 1q of digital outputs of n-gotsu 1- representing the womb.

Bettle, this one hundred hundred-), '; Noni / Norudeno L or Control Line 1 ・ ”
1~M, □ group 11! The number of surrounding GJs in the i4M property is Ii, MJ3 within the IU antistatic current range 4/i, and the first
In the figure -1- the control line f4 of the conventional Jiko Sefson AD conversion circuit described above: 1 in the case of IP fuson game 1 to circuit M
When written in /m, J means 1 wa (℃).

Therefore, in the case of the Gielfson AD conversion circuit according to JJ, the input current shown in FIG. Compared to the circuit, it has a wide range of m times, and it can be converted to a digital output with an infinite number of bits.
According to the Jollefson Vals ΔD conversion circuit invented by No. 3 Kiyori, shown in FIG. Fuson gate circuit IV111-・N・1
1□.

M21 to M2IIl...Mnl to M1.1 These bias currents \A1 are supplied with a pulse bias current as in the case of the Ziko Sefson pulse △1] conversion circuit according to the first invention of the present application described above in FIG. Generation circuit D (not shown)
The pulse bias current from ]J (is supplied as bias current Ib), and the control line 1
The 1st E+F song circuits 01 to Q operate by supplying a sinusoidal or n-wave alternating current bias current [a] to their bias current lines 1, as in the case of FIG. Therefore, as described above, the analog input current can be converted into a digital output in an elaborate manner, and the conversion can be performed at the same high speed as in the case of FIG.

Harm'' [Al Figure 15 1, Tama, Kito No. 33 ``Second implementation of Jopifuson △D conversion circuit invented by J. 1?I 15 Accepted.

In FIG. 15, parts corresponding to those in FIG. 10 are designated by the same reference numerals C11, and detailed explanations thereof will be omitted.

In accordance with FIG. 15, the second implementation of the di:IL′Fson ΔD conversion circuit according to the third invention of the present application is implemented. E
] Same as the 1111 configuration of the L-Fusson AD variable circuit (there is a configuration of η).

That is, the circuit 1-1t'll of the open-chain characteristic of the control υ(1-wire di-Tl t fsong-1 to (i-1) Mil to MiIll,
or 2x11 to the right, and instead of -C, control line A and 1]
Pifsong one circuit MII “M1m” “21~”2m
'``''''...M -1 ~ 1's agony 1 direct characteristic cycle!I
IJ is Ii4(J(72 nm).

YoIko, control 1lII line f] Ji,, -I Refsunge-1-
'The input current supplied to the input current line 12 in the circuit control i2I+ current line 2! , (but instead of supplying the same value ゛
~Circuit M11~M;~1~M:...'”'
M2n~”nln’s 11.11+m 21
2m ■Current line 2 has 10 noson ΔD as shown in Figure 7 above.
In the variable 1φ circuit, C1, its control line f-1, the line song 1, circuit ~ 1, ~ 12... M n, Ana 11
(13-1)
.

(lc・,2)...(IS・n)
-1), (+,,-,2>S
S...(+ ・, n
) so that it is supplied by Ii and C.

For this reason, FIG. The resistors R, R, J, . . . Ro are connected in series to the current line 12. In this case, assuming that one end of the input current line 12 is grounded, a control current I! of +, -·Mlm is input to the Josephson gate circuit with control line. i12 are connected in series, one end of which is connected to the resistor R1.
' is connected to the midpoint between the resistors R(i-1) and R, and the other end is grounded.

The following is the configuration of the second example of the IL/NOSON AD conversion circuit according to the third invention of the present application.

According to the Josephson AD conversion circuit according to the present invention having a configuration of C#,), it has a configuration similar to that of 1 to 7 in FIG. 10, except for the above-mentioned matters. .

On the other hand, the JoLfson gate circuit with marking line Mi, ~IVI;
M is the control line feeder Schiff 11 of the Josephson ΔD variation circuit described in Fig. 7 CF? It has a one-direction characteristic while corresponding to the threshold characteristic of the Fuson gate circuit M, and its control oIl line r-1 di3+1 Fuson I no-1-circuit M
11~Mi, control current line 2, funori [1 person 1]
A current 13 is directly supplied to the control line I+ control current line 2 of the conventional Josephson D conversion circuit 21f and the I+ control current line 2 of the Josephson gate circuit M.

Therefore, even in the case of the present invention, which is not shown in FIG.
It will be appreciated that the digital output representing the .

In addition, in J3, an embodiment of the converting circuit for converting the first, second, and third lights 1111 into dicosephonon pulses of the present application will be described. In the GJ high non-pulse ΔD conversion circuit according to the third invention, the bias current lines 1 of the Josephson gate circuits Mi1 to N4Hn have −[,
The first invention according to the first invention of the present application described above is a non-pulse AD modification 1! ! ! According to the embodiment of the circuit, the configuration for supplying the pulse bias current from the 1-pulse bias current light circuit to the 4th embodiment of the JoI Sefson pulse ΔD conversion circuit according to the fourth invention It is also possible to add C to the bias current line 1 of the Josephson gate circuit M, .
¥1. The configuration in which the pulse bias current is supplied from the pulse bias current generating circuit Djj can also be used as an embodiment of the Sefson pulse AD converter 1 negative circuit according to the fifth invention of the present application.

Furthermore, as described above, in 15, the Josephson gate circuits M11 to Mim with control lines have the period I, and the G3 reflexion gate circuits with control lines M11 to Mim have the period I,
The cycle of rl ~ 111 ~ M1111 cycle 11 2 light (Yo 11
The period of is 11, and this (accordingly, the control 12Ill line f=
J Josephson Gate times 2, M, 1 to Ml-
The control i2I current line 2 has an input current [,, part 1
1^te or Ir1l ill line with Joseph Song 1
・Analog input current I(i-1) supplied to 1+control current line 2 of circuit M1 We have described the case where it is supplied at ↑/'2 of lin of circuit M1, but control! 1111 with ji” [Flang-1~
Circuit Mid, Mi2...Mim, 1771 of ε!
II has a period of +1, and the period differs by 4.1 from the above-mentioned one.
12, an analog input current 18 is supplied to [lii'iC different from /Jli'i (Figs.
Figure combination 11. The same effect can be achieved in the case of the 19th century) in the 19th century).

Various other modifications and changes may be made without departing from the spirit of the invention.

[Brief explanation of drawings]

FIG. 1 is a cJ system connection diagram showing an example of a conventional Josephson AD conversion circuit. Fig. 2 1, the control used for this ff1l rM f=
This is a non-sigma diagram of the circuit group 1iIlli special ↑1. FIG. 3 is a connection diagram of a circuit with control lines used in a conventional diFIL/FIL/Fson ΔD conversion circuit based on FIG. 1. Figure 4 shows the analog J current shown in Figure 1 in the dynamic explanation of the conventional Josephson AD converter circuit.
The figure shows the relationship between the digital outputs. 5 to 7 are systematic connection diagrams showing embodiments of the Josephson AD conversion circuit according to the present invention. Figure 8 shows the Jollefson pulse AO variation 1 shown in Figure 7!
FIG. 3 is a diagram showing the durability of the Josephson gate circuit with control line used in the J circuit. 9 and 10 are systematic connection diagrams of other embodiments of the Josephson pulse AD conversion circuit according to the present invention.
It is a y diagram showing the open-chain characteristics of the diagonal gate circuit with control line used in the D conversion circuit. FIG. 12 is a connection diagram showing an example of the control powder-equipped jicocefsonge 1 circuit used in FIG. 10. FIGS. 13 and 14 are diagrams showing the relationship between analog input current and digital output for explaining the operation of the Josephson AD conversion circuit according to the present invention shown in FIG. 1Q. FIG. 15 is a systematic connection diagram showing another example of the Gikosi-Noson ΔD conversion circuit according to the present invention. 1...Bias current line 2.3...Control ILI current line 4.4'......... Output
96MH (i = 1, 2...n)...Control 21I line How many Josephson circuits 8,...Control 2II current line 5...Bias current line 6...Josephson Junction element 7.8... Control current line F, ~F3... 1ill Inn nailed Joseph Song 1 circuit 11.11'... Bias current line 1 j (j=1.2... ・・・・
...m)...tll III current line Mij (i = 1.2...n: j = 1.2.
... m) ... Josephson gate circuit with control line Q ... υ control line (=j) Josephson gate circuit with control line, D ... Pulse bias current generation circuit 41 ... Bias current lines R~R, R'~R', r1~r.onIn, r~r', r1"~r,"n...0if m people

Claims (1)

[Claims] 1. The device has a bias current line and a control current line, and is responsive to the value of the control current supplied to the control current line and the value of the bias current supplied to the bias current line. The output terminals of the pair assume a zero voltage state or a voltage state, and the threshold characteristics for taking the zero voltage state or the voltage state differ from each other or with respect to the value of the control current supplied to the control current line. n (n≧2) Josephson gate circuits with control lines M_1, M_2, ......M_n configured using Josephson junction elements having the same periodicity, a bias current line, and a control current and a zero voltage state or Josephson gate circuits with n control lines Q_1, Q_2...Q_n configured using Josephson junction elements that take a voltage state, and a pulse bias current with a narrow width compared to the alternating current bias current. The pulse bias current generation circuit is common to the Josephson gate circuits with control lines M_1 to M_n, and the Josephson gate circuit with control lines Q_i (i=1,
The output ends of the pair of control current lines of 2......n) are connected to the output ends of the pair of the Josephson gate circuits with control lines M_i, and the bias current lines of the Josephson gate circuits with control lines M_1 to M_n are connected to the output ends of the pair of control current lines M_i. A pulse bias current obtained from the pulse bias current generation circuit is supplied to the pulse bias current generating circuit, and the alternating current bias current is supplied to the bias current lines of the Josephson gate circuits with control lines Q_1 to Q_n, and the pulse bias current is supplied to the Josephson gate circuits with control lines. By supplying analog input currents with the same or different values to the control current lines of the circuits M_1, M_2...M_n, the output terminals of the pair of Josephson gate circuits with control lines Q_1, Q_2, ...Q_n are controlled. A Josephson AD conversion circuit, characterized in that it outputs an n-bit digital output representing the value of the analog input current. 2. It has a bias current line and a control current line, and a pair of output terminals according to the value of the control current supplied to the control current line and the value of the bias current supplied to the bias current line. A zero voltage state or a voltage state is taken between the two, and the threshold characteristic for taking the zero voltage state or the voltage state has a periodicity of mutually different or the same period with respect to the value of the control current supplied to the control current line. n (n≧2) Josephson gate circuits with control lines M_1, M_2...M_n configured using Josephson junction elements, a bias current line, and a control current line, Depending on whether the control current is supplied to the control current line as a binary value of "1" or "0", a zero voltage state or a voltage state is achieved between the pair of output terminals. n Josephson gate circuits with control lines Q_1, Q_2......Q_n configured using Son junction elements and a plurality of n pulse bias currents that generate a narrow pulse bias current from the AC bias current. The Josephson gate circuit Q_i (i=1,
The output ends of the pair of control current lines of 2......n) are connected to the output ends of the pair of Josephson gate circuits with control lines M_i, and the bias current lines of the Josephson gate circuit with control lines M_i, The pulse bias current obtained from the pulse bias current generation circuit D_i is supplied, and the alternating current bias current is supplied to the bias current lines of the Josephson gate circuits with control lines Q_1 to Q_n. By supplying analog input currents of the same or different values to the control current lines of M_1, M_2, ......M_n, the control lines of the Josephson gate circuits with control lines Q_1, Q_2, ......Q_n can be controlled. A Josephson AD conversion circuit characterized in that an n-bit digital output representing the value of the analog input current is output from an output end. 3. It has a bias current line and a control current line, and a pair of output terminals according to the value of the control current supplied to the control current line and the value of the bias current supplied to the bias current line. A zero voltage state or a voltage state is taken between the two, and the threshold characteristic for taking the zero voltage state or the voltage state has a periodicity of mutually different or the same period with respect to the value of the control current supplied to the control current line. n·m (n≧2, m≧2) Josephson gate circuits with control lines M_1_1 to M_1_m configured using Josephson junction elements;
M_2_1~M_2_m;......M_n_1~M_n_
m, a bias current line, and m control current lines H_1, H
2,...Hm, and the control current lines H_1 to H_
The control current is displayed as ``1'' on the even numbered control current lines in m.
” (or “0”) or the control current line H
Depending on whether the control current is supplied as "1" (or "0") in the binary display to the odd numbered control current lines among _1 to H_m, a zero voltage state or a voltage-enabled state occurs between the pair of output terminals. Josephson gate circuits with n control lines configured using Josephson junction elements that take states Q_1, Q_2......Q_
n, and a pulse bias current generation circuit that generates a narrower pulse bias current from an alternating current bias current, and has a control current line H_i (j=1, 2) of the Josephson gate circuit with control line Q_i. The output terminal of the pair of . . . m) is the Josephson gate circuit with control line M_i_j (i=1
, 2......n), and the Josephson gate circuits with control lines M_1_1 to M_
1_m_', M_2_1~M_2_m_'......M_n
The pulse bias current obtained from the pulse current generation circuit is supplied to the bias current lines of _1 to M_n_m, the alternating current bias current is supplied to the bias current lines of the Josephson gate circuits with control lines Q_1 to Q_n, and the Josephson gate circuit with control line M_1_1~M_1_
m;M_2_1~M_2_m;......M_n_1~M_
By supplying analog input currents with the same or different values to the n_m control current lines, the Josephson gate circuit with control lines Q_1; Q_2;...Q_n
A Josephson AD conversion circuit, characterized in that an n-bit digital output representing the value of the analog input current is output from a pair of output terminals. 4. A bias current line and a control current line, and a pair of output terminals according to the value of the control current supplied to the control current line and the value of the bias current supplied to the bias current line. A zero voltage state or a voltage state is taken between the two, and the threshold characteristic for taking the zero voltage state or the voltage state has a periodicity of mutually different or the same period with respect to the value of the control current supplied to the control current line. n·m (n≧2, m≧2) Josephson gate circuits with control lines M_1_1 to M_1_m configured using Josephson junction elements;
M_2_1~M_2_m;......M_n_1~M_n_
m, a bias current line, and m control current lines H_1, H
_2, ......H_m, and the control current lines H_1 to
Either the control current is supplied as "1" (or "0") in binary display to the even numbered control current lines in H_m, or the control current is supplied to the odd numbered control current lines among the control current lines H_1 to H_m. It is constructed using a Josephson junction element that assumes a zero voltage state or a voltage state between the pair of output terminals depending on whether the output terminal is supplied with a binary value of "1" (or "0"). Josephson gate circuit with n control lines Q_1, Q_2......
Q_n, and a plurality of n pulse bias current generating circuits D_1, D_2...D_n that generate a pulse bias current with a narrow width compared to the alternating current bias current, and the Josephson gate circuit with control line Q_i The output ends of the pair of control current lines H_j (j=1, 2...m) are connected to the Josephson gate circuit with control line M_i_j (i=1,
2......n) are connected to the output terminals of the pair of Josephson gate circuits with control lines M_i_1 to M_
The pulse bias current obtained from the pulse bias current generation circuit D_i is supplied to the bias current line of i_m, and the Josephson gate circuit with control line Q_1 to Q_n
Supply the above AC bias current to the bias current line of
Josephson gate circuit with control line above M_1_1~M_
1_m;M_2_1~M_2_m;......M_n_1~
By supplying analog input currents with the same or different values to the control current lines of M_n_m, the Josephson gate circuit with control lines Q_1;Q_2;...Q
A Josephson AD conversion circuit, characterized in that n-bit digital output representing the value of the analog input current is outputted from the pair of output terminals of _n. 5. A bias current line and a control current line, and a pair of output terminals depending on the value of the control current supplied to the control current line and the value of the bias current supplied to the bias current line. A zero voltage state or a voltage state is taken between the two, and the threshold characteristic for taking the zero voltage state or the voltage state has a periodicity of mutually different or the same period with respect to the value of the control current supplied to the control current line. n·m (n≧2, m≧2) Josephson gate circuits with control lines M_1_1 to M_1_m configured using Josephson junction elements;
M_2_1~M_2_m;......M_n_1~M_n_
m, a bias current line, and m control current lines H_1, H
_2, ......H_m, and the control current lines H_1 to
Either the control current is supplied as "1" (or "0") in binary display to the even numbered control current lines in H_m, or the control current is supplied to the odd numbered control current lines among the control current lines H_1 to H_m. It is constructed using a Josephson junction element that assumes a zero voltage state or a voltage state between the pair of output terminals depending on whether the output terminal is supplied with a binary value of "1" (or "0"). Josephson gate circuit with n control lines Q_1, Q_2......
Q_n, and a plurality of n·m pulse bias current generating circuits D_1_1 to D_1_m; D_2_ which generate pulse bias currents having a narrower width than the AC bias current from the AC bias current.
1 to D_2_m;...D_n_1 to D_n_m, and the output terminal of the pair of control current lines H_j (j=1, 2...m) of the Josephson gate circuit with control line Q_i is
Josephson gate circuit with control line M_i_j (i=
1, 2...n), and the pulse bias current generating circuit D_i is connected to the bias current line of the Josephson gate circuit with control line M_i_j.
supplying the pulse bias current obtained from _j, and supplying the AC bias current to the bias current lines of the Josephson gate circuits with control lines Q_1 to Q_n, and supplying the alternating current bias current to the bias current lines of the Josephson gate circuits with control lines M_1_1 to M_1_m;
M_2_1~M_2_m;......M_n_1~M_n_
By supplying analog input currents with the same or different values to the control current lines of m, the analog input current is inputted from the output ends of the pair of Josephson gate circuits with control lines Q_1; Q_2;...Q_n. A Josephson AD conversion circuit characterized in that it outputs an n-bit digital output representing a current value.