JPS6167255A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To improve the current amplification factor and operating speed of an integrated injection logic circuit (I<2>L) by forming other conductive type second buried layer of an impurity having larger diffusion coefficient in one conductive type first buried surface of a region for forming the I<2>L. CONSTITUTION:An N<+> type impurity is diffused in a P type substrate 1 to form an N<+> type first buried layer 2, and ions of an impurity having a diffusion coefficient larger than the impurity of the layer 2 are then implanted only in an I<2>L region to form an N type second buried layer 3. Then, an epitaxially layer 4 is grown, P<+> type impurity is diffused from the surface to form an insulator separation region 5, ions are then implanted from the surface of the layer 4 of the I<2>L forming region to form a P type first base region 6. Then, a shallow P<+> type second base region 7b having high density higher than the region 6 is formed from the surface of the layer 4, N<+> type impurity is then diffused to form the emitter collecting region 8a and collector region 8b of the I<2>L and the emitter region 8c and the collector region 8d of a bipolar transistor.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a method for manufacturing a semiconductor device, and particularly to a method for manufacturing a semiconductor device, and in particular, a method for manufacturing a semiconductor device.
Logic.

The present invention relates to a method of manufacturing a semiconductor device having an ordinary bipolar transistor (hereinafter referred to as I2L) and a gold circuit board.

(Prior Art) FIG. 2 is a structural sectional view of a conventional integrated circuit that coexists with I2L and bipolar transistors. In FIG. 2, part A is a bipolar transistor part coexisting with I2L, and part B constitutes I2L. That is, l
is a P-type substrate, 2 is an N-type first buried layer, and 4 is a Nu-type substrate.
Epitaxial layer, 5 is P+ type isolation region, 6 is P
Mold cylinder 1 pace area, 7a is P+ type injector area, 7
b is the P+ type second pace area, 7C is the P type base area,
8a is an N+ type emitter contact region, 8b is an N raw type collector region, 8C is an N medium emitter region, and 8d is an 8th base collector contact region.

Of these regions, the P-type injector region 7a, the N-type epitaxial layer 4, and the P+ type second space region 7b are emitters of PNP transistors, respectively.

A unipolar lateral transistor is formed which functions as a base and a collector and serves as an injection element, and the Ni emitter layer 4, the P+ type second space region 7b, and the N-type collector region 8b are NPN) as the emitter and base of the transistor. , a vertical reverse-acting transistor is formed to act as a collector, and the collector of the horizontal transistor and the base of the vertical reverse-acting transistor are common, and I2L t-n in the pixel element.
has been completed.

Furthermore, an NPN bipolar transistor T- is constructed by the N-shaped ivy region 8C, the P-type space region 7c, and the N-type collector contact region.

Note that 9 is an oxide film formed on the surface, 10 is an injector electrode pattern, 11.14 is an emitter electrode pattern, 1
2.15 is a base electrode pattern, and 13.16 is a collector electrode pattern.

I2L has many special features such as simple manufacturing process, high degree of integration, and ability to coexist with ordinary bipolar integrated circuits. had the following shortcomings:

(1) Current amplification factor of reverse action NPN transistor (hereinafter β
up) is determined by the current amplification factor (hereinafter referred to as hFI) of a normal NPN transistor. (hereinafter referred to as BVOIO) will decrease.

(21 Normal NPN) To ensure the BVago of the transistor ((lower epitaxial layer concentration and reverse operation NP)
The effective epitaxial layer thickness (hereinafter referred to as Wepi) immediately below the base region of the N-transistor must be made large, and as a result, the operation speed decreases due to the accumulation of holes.

As a countermeasure to overcome the above drawbacks, the configuration shown in FIG. 3 has been developed. Figure 3 shows the conventional improved main I2L
FIG.

As shown in FIG. 3, ・Reverse operation NPN) Low concentration P-p5 impurity is deeply diffused into the base region of the transistor to form a first pace region 6fr. 9 degrees P+pox impurities are diffused to form a second pace region 7b'l. IL improved in this way
The system has the following advantages over the conventional configuration.

(1) βup of a reverse operation NPN transistor can be highly controlled independently of hFl of a normal NPN l-transistor.

(2) We can reduce We p i and improve operation speed.

(3) Since the bottom of the reverse operation NPN transistor is formed of a low gold concentration base region (first paste region), the emitter-base grounding capacitance can be reduced, and the operating speed, especially in low current, can be improved.

As mentioned above, it shows superior characteristics compared to the conventional Eco-L, but there are limits when aiming for even higher speeds.

The reason for this is that in I2L, Wepitl
-Make it as thin as possible and use a normal NPN transistor.
This is because it is necessary to form the first space region of a low-concentration, deep-junction, reverse-action NPN) transistor under process conditions that ensure Y and ω, and it is not possible to make Wepi 0. That is, since the first space region cannot reach the buried layer, there is a limit to the speed increase due to the accumulation of holes due to the emitter-base junction capacitance at the bottom of the first base region of the reverse operation NPN transistor. βup again
It is also difficult to make the first base region reach the buried layer from a control point of view.

(Objective of the Invention) The object of the present invention is to eliminate the above-mentioned drawbacks, and to reduce the β of I2L without reducing the breakdown voltage of ordinary bipolar transistors.
An object of the present invention is to provide a method for manufacturing a semiconductor device that achieves the same improvements in speed and operating speed.

[Structure of the Invention] A method for manufacturing a semiconductor device according to the present invention is a method for manufacturing a semiconductor device in which an I2L transistor and a normal bipolar transistor are formed on the same semiconductor substrate. a step of forming a brush 1 buried layer of conductivity type, and a diffusion coefficient of impurity larger than that of the impurity forming the first buried layer gold on the surface of the first buried layer of the other conductivity type in the I2L t-forming region; A step of forming a second buried layer of another conductivity type using an impurity having a diffusion coefficient, and a step of forming an epitaxial layer of another conductivity type on the semiconductor substrate on which the WXl and W2 buried layers are formed. and a region including at least the internal base region of the inverter transistor of I2L.
'F! A step of forming an i-type third region, and forming a junction with a higher concentration and shallower depth than the third region in the base ψ region of the normal bipolar transistor, the injector region of I2L, and the external base region of the inverter transistor. The method is characterized in that it includes a step of simultaneously forming a fourth region of electric type, and a step of simultaneously forming a collector region of the inverter transistor and an emitter region of the normal bipolar transistor.

(Example) Embodiments of the present invention will be described below with reference to the drawings.

FIGS. 1(a) to 1(c) are cross-sectional views shown in order of steps to explain and explain one embodiment of the present invention.

First, as shown in FIG. 1(a), an N+ type impurity, such as antimony (S b )f:, is diffused into a P type substrate 1.
A + type buried layer 2 is formed, and then an impurity having a larger diffusion coefficient than the impurity formed in the first buried waste, for example, phosphorus (
P) Ions are implanted only into the eI 2L portion to form an N-type second buried layer 3't-. Next, an epitaxial layer 4 is grown, and a P+ type impurity is diffused from the surface of the epitaxial layer 40 to form an insulating isolation region 5t-, and then a P-type impurity (for example, boron CB) t- ion is added to the epitaxial layer 40 from the surface of the epitaxial layer 40 in the X2L formation region. The base region 6 of the P-type cylinder 1 is formed by implantation. At this time, the first base region is formed to include at least the internal base region of the I2L inverter transistor. Here, it is desirable that the second buried layer 3 be shaped so as to be in contact with the first base region.

Next, as shown in FIG. 1(b), an epitaxial layer 4 is formed.
from the surface of
pm second base region 7bl is formed.

At this time, a P type injector region 7a and a P+ type base region 7C of a normal bipolar transistor are also formed at the same time.

Next, as shown in FIG. 1(C), an epitaxial layer 4 is formed.
N+ type impurities are diffused from the surface of the transistor to simultaneously form the emitter contact region 8a and collector region 8b of I2L and the emitter region 8c and collector contact region +3dt- of a normal bipolar transistor. Thereafter, predetermined contact opening areas of the emitter, base, collector, and injector are oxidized with 11W9t-Esotin, and each electrode pattern 10. ．． 11゜12.13,14,15.1
6t-form.

Through the above steps, a semiconductor device according to an embodiment of the present invention is completed.

According to this embodiment of the present invention, since the second buried layer is formed in I2L, Wepj becomes small,
Hole accumulation is reduced and operation speed is increased. Furthermore, when the second buried layer t-@1 is formed in contact with the base region, Wepi=0, and the υ operation speed is further improved, and the emitter injection effect of the inverter transistor is also increased, so βup is further increased. improves.

Note that βup of the inverter transistor and hFl of the normal bipolar transistor can be controlled independently as before.
Needless to say, the withstand voltage of a normal bipolar transistor can be ensured.

It should be noted that the present invention is not limited to the above embodiments, and the same effect can be obtained even if the polarity is changed, for example.

(Effect of the invention) As explained above, according to the present invention, βup of I2L
It is possible to control the hFIl of a normal bipolar transistor completely independently, and it is possible to realize improvements in β suppression and operating speed compared to the conventional method without reducing the withstand voltage of a normal bipolar transistor.

[Brief explanation of the drawing]

Figures 1 (a) to (c) are cross-sectional views shown in process steps to explain one embodiment of the present invention, and Figure 2 is a cross-section of a conventional integrated circuit in which I'L and bipolar transistors coexist. figure,
3rd V is a cross-sectional view of a conventional integrated circuit with improved I2L and bipolar transistors. 1...P type substrate, 2...N+ type first buried layer, 3...N type second buried layer, 4...
N-type epitaxial layer, 5...P-type insulation isolation region, 6...P-type first base region, 7a...
...P+ type injector area, 7b...P
Type second base area, 7C...-Pfi pace area,
13a...N+ type emitter contact region, 8
b...N+ type collector region, 8C...
N+ type emitter region, 8d...N type collector contact region, 9...Oxide film, 10...
・Injector electrode pattern, 11.14...
Emitter electrode pattern, 12.15...Base electrode pattern, 13°16...Collector electrode pattern. Figure 3

Claims (2)

[Claims] (1) In a method for manufacturing a semiconductor device in which an I^2L and a normal bipolar transistor are formed on the same semiconductor substrate,
forming a first buried layer of another conductivity type in each element formation region of a semiconductor substrate of one conductivity type; forming a second buried layer of a different conductivity type with an impurity having a diffusion coefficient greater than the diffusion coefficient of the impurity forming the first buried layer; and a semiconductor in which the first and second buried layers are formed. A step of forming an epitaxial layer of another conductivity type on the substrate, and I^2L
forming a third region of one conductivity type in a region including at least the internal base region of the inverter transistor;
simultaneously forming a fourth region of one conductivity type with a higher concentration and a shallower junction than the third region in the injector region of the inverter transistor and the external base region of the inverter transistor; 1. A method of manufacturing a semiconductor device, comprising the step of simultaneously forming an emitter region of a transistor. (2) Claim (1) characterized in that the impurity for forming the first buried layer is Sb or As, and the impurity for forming the second buried layer is P. A method for manufacturing a semiconductor device according to section 1.