JPH01246873A - Semiconductor device - Google Patents

Abstract

PURPOSE:To improve a Schottky diode in a breakdown strength and a property by a method wherein a semiconductor device is provided with the Schottky diode, where an electrode constituting the diode is connected with a impurity doped semiconductor of a guard ring formed of an impurity region around the electrode. CONSTITUTION:A semiconductor device is provided, where an electrode constituting a Schottky diode(SBD) or a Schottky electrode 32 formed of, a Schottky metal and a guard ring 33 formed of a p-type impurity region are formed on an n-type semiconductor region 31. In this process, an impurity doped semiconductor 34 forming the guard ring 33 and the electrode 32 are provided as being connected with each other. By this method, the Schottky diode 32 is improved in a breakdown strength owing to the guard ring 33, and the SBD 32 can be prevented from varying in characteristic due to an inconstant space between the guard ring 32 and the electrode 32.

Description

[Detailed description of the invention] The present invention will be explained in the following order.

A. Field of industrial application B. Overview of the invention C. Prior art D. Problem to be solved by the invention E. Means for solving the problem (Fig. 1) F. Effect G. Example H. Effect of the invention A. Field of industrial application The present invention relates to a semiconductor device, particularly a semiconductor device having a Schottky diode on a semiconductor substrate, or a bipolar transistor together with a Schottky diode, in particular a bipolar transistor whose emitter and base regions are respectively in contact with an impurity-containing semiconductor layer, and in which impurities are introduced. The present invention relates to a semiconductor device including a so-called double polysilicon type bipolar transistor formed by.

B. Summary of the Invention The present invention provides a semiconductor device having a Schottky diode having a guard ring on a semiconductor substrate, in which the guard ring is formed by introducing impurities from an impurity-containing semiconductor layer, and the Schottky electrode is The structure is such that it is connected to an impurity-containing semiconductor layer.

Further, in the present invention, in a semiconductor device in which a Schottky diode and a bipolar transistor are integrally formed on a semiconductor substrate, the guard ring of the Schottky diode is formed by forming the same impurity anastomosis as the impurity-containing semiconductor layer in contact with the base region of the bipolar transistor. The structure is formed by introducing impurities from a layer, and the impurity-containing semiconductor layer and the Schottky electrode are connected.

The present invention reliably improves the withstand voltage and stabilizes the characteristics of the Schottky diode and further reduces the occupied area by employing the above-mentioned configurations.

C. Conventional technology A Schottky diode (hereinafter abbreviated as SBD), which consists of a diode using a Schottky barrier, is a TTL
() transistor transistor logic) and ECL
It is used to speed up logic circuits using bipolar transistors, such as (emitter-coupled logic).

Figure 2 shows the SBD between the base and collector of transistor Q.
An example of LS-TTL (low power Schottky TTL) clamped with In this case, since the base-collector is clamped by SBD which has a forward voltage Vf lower than the base-emitter voltage VBE, when the transistor Q is on, the collector-emitter voltage VCE
VCE = VER - Vf, and since VCE > VCE (sat) (Vci (sat) is the collector-emitter saturation voltage), it becomes difficult to saturate, and the speed increases.

Figure 3 is an example of an SBD load switching type ECLXRAM (random access memory) cell, which has a high resistance RH
By connecting the SBD in parallel with the SBD, low power consumption and high speed can be achieved.

When this SBD is applied particularly to LS-TTL, the SBD is configured with a guard ring because of the requirement to increase the reverse breakdown voltage. FIG. 4 shows a cross-sectional view of an SBD having this guard ring. In this example, a Schottky metal, that is, a Schottky electrode (2) is deposited on an n-type semiconductor region (1). A Schottky barrier (3) is formed around the Schottky barrier (3), and a guard ring (4) is provided around the Schottky barrier (3) by a p-type semiconductor region in the figure, which has a conductivity type different from that of the semiconductor region (1). It is designed to reduce electric field concentration at the peripheral edge and achieve high withstand voltage. Figure 5 is a current-voltage characteristic curve diagram of the SBD. In Figure 5, the solid line curve (5) shows the forward current-voltage characteristic curve, and the broken line curve (6) shows the SBD without the guard ring (4). Current in the opposite direction of −
A voltage characteristic curve diagram is shown. When the SBD is provided with the guard ring (4) shown in Fig. 4, the chain line curve (
The characteristic curve as shown in 7) shifts, and the withstand voltage is improved.

However, in a semiconductor device equipped with such an SBD, providing a guard ring poses problems such as complicating the process and causing variations in the SBD area due to the provision of the guard ring, resulting in variations in characteristics. be.

On the other hand, in recent years, a low resistance base electrode extraction region (that is, a graft base region) and an emitter region have been formed by introducing impurities into a semiconductor substrate from an impurity-containing semiconductor layer, for example, a polycrystalline silicon layer. The so-called double-polysilicon bipolar transistor, which has a self-alignment (self-alignment) for each position of the emitter and base and the electrodes leading from these, has been attracting attention because of its small area and high speed. Bathing.

It has been proposed to configure, for example, an LS-TTL by combining such a double polysilicon type bipolar transistor and an SBD equipped with a guard ring. In order to avoid the increase in the number of manufacturing steps caused by this, a method has been proposed in which, for example, the 5BII guard ring is formed by using an impurity-containing semiconductor layer for forming the graft base region of a double polysilicon bipolar transistor. There is. An example of this is disclosed in, for example, Japanese Patent Laid-Open No. 1260/1983.

An example of a structure in which a graft base region of a double polysilicon bipolar transistor, a guard ring of an SBD, etc. are formed at the same time will be described with reference to FIG. In this example, an n-type collector buried region (12) with a high impurity concentration is formed on a p-type semiconductor substrate (11), and an n-type semiconductor layer (13) is epitaxially grown on this semiconductor. A substrate (14) is constructed, and 5i is formed on the semiconductor substrate Fi (14), that is, on the semiconductor N (13).
(h An insulating layer (15) is formed, and a first impurity semiconductor layer (16) doped with a first p-type impurity through ring-shaped windows (15a) and (15b) bored in the insulating layer (15). is formed, and the first impurity semiconductor Fit (16
) are introduced into the p-type graft base region (17) and guard ring region (18), respectively.
is formed. In this case, the first impurity semiconductor layer (16) covers the surface including the inner peripheral edge of the first impurity semiconductor layer (16).
An iO2 insulating layer (19) is deposited. Further, in a portion surrounded by the graft base region (17), a p-type base operating region, so-called intrinsic base region (20), is formed by implanting impurity ions, for example. A second impurity semiconductor i (21) containing impurities is deposited on this base operating region (20), and an n-type emitter region (23) is formed by introducing impurities therefrom. However, in this case, the emitter region (23) and the first impurity semiconductor layer (16) which also serves as the base extraction electrode
), a side wall made of a 5i (h insulating layer or a silicosinonitride film) is provided at the inner peripheral edge of the first impurity semiconductor layer (16) on the graft base region (17). (24) is formed.

In this case, the forming part of the SBD, that is, the guard ring (18
) is also formed on the inner peripheral edge of the insulation R (19) and a side wall (24), and a Schottky metal, that is, a Schottky electrode (2
5) is formed. Therefore, in this case, the Schottky barrier SB and the guard ring (1
8) means that the presence of the sidewall (24) makes it difficult to improve the pressure resistance stably and reliably due to the presence of the sidewall (24), or that the presence of the sidewall (24) makes the SBD
There are problems such as the area becomes unstable, resulting in variations in characteristics.

In the structure shown in Figure 6, the guard ring (
18) and the Schottky electrode (25), it is necessary to increase the diffusion width of the impurity from the first impurity semiconductor layer (16). The width of the base region (17) also becomes large, and this comes into contact with the emitter region (23), resulting in a decrease in the reverse withstand voltage V ebo between the emitter and base, or the collector of injected carriers passing through the graft base region (17). The generation of a path toward the base substantially increases the base width, resulting in a decrease in the current amplification factor hpi, and furthermore, causes problems such as a decrease in the transition frequency ft and deterioration of high frequency characteristics.

D Problems to be Solved by the Invention The present invention solves problems such as variations in characteristics of the SBD and instability of breakdown voltage in a semiconductor device having an SBD equipped with the above-mentioned guard ring without deteriorating the characteristics of a bipolar transistor. (solve.

E. Means for Solving the Problems In the present invention, as shown in FIG. In a semiconductor device having a Schottky electrode (32) made of metal and a guard ring (33) made of a p-type impurity region in the illustrated example of the second conductivity type surrounding the SBD, an impurity forming the guard ring (33) Containing semiconductor layer (
34) and the electrode (32) are connected.

Further, in the present invention, a bipolar transistor Tr and a Schottky diode SB are provided on the semiconductor region (31).
In the semiconductor device comprising D, the semiconductor region (31
), a first impurity-containing semiconductor layer (34) is provided extending to at least the base region (35) of the bipolar transistor Tr and the surrounding position of the SBD, and the first impurity-containing semiconductor layer (34) is provided on the semiconductor region (31). A graft base region (351) and a guard ring (33) that are in contact with the impurity-containing semiconductor layer (34) and have the same conductivity type as the impurity of the impurity-containing semiconductor layer (34).
Schottky electrode (3
2) and an impurity-containing semiconductor layer (34) are connected.

F Function According to the configuration of the present invention described above, the guard ring (3
3) and the impurity-containing semiconductor layer (34) constituting this, a guard ring (33) is formed at a distance from the Schottky barrier, resulting in a high breakdown voltage effect. It is possible to avoid the extinction or instability of
It is possible to avoid variations in the occupied area of the SBD and therefore characteristics due to the presence of an unstable interval between the SBD and the Schottky electrode (32).

G. Embodiment Referring to FIGS. 1A to 1, an example of the case where the device of the present invention is applied to a semiconductor device comprising a combination of an npn bipolar transistor Tr and an SBD provided with a guard ring will be described to facilitate understanding thereof. The order of each manufacturing process will be explained one by one along with an example manufacturing method.

First, as shown in FIG. 1A, a p-type silicon semiconductor substrate (36) having a (111) crystal plane as its main surface is prepared, and an n-type high concentration collector buried region (37) is provided on its -main surface. ) are selectively formed, and p-type channel stopper regions (38) for isolating each element are formed by selective diffusion or the like.

As shown in FIG. 1B, on the substrate (36), a semiconductor layer (31) of a different conductivity type, for example, an n-type, that is, an n-type semiconductor region (31) is epitaxially grown (11).
1) Construct a semiconductor substrate (39) whose main surface is a crystal plane.

As shown in FIG. 1C, an oxidation-resistant mask layer (41) made of silicon nitride SiNx is deposited on the semiconductor layer (31) of the semiconductor substrate (39) via a 5i (h buffer N (40)). Then, this mask layer (
41) Etching resist N on top (42) For example, photoresist is selectively deposited on areas other than those where a thick local oxide film is to be formed.

Using the etching resist Ti (42) as a mask, the first
As shown in the figure, the oxidation-resistant mask layer (41) is selectively etched by, for example, RIB (reactive ion etching), and then the 5iOF buffer layer (41) below this is etched.
0), for example, RIB L, and the semiconductor layer below this (
31) to the required depth by RIE, for example, to form a recess (43).
) to form.

Next, as shown in FIG. 1E, for example, the etching resist layer (42) is removed and the inside of the recess (43), that is, the part where the oxidation-resistant mask layer (41) is not present, is thermally oxidized to form a thick oxide film (44). ) in the field part, and electrically in the semiconductor layer (
31) into the parts to be divided.

As shown in FIG. 1F, the oxidation-resistant mask layer (41) is removed by etching, and, for example, a 5i02 layer (45) is formed by CVD (chemical vapor deposition), and on top of this, for example, a photoresist layer is further formed. (46) is spin-coded to substantially flatten the surface.

As shown in FIG. 1G, so-called etch-back is performed from the surface flattened by the 5i (h layer (45) and the photoresist 14j (46) to a position where the semiconductor layer (31) is exposed to the outside, and the selected Specifically, an n-type impurity is ion-implanted to form a collector electrode extraction region (47).

As shown in FIG. 1H, a 5i02 insulating film (4 days) is formed by surface thermal oxidation or CVD method. and,
An etching resist such as a photoresist layer (49) is deposited on top of this, and finally a window (49) is formed in the area where the base region and guard ring of the bipolar transistor are to be formed.
9e) and (49c) are formed.

As shown in FIG. 1I, the photoresist N (49) explained in FIG.
5i(h insulation film (48) through 49B) and (49c)
) are drilled with windows (48B) and (48c). Thereafter, the photoresist layer (49) is removed and a semiconductor layer, such as a polycrystalline silicon layer, is formed on the entire surface by CVD or the like, and n-type impurity ions such as B", BF2+, etc. are ion-implanted into the first layer. In this case, the concentration distribution of the ion implantation is such that the peak position does not reach the interface with the semiconductor substrate (the interface with the semiconductor layer (31)), that is, the semiconductor layer (34) contains impurities. (34) to form such that it exists in

Next, as shown in FIG. 1J, an etching resist, such as a photoresist layer (51), is applied on the semiconductor layer (34), and a window (51s) is formed in the part where the Schottky electrode of the SBD will finally be formed. A window (34s) is formed by etching the underlying semiconductor layer (34) through this window (51s) by RIH method or the like.

As shown in FIG. 1K, the photoresist Ji (51) in FIG. 1J is removed, and the window (34s) of the semiconductor layer (34) is removed.
) After forming an insulating layer (52), for example 5i02, on the entire surface by, for example, CVD, an etching resist such as photoresist (5
3), a window (53B) is formed in the part that will eventually form the base operating region of the bipolar transistor, and a window (53B) is formed in the insulating layer (52) through this window (53B).
2B).

As shown in the first diagram, a window (34B) is formed in the semiconductor layer (34) through the window (52B). The method of drilling the window (34e) in this case is, for example, disclosed in Japanese Patent Application Laid-Open No. 60-2405.
The method disclosed in No. 9 may be used. That is, in this case, first, a recessed portion is formed by anisotropic dry etching, for example, RIH, at a depth beyond the portion of the semiconductor layer (34) having the impurity concentration peak position of the impurity ion implantation described in FIG. Thereafter, an annealing treatment is performed to diffuse impurities in the semiconductor N (34) as necessary, and then an etching solution such as XOH etching solution or A1 ( A window (34B) is formed in the semiconductor layer (34) by etching using an etching solution (mixture of amine, pyrocatechol, and water). When such a method is used, the semiconductor layer (34), that is, polycrystalline silicon, is substantially exposed to the XOH etching solution or AP etching solution.
Relatively fast etching speed compared to W etching solution.
The etching speed of the semiconductor layer (31) is relatively high due to the presence of (100) crystal planes.
) The (111) crystal plane of the semiconductor N (31) is exposed everywhere, and the etching rate decreases rapidly. (34B
). In this crystallographic anisotropic etching, even if polycrystalline silicon is doped with impurities at a high concentration, the etching performance will be reduced. For M (34), the peak position of the impurity concentration is selected in advance at a position that does not reach the interface with the semiconductor layer (31), and the part having this peak is removed by etching with RIH, thereby making it possible to avoid impurity doping. Even if the semiconductor layer (34) is etched, the difference in etching rate between the polycrystalline semiconductor layer and the single-crystalline semiconductor layer can be reliably maintained. And then this window (3
4e), a p-type impurity such as B+ or BP2+ ions is ion-implanted into the semiconductor layer (31) to form a base operating region (352), and then a window (52B) is formed on the entire surface.
) (34B) and further insulation N (
52) is deposited by CVD, annealing is performed to activate the base operating region (352), and impurities in the semiconductor layer (34) are removed from the semiconductor layer (semiconductor region) (31).
are introduced to form a graft base region (351) and a guard ring (33), respectively.

As shown in FIG. 1M, RIE etching, that is, anisotropic etching is performed on the entire surface of the insulating layer (52) to form a thin part of the window (52) in the one-layer structure compared to other parts of the window (34B).
Drill B→. In this case, the inner periphery of the windows (52B) and (34B) in the first diagram is substantially insulated N (52).
Due to the large thickness of the window (52B2), a sidewall (
53) is formed. Also, in this case, it is important to note that S
In the electrode forming part of the BD, since no windows are formed, sidewalls do not occur, and there is no sidewall at the periphery of the base operating region (352) that will eventually become the bipolar transistor Tr. The only difference is that a side wall (53) is formed.

As shown in FIG. 1N, a semiconductor layer, for example, a polycrystalline silicon layer doped with impurities, is formed on the entire surface including the inside of the window (52B2) where the sidewall (53) is present, or a polycrystalline silicon layer is formed. After formation, impurity ions are implanted into this to form a second impurity-containing semiconductor layer (54).
form. Then, an overcoat such as a SiO2 insulating layer, that is, an insulating layer (55) for preventing out-diffusion is formed on the entire surface by CVD or the like. Thereafter, an annealing process is performed to introduce impurities from the second impurity-containing semiconductor layer (54) into the semiconductor layer (31) to form an n-type emitter region (56).

As shown in FIG. 10, the overcoat insulating layer (55) is removed, and the second impurity-containing semiconductor layer (54) is etched away except for the emitter extraction electrode portion.

Further, a window (57) is provided in the insulating layer (52) and the first impurity-containing semiconductor layer (34) on the portion surrounded by the guard ring (33), spanning over or in contact with the guard ring (33). A Schottky metal such as Pt is drilled through this window (57).

After evaporating W, Mo, etc. over the entire surface, unnecessary parts are removed and patterned, and then the emitter extraction electrode part (second
AI! on the impurity-containing semiconductor layer (54)). An emitter electrode (58) is formed by forming a metal electrode by full-surface vapor deposition and selective etching. In this way, an n-type semiconductor region (semiconductor layer) can be formed on a common semiconductor substrate (j9).
(31) is a collector region, and on top of this is a graft base region (35I) and a base region (35) with a base operating region (352) surrounded by this, and on the base operating region (352). An npn-type bipolar transistor Tr in which an n-type emitter region (56) is selectively formed is formed, and a guard ring (3) is formed.
3) and a first impurity-containing semiconductor layer (34) thereon.
), that is, in contact with the guard ring (33), a semiconductor device is constructed in which a Schottky barrier diode SBD is formed with a Schottky electrode (32) formed so that a Schottky barrier can be formed in contact with the guard ring (33). .

In the example described above, the present invention is applied to a semiconductor device that is a combination of an npn bipolar transistor and an SBD. Various modifications and changes can be made, such as the ability to obtain a semiconductor device by combining SBDs.

H Effects of the Invention According to the device of the present invention described above, the impurity-containing semiconductor layer (34) forming the guard ring (33), that is, in contact with the guard ring (33),
), the Schottky electrode (32) of the Schottky barrier diode is formed in contact with the Schottky barrier diode so that there is no side wall between the two, thereby surely improving the breakdown voltage of the Schottky barrier diode. At the same time, the existence of sidewalls can cause unnecessary increase in surface bond or unstable guard ring (33
) can be avoided, and a highly reliable semiconductor device with stable characteristics can be constructed.

[Brief explanation of the drawing]

Fig. 1 A-0 is a manufacturing process diagram for explaining an example of the device of the present invention, Fig. 2 is an LS-TTL circuit example, and Fig. 3 is an SB-TTL circuit diagram.
D Load switching type ECL RAM cell circuit example, Figure 4 is S
FIG. 5 is a diagram showing a general configuration of a BD, FIG. 5 is a current-voltage characteristic curve diagram of an SBD, and FIG. 6 is a sectional view of a conventional device. (31) is a semiconductor region, Tr is a bipolar transistor, SBD is a Schottky barrier diode, (35) is a base region, (351) is a graft base region, (35
2) is the base operating region, (56) is the emitter region, (3
3) is a guard ring, (32) is a Schottky electrode, (
34) and (54) are first and second impurity-containing semiconductor layers.

Claims (1)

[Claims] 1. A semiconductor device having an electrode forming a Schottky diode on a semiconductor region of a first conductivity type, and a guard ring consisting of an impurity region of a second conductivity type surrounding the Schottky diode, A semiconductor device characterized in that the impurity-containing semiconductor layer forming a guard ring and the electrode are connected. 2. In a semiconductor device integrally comprising a bipolar transistor and a Schottky diode on a semiconductor region, an impurity is present on the semiconductor region extending at least to a base region of the bipolar transistor and a position around the Schottky diode. A containing semiconductor layer is provided, and a base region and a guard ring are provided on the semiconductor region, in contact with the impurity-containing semiconductor layer, and having the same conductivity type as an impurity in the impurity-containing semiconductor layer, and an electrode forming the Schottky diode. A semiconductor device characterized by being connected to the impurity-containing semiconductor layer.