JPS6167084A - Document display unit - Google Patents
Document display unitInfo
- Publication number
- JPS6167084A JPS6167084A JP59187937A JP18793784A JPS6167084A JP S6167084 A JPS6167084 A JP S6167084A JP 59187937 A JP59187937 A JP 59187937A JP 18793784 A JP18793784 A JP 18793784A JP S6167084 A JPS6167084 A JP S6167084A
- Authority
- JP
- Japan
- Prior art keywords
- video memory
- memory
- line
- buffer
- data
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
【発明の詳細な説明】
〔発明の利用分野〕
本発明は文書表示装置に係り、特に、大容＃なビデオメ
モリをもち、高精細表示を行なうために、ビデオメモリ
のアクセス負荷が高い装置において高速に二次元の符号
化、復号化に好適な、ビデオメモリアクセス方式の文書
表示装置に関する。[Detailed Description of the Invention] [Field of Application of the Invention] The present invention relates to a document display device, and is particularly applicable to a device having a large-capacity video memory and requiring a high video memory access load in order to perform high-definition display. The present invention relates to a video memory access document display device suitable for high-speed two-dimensional encoding and decoding.
従来の装置は、ビデオメモリの内容を二次元の符号化、
復号化を行なう場合、−ラインの符号化、復号化の処理
には、現ラインと一ライン前のラインをビデオメモリに
アクセスする必要がめった。Conventional devices encode the contents of video memory in two dimensions,
When performing decoding, it is often necessary to access the video memory for the current line and the previous line in order to encode and decode the -line.
しかし、表示の高精細化につれ、ビデオメモリのアクセ
ス負荷が高＜ ’ｘ ｂ 、高速な符号化、復号化がで
きなかった。なお、この種の装置として関連するものＫ
は、例えば、特開昭５８−６６９８９号、同５８−８３
４３７号公報等が挙げられる。However, as the definition of display increases, the access load on the video memory becomes high, making it impossible to perform high-speed encoding and decoding. In addition, related devices of this type K
For example, JP-A-58-66989, JP-A-58-83
Publication No. 437 and the like can be mentioned.
本発明の目的は、ビデオメモリへのアクセス数を半減し
、かつ高速に符復号化を行うことのできる文書表示装置
を提供するにある。SUMMARY OF THE INVENTION An object of the present invention is to provide a document display device that can reduce the number of accesses to a video memory by half and perform high-speed encoding and decoding.
本発明は、三ライン以上のバッファメモリとデータ転送
部を設はデータ転送部によシビデオメモリ、バッファメ
モリ間の転送を行ないながら、二次元符復号化部からの
アクセスは高速アクセスできるバッファメモリによりア
クセスすることによシ、ビデオメモリへのアクセスは一
ラインの符復帰化に対し、−ラインのアクセスでよくな
り、ビデオメモリへのアクセス数を半減させ高速処理化
したものである。The present invention has a buffer memory with three or more lines and a data transfer section, and while the data transfer section performs transfer between the video memory and the buffer memory, the buffer memory allows high-speed access from the two-dimensional code/decoder section. By accessing, the video memory can be accessed by -line access for one line of code reverting, and the number of accesses to the video memory is halved and processing speed is increased.
以下、本発明の一実施例ｆｆ、第１図及び第２図により
説明する。第１図は全体構成であり、入出力部４、二次
元符復号化処理部１、バックアメモリ５、ビデオメモリ
２、表示部３は、図示のように接続されている。また、
データ転送部６は、ビデオメモリ２とバッファメモリ５
間のデータ転送用に接続され、二次元符復号化処理部ｌ
は、バッファメモリ５ｔｌ−介してビデオメモリ２とデ
ータの授受を行なう。第２図はバッファメモリ５の使用
手順を示したもので、バッファメモリに三ライン分金持
った例を示す。以下、符号化処理を例にとシ説明する。Hereinafter, one embodiment ff of the present invention will be explained with reference to FIGS. 1 and 2. FIG. 1 shows the overall configuration, and the input/output section 4, two-dimensional code/decoding processing section 1, backup memory 5, video memory 2, and display section 3 are connected as shown. Also,
The data transfer unit 6 includes a video memory 2 and a buffer memory 5.
A two-dimensional code/decoder processing unit is connected for data transfer between
exchanges data with the video memory 2 via the buffer memory 5tl. FIG. 2 shows the procedure for using the buffer memory 5, and shows an example in which the buffer memory has three lines worth of money. The encoding process will be described below as an example.
ビデオメモリ内のデータをデータ転送部６により最初に
第一２イン目のデータをＡバラ、７．７へ転送する。次
に、第三ライン目のデータをｉシクツファへ転送すると
同時に、へバッファのデータを用いて、第一ラインの符
号化を二次元符復号化処理部ｌが行なう。次に、第三ラ
イン目のデータ金Ｃバッファに転送してＡバッファ及び
Ｂバッファのデータを用いて第三ライン目の符号化を−
行なう。次に、第１！！ａライン目のデータ？Ａバッフ
ァへ転送して、Ｂバッファ及びＣバッファのデータを用
いて第三ライン目の符号化を行なう。以降、同様に処理
金続ける。これにより、二次元符号化時に、−ライン処
理に対し、アクセス時間のかかるビデオメモリへのアク
セスは、実質−ラインですみ、高速で符号化処理を行な
うにあたり極めて有用である。なお、二次元復号化につ
いても同様にして高速化が実現できる。The data in the video memory is first transferred by the data transfer unit 6 to the first and second inputs to the A-bar, 7.7. Next, while transferring the third line data to the i-switch buffer, the two-dimensional code/decoder l encodes the first line using the data in the i-buffer. Next, the third line data is transferred to the C buffer and the third line is encoded using the data in the A buffer and B buffer.
Let's do it. Next, number one! ! A-line data? The data is transferred to the A buffer, and the third line is encoded using the data in the B and C buffers. From then on, processing money will continue in the same way. As a result, during two-dimensional encoding, access to the video memory, which takes an access time, is essentially only one line, compared to -line processing, which is extremely useful for high-speed encoding processing. Note that speeding up of two-dimensional decoding can be achieved in the same manner.
本発明によれば、二次元符復号化処理においてアクセス
時間のかかるビデオメモリへのアクセスは、−ラインの
処理あたり一ラインのアクセスででき、かつ、ビデオメ
モリとバッファメモリ間の転送を、符復号化処理と並列
して実行できるので、二次元符復号化処理を高速に実行
できる効果がある。According to the present invention, access to the video memory which takes a long access time in two-dimensional coding/decoding processing can be performed by accessing one line per line processing, and the transfer between the video memory and the buffer memory can be performed by coding/decoding. Since it can be executed in parallel with the encoding process, it has the effect of allowing the two-dimensional encoding/decoding process to be executed at high speed.
第１図は本発明の一実施例の全体構成図、第２図は第１
図におけるパックアメモリ構成図である。
ｌ・−・二次元符復号化処理部、２・・・ビデオメモリ
、３・・・表示部、４・・・入出力部、５・・・ノ（ラ
フアメモリ、６・・・データ転送部。FIG. 1 is an overall configuration diagram of an embodiment of the present invention, and FIG.
It is a pack memory block diagram in a figure. 1... Two-dimensional code/decoding processing section, 2... Video memory, 3... Display section, 4... Input/output section, 5... N (rough memory, 6... Data transfer section.
Claims (1)
表示制御部、前記ビデオメモリの内容を符号化し入出力
部へ転送し、また、前記入出力部からのデータを復号化
し前記ビデオメモリへ転送する画像符復号化処理部から
なる文書表示装置において、 前記ビデオメモリと前記画像符復号化処理部の間にバッ
ファメモリとデータ転送装置を設けたことを特徴とする
文書表示装置。[Claims] 1. A video memory, a display control unit that displays the contents of this video memory, encodes the contents of the video memory and transfers it to an input/output unit, and decodes data from the input/output unit. A document display device comprising an image encoding/decoding processing section for transferring to the video memory, characterized in that a buffer memory and a data transfer device are provided between the video memory and the image encoding/decoding processing section. .
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59187937A JPS6167084A (en) | 1984-09-10 | 1984-09-10 | Document display unit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59187937A JPS6167084A (en) | 1984-09-10 | 1984-09-10 | Document display unit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6167084A true JPS6167084A (en) | 1986-04-07 |
Family
ID=16214787
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP59187937A Pending JPS6167084A (en) | 1984-09-10 | 1984-09-10 | Document display unit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6167084A (en) |
-
1984
- 1984-09-10 JP JP59187937A patent/JPS6167084A/en active Pending
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US6378030B1 (en) | Method and apparatus for processing video data | |
| US6820087B1 (en) | Method and apparatus for initializing data structures to accelerate variable length decode | |
| US6313766B1 (en) | Method and apparatus for accelerating software decode of variable length encoded information | |
| JPS62230164A (en) | Degital signal coding/decoding circuit | |
| JPS6167084A (en) | Document display unit | |
| JP2738136B2 (en) | Blocking device | |
| JPH07168933A (en) | Generation circuit of zigzag scan address | |
| JPS62195979A (en) | Facsimile code converter | |
| JPS61149989A (en) | Semiconductor memory | |
| JPH10105672A (en) | Computer and memory integrated circuit with operation function to be used in this computer | |
| JPH04258084A (en) | Code rule converter | |
| JPH0353388A (en) | Two-dimensional encoded data decoding and reducing device | |
| JPH01194672A (en) | Picture information decoder | |
| KR100252636B1 (en) | 8x8 block address generating circuit for jpeg coding | |
| JPH0229834A (en) | Image processor | |
| JP2584744B2 (en) | Data transmission equipment | |
| JPS63292769A (en) | Compressing method for picture data | |
| JPS63156455A (en) | Method for constituting hardware of communication terminal equipment for multimedia | |
| JPS58215868A (en) | Line memory circuit for encode-decoder of facsimile for suppressing two dimensional redundancy | |
| JPS63137376A (en) | Rapid rotating circuit | |
| JPS62232275A (en) | Picture recording and reproducing device | |
| JPS63287265A (en) | Picture processing device | |
| JP2002247378A (en) | Video memory control method for compressed image data | |
| JPH01195771A (en) | Two-dimensional picture coding device | |
| JPH07230543A (en) | Picture data compressing device |