JPS6165558U - - Google Patents

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Publication number
JPS6165558U
JPS6165558U JP15549185U JP15549185U JPS6165558U JP S6165558 U JPS6165558 U JP S6165558U JP 15549185 U JP15549185 U JP 15549185U JP 15549185 U JP15549185 U JP 15549185U JP S6165558 U JPS6165558 U JP S6165558U
Authority
JP
Japan
Prior art keywords
code
character
circuit
memory
register
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP15549185U
Other languages
Japanese (ja)
Other versions
JPS625728Y2 (en
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP1985155491U priority Critical patent/JPS625728Y2/ja
Publication of JPS6165558U publication Critical patent/JPS6165558U/ja
Application granted granted Critical
Publication of JPS625728Y2 publication Critical patent/JPS625728Y2/ja
Expired legal-status Critical Current

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Description

【図面の簡単な説明】[Brief explanation of drawings]

第1図はこの考案を電子式翻訳機に適用した一
実施例の回路ブロツク図、第2図は英語のキヤラ
クタコードを示す図、第3図は変換回路8の具体
的な回路構成図、第4図A,Bは夫々、従来また
は本実施例における単語のコード化の一例を示す
図、第5図は従来または本実施例における単語を
コード化した場合のキヤラクタ数を比較した図、
第6図は他の実施例の要部の回路構成図である。 1……キー入力部、2……制御部、3,9,1
1……レジスタ、4……アドレス指定回路、5…
…比較回路、6……表示部、7……ROM、8…
…変換回路、18……検出回路、19……デコー
ダ。
FIG. 1 is a circuit block diagram of an embodiment in which this invention is applied to an electronic translator, FIG. 2 is a diagram showing English character codes, and FIG. 3 is a specific circuit configuration diagram of the conversion circuit 8. 4A and 4B are diagrams showing examples of word encoding in the conventional method and the present embodiment, respectively; FIG. 5 is a diagram comparing the number of characters when words are encoded in the conventional method and the present embodiment;
FIG. 6 is a circuit diagram of main parts of another embodiment. 1... Key input section, 2... Control section, 3, 9, 1
1...Register, 4...Addressing circuit, 5...
... Comparison circuit, 6 ... Display section, 7 ... ROM, 8 ...
...Conversion circuit, 18...Detection circuit, 19...Decoder.

補正 昭60.11.11 考案の名称を次のように補正する。 考案の名称 キヤラクタコード変換装置 実用新案登録請求の範囲を次のように補正する
Amendment November 11, 1980 The name of the invention is amended as follows. Title of the invention Character code conversion device The scope of the claims for utility model registration is amended as follows.

【実用新案登録請求の範囲】 1つのコードに1キヤラクタを対応付けると共
に、このコードと同一ビツト数からなる1つのコ
ードに複数のキヤラクタを対応付け、これら各コ
ードにより表わされるキヤラクタ情報を記憶する
メモリと、このメモリのアドレスを指定するアド
レス指定回路と、このアドレス指定回路により指
定された上記メモリのアドレスから読み出したキ
ヤラクタ情報を記憶する第1のレジスタと、この
第1のレジスタに記憶されたキヤラクタ情報を1
キヤラクタコードずつ読み出し、該コードが複数
キヤラクタが対応付けられている圧縮コードかど
うかを検出する検出回路と、この検出回路が圧縮
コードを検出したとき、該コードに対応付けられ
ている複数のキヤラクタコードを発生するデコー
ダと、上記第1のレジスタから順次読み出された
キヤラクタ情報を順次記憶する第2のレジスタと
、上記検出回路が圧縮コードを検出したとき、上
記第1のレジスタから第2のレジスタへのキヤラ
クタコードの転送を禁止し、上記デコーダで発生
したキヤラクタコードを上記第2のレジスタへ書
き込むゲート回路とを具備したことを特徴とする
キヤラクタコード変換装置。 図面の簡単な説明を次のように補正する。 明細書第18頁第2行目に、「、第6図は…構
成図」とあるを削除する。
[Claims for Utility Model Registration] A memory for associating one character with one code, associating a plurality of characters with one code having the same number of bits as this code, and storing character information represented by each of these codes. , an addressing circuit that specifies the address of this memory, a first register that stores character information read from the address of the memory specified by this addressing circuit, and character information stored in this first register. 1
A detection circuit reads character codes one by one and detects whether the code is a compressed code associated with multiple characters, and when this detection circuit detects a compressed code, reads out multiple characters associated with the code. a decoder that generates a compressed code; a second register that sequentially stores character information sequentially read out from the first register; A character code conversion device comprising: a gate circuit that prohibits transfer of a character code to the second register, and writes a character code generated by the decoder to the second register. The brief description of the drawing has been amended as follows. In the second line of page 18 of the specification, the statement ``Figure 6 is a configuration diagram'' is deleted.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 1つのコードに1キヤラクタを対応付けると共
に、このコードと同一ビツト数からなる2つのコ
ードに複数キヤラクタを対応付け、これら各コー
ドにより表わされるキヤラクタ情報を記憶するメ
モリと、このメモリのアドレスを指定する手段と
、この手段により指定された上記メモリのアドレ
スに記憶されているキヤラクタ情報を読出す手段
とを具備してなるキヤラクタ情報記憶装置。
A means for associating one character with one code and associating a plurality of characters with two codes having the same number of bits as this code, storing a memory for storing character information represented by each of these codes, and specifying an address of this memory. and means for reading the character information stored at the address of the memory specified by the means.
JP1985155491U 1985-10-11 1985-10-11 Expired JPS625728Y2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1985155491U JPS625728Y2 (en) 1985-10-11 1985-10-11

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1985155491U JPS625728Y2 (en) 1985-10-11 1985-10-11

Publications (2)

Publication Number Publication Date
JPS6165558U true JPS6165558U (en) 1986-05-06
JPS625728Y2 JPS625728Y2 (en) 1987-02-09

Family

ID=30713504

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1985155491U Expired JPS625728Y2 (en) 1985-10-11 1985-10-11

Country Status (1)

Country Link
JP (1) JPS625728Y2 (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS56149667A (en) * 1980-04-21 1981-11-19 Sharp Corp Electronic interpreter

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS56149667A (en) * 1980-04-21 1981-11-19 Sharp Corp Electronic interpreter

Also Published As

Publication number Publication date
JPS625728Y2 (en) 1987-02-09

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