JPS60135907U - numerical control device - Google Patents

numerical control device

Info

Publication number
JPS60135907U
JPS60135907U JP2276284U JP2276284U JPS60135907U JP S60135907 U JPS60135907 U JP S60135907U JP 2276284 U JP2276284 U JP 2276284U JP 2276284 U JP2276284 U JP 2276284U JP S60135907 U JPS60135907 U JP S60135907U
Authority
JP
Japan
Prior art keywords
control device
numerical control
data
reading
storage means
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2276284U
Other languages
Japanese (ja)
Inventor
潔 岡田
Original Assignee
三菱電機株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 三菱電機株式会社 filed Critical 三菱電機株式会社
Priority to JP2276284U priority Critical patent/JPS60135907U/en
Publication of JPS60135907U publication Critical patent/JPS60135907U/en
Pending legal-status Critical Current

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  • Numerical Control (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Abstract] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of drawings]

第1図はこの考案の一実施例の構成を示すブロック図、
第2図は第1図中の記憶回路の詳細を示す回路図である
。 図中、1はキーボード、1aは文字キー、1bは数字キ
ー、1cはCRキー、1dはLFキー、1−eは記憶キ
ー、1fは読出しキ、−12はキーボードエンコーダ、
3はコード判別回路、4は記憶回路、40は入力バッフ
ァメモリ、41は保存メモリ、42.43はアンドゲー
ト、44はオアゲートである6なお、図中の同一番号は
同一または相当部分を示す。
FIG. 1 is a block diagram showing the configuration of an embodiment of this invention.
FIG. 2 is a circuit diagram showing details of the memory circuit in FIG. 1. In the figure, 1 is a keyboard, 1a is a character key, 1b is a number key, 1c is a CR key, 1d is a LF key, 1-e is a memory key, 1f is a read key, -12 is a keyboard encoder,
3 is a code discrimination circuit, 4 is a storage circuit, 40 is an input buffer memory, 41 is a storage memory, 42, 43 is an AND gate, and 44 is an OR gate.6 Note that the same numbers in the drawings indicate the same or corresponding parts.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] データ入力手段から入力されたデータに基づいて制御を
行う数値制御装置においぞ、入力された所要のデータを
記憶する記憶手段と、この記憶手段仲記憶されたデータ
を読出し入力させる読出手段とを具備せしめたことを特
徴とする数値制御装置。
A numerical control device that performs control based on data input from a data input means is equipped with a storage means for storing required input data, and a reading means for reading and inputting the data stored in the storage means. A numerical control device characterized by the following features:
JP2276284U 1984-02-20 1984-02-20 numerical control device Pending JPS60135907U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2276284U JPS60135907U (en) 1984-02-20 1984-02-20 numerical control device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2276284U JPS60135907U (en) 1984-02-20 1984-02-20 numerical control device

Publications (1)

Publication Number Publication Date
JPS60135907U true JPS60135907U (en) 1985-09-10

Family

ID=30515361

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2276284U Pending JPS60135907U (en) 1984-02-20 1984-02-20 numerical control device

Country Status (1)

Country Link
JP (1) JPS60135907U (en)

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