JPS6165529A - Digital-analog converting circuit - Google Patents

Abstract

PURPOSE:To realize D/A conversion with simple circuit and high resolution and high accuracy without being limited by the relative specific accuracy of an element by using a reference clock, a 1/2<n> frequency divider, a means for superimposing an output of the 1/2<n> frequency divider according on the digital input and a means for interrupting the constant current by the signal. CONSTITUTION:A reference clock (a) from a reference clock generator 12, a 1/2 clock (b) having 1/2 of the frequency of the reference clock (a), a 1/4 clock (c) being 1/4 of the (a) and a 1/8 clock (d) being 1/8 of the (a) are generated. An output current (n) of an OR gate 8 is given to a current switch 13 to close the switch 13 when the signal (n) is at high level. A constant current source 14 is connected to one input of the switch 13 and an integration device 16 comprising an operational amplifier 14 and a capacitor 15 is connected to the other input. A switch 17 is connected between the input and output of the integration device and a sample-and-hold circuit 18 is connected to the output of the integration device. Signals (p) and (q) of a control circuit 19 control the switch 17 and the circuit 18.

Description

Detailed Description of the Invention (Technical Field) The present invention relates to a digital-to-analog conversion circuit (hereinafter referred to as D/Ai
(color circuit).

(Prior Art) Conventionally, a D/A conversion circuit using an a-2R ladder resistor is well known. This D/A conversion circuit can be realized with a relatively simple circuit configuration, but in order to achieve high resolution and high precision, strict relative ratio phase changes are required for the resistors and transistors used. Because of this restriction, R,−2B
The disadvantage is that it is very difficult to perform high-resolution, high-precision conversion with a D/A conversion circuit using a ladder resistor.

In addition, as other conventional D/A conversion circuits, there are
As shown in Publication No. 99821, there was a circuit that set a digital signal at a constant rate and charged an integrating circuit with a constant current for the time counted by a preset counter to obtain a voltage proportional to the digital signal. This circuit is capable of high-resolution and high-precision D/A conversion, but
The drawback is that the circuit becomes complicated because it uses a preset counter.

(Object of the Invention) An object of the present invention is to provide a high-resolution, high-precision D/A conversion circuit that is not limited by the relative accuracy of internal elements and can be configured with a simple circuit.

(Structure of the Invention) The digital-to-analog conversion circuit of the present invention includes a reference clock generator that generates a reference clock, and second to n-th 1/2 frequency dividers connected in series to the reference clock generator in multiple stages. , a first AND gate inputting complementary signals of the reference clock and signals from each of the second to nth 1/2 frequency dividers and the least significant bit of the digital input; The signal from the 1/2 frequency divider of i and the n+1th
~2nd to (n-1)th AND gates that input the complementary signal of the signal from the nth 1/2 frequency divider and the first bit from the least significant of the digital input; A constant current is generated by the signals from the OR gates: the n-th AND gate that inputs the signal from the frequency converter and the most significant bit of the digital input, and the OR gate that inputs the signals from the first to n-th AND gates. The current is configured to include a switch that connects the constant current to and from the constant current, and an integrating means that integrates the constant current that is interrupted.

(Operation of the Invention) The D/A conversion circuit of the present invention controls a current switch using a 1/2 frequency divider, a reference clock, and a logic section to charge a constant current into an integrating circuit for a time proportional to a digital signal. , D/A conversion is performed without using any elements that require analog precision except for the integrating circuit. The present invention will be described below based on embodiments with reference to the drawings.

FIG. 1 is a circuit diagram of a first embodiment of the present invention. The reference clock generator 12 is T-F/F (T-F/F).
11 and connect the output of T-F/Fil to T-F/FIO
In addition, the output of T-F/F10 is connected to the input of T''-F'/F9, and the reference clock a from the reference clock generator 12 is input.

1/2 clock b whose frequency is 1/2 of the reference clock a,
1/4 clock c, 1/8 l/8 clock d
Create four clocks. - Connect inverters 1 to 3 with 1/8.1/4.1/2 clock d-bK, respectively, and create complementary clock (ge) with 1/8 to 0 and gate 4.
Clock d and MSB (most significant digit) input h of the digital input signal, 1/4 clock c to AND gate 5, ! :
i/g complementary clock g and digital input signal 2
+1 d (2nd input from the top j, 1/2 clock b and 1/8 complementary clock g to AND gate 6, 1
/4-phase bucket clock f and the 3rd (3rd) of the digital input signal
th digit) Input is an, reference clock a is in the thorn door.
and 1/8 phase 1fi clock 12.1/4 complementary clock f
, 1/2 complementary clock e, LSB of digital input signal
(4-lower digit) Connect the input m, and connect the outputs of AND gates 4 to 7 to the OR gate 8. Connect the output signal n of the OR gate 8 to the current switch 13, and when the signal n is at a high level, the switch 13 Close. A switch 17 is connected between the input and output of a zero integrator, in which a constant current source 14 is connected to one end of the switch 13, and an integrator 16 composed of an operational amplifier 14 and a capacitor 15 is connected to the other end. The switch 17 and the sample-and-hold circuit 18 are controlled by the signal p and signal q of the zero control circuit 19 which connects the sample-and-hold circuit 18 to the output of the integrator. In this embodiment, a 4-bit D/A conversion circuit is constructed.

FIG. 2 shows a timing diagram when a 101O digital signal is input to this 4-bit D/A conversion circuit. Before the start of conversion, the switch 13 is opened by the signal n.
The switch 17 is closed by the signal p. The base lock generator 12 is activated by the conversion start signal from the control circuit 19.
starts oscillating, and at the same time the switch 17 is opened by the signal p. Digital input 101O and the clock are combined to produce signal n shown in FIG. The switch 13 is closed only when the signal n is at a high level, and the constant current from the constant current source 14 is divided by the divider 16. In other words, since the input j1m is O, the output of the AND gate 5.7 is always The output of AND gate 4 is 1/
8 Clock d is high level only when it is high level, and the output of AND gate 6 is 1/2 clock b and 1/4.1/
8 complementary clock'l? The signal n is at a high level only when both are at a high level, and the signal n is at a high level only during the second cycle and the fifth to eighth cycles of the reference clock a from the conversion start signal of the control circuit 19.

Published immediately after 8 cycles of reference clock a are output.
The circuit 19 outputs the signal q, and the output of the integrator 16 is held in the sample-and-hold 1 circuit 18, after which the signal p (switch 17 is closed and returns to the initial state. Thereafter, the next conversion starts in the same way. be done.

The accuracy of this D/A conversion circuit is determined by the accuracy of the reference clock a. Therefore, if a crystal oscillator or other device with high precision and stability is used for the reference C2 generator 12, a D/A oscillator circuit with high phase change and high resolution can be easily constructed.

FIG. 3 is a circuit diagram of a second embodiment of the present invention, in which an 'l'-F/F 20 is added to the first embodiment. 1st
In this embodiment, when the reference clock's D and -T ratios exceed 50, the positive value becomes the difference in the conversion result. So standard black.

The T-F/F 20 is connected to the generator 12 and the 1/2 clock a' is activated.
1/4 clock b' and 1/8 clock c/ for F/Fil~9 and inverters 3~l.

1/16 C1 y R d' and 1/4 complementary clock e/.

A 1/8 complementary clock f' and a 1/16 complementary clock g' are generated and inputted to AND gates 7-4.

In this case, 16 clocks are required to perform the - conversion, so the conversion time is twice that of the first embodiment. However, even if the duty ratio of the reference clock a deviates from 5 Oes, each of l/2.1/4, l/s, and 1/16 ratios o and a' to d' have a duty ratio of 50. It does not affect the conversion accuracy. Therefore, the second embodiment is suitable for constructing a high-resolution and high-precision conversion circuit.

(Summary of the Invention) As described above, the D/A conversion circuit of the present invention has a means for superimposing the outputs of the reference clock, the 1/21 frequency divider, and the 1/2" frequency divider according to the state of the digital input. By configuring a D/A conversion circuit equipped with a constant current and a means for intermittent constant current based on the signal, high resolution and high precision can be achieved with a simple circuit without being limited by the relative ratio accuracy of the elements. This has the effect of enabling D/A conversion.

[Brief explanation of drawings]

Claims (1)

[Claims] a reference clock generator that generates a reference clock, and second to nth first to n-th clocks connected in series to this reference clock generator
/2 frequency divider, the reference clock and the second to n-th frequency dividers;
a first AND gate inputting the complementary signal of the signal from each of the 1/2 frequency dividers and the least significant bit of the digital input; 2nd to (n-1)th AND gates inputting complementary signals of the signals from the i+1st to nth 1/2 frequency dividers and the i-th bit from the least significant of the digital input; 2
An n-th AND gate that inputs the signal from the frequency divider and the most significant bit of the digital input, an OR gate that inputs the signals from the first to n-th AND gates, and a constant current due to the signal from this OR gate. and a switch for intermittent
and integrating means for integrating this intermittent constant current.