JP3311208B2 - Voltage / frequency converter - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a voltage / frequency converter for converting a frequency corresponding to an input voltage.

[0002]

2. Description of the Related Art FIG. 8 shows a conventional example of a voltage / frequency converter for converting a frequency corresponding to an input voltage used in an electronic watt-hour meter. FIG. 9 shows waveforms at various points in FIG.

In FIG. 1, a selector 8 for obtaining a composite current I3 of an input current E1 and a reference current I2 with respect to an input voltage E.
And the integrator 1 integrates the combined current I3 of the selector 8 to obtain an integrated voltage A. Next, in the comparator 2,
The integrated voltage A is compared with the reference voltage AG. When the integrated voltage A is higher than the reference voltage AG, a low level is output, and when the integrated voltage A is low, a high level is output. Then, the output signal J of the comparator 2 and the signal K do not match and the pulse signal C
A JK flip-flop 3 that outputs a selection signal K when LK changes from a low level to a high level. The selection signal K controls the switch SW1 for flowing the reference current I2 of the selector 8. Reference numeral 5 in the figure is a pulse signal generator. Here, when the output signal K of the JK flip-flop 3 is at a high level, the switch SW1 is closed and the current I3 flowing into the capacitor C1 of the integrator 1 is

[0004]

## EQU1 ## I3 = I1-I2 (<0). This is because I1 <I2. At this time, the integrator 1 starts integration in the plus direction. When the integrated voltage A of the integrator 1 becomes higher than the reference potential AG, the output signal J of the comparator 2 goes low. Comparator 2
Becomes low, the input of the JK flip-flop 3 becomes J: low level K: high level (= Q output), and the output signal K of the JK flip-flop 3 becomes low at the rise of the pulse signal CLK. Become. When the output signal K of the JK flip-flop 3 is at a low level, the switch SW1 is opened, and the current I3 flowing into the capacitor C1 of the integrator 1 is

[0005]

I3 = I1 (> 0), and the integrator 1 starts integration in the minus direction. When the integrated voltage A of the integrator 1 becomes lower than the reference potential AG, the output signal J of the comparator 2 goes high. The input of the JK flip-flop 3 becomes J: high level K: low level (= Q output), and the output signal K of the JK flip-flop 3 becomes high level at the rise of the pulse signal CLK. When the output signal K of the JK flip-flop 3 is at a high level, the itch SW1 closes and returns to the initial state. here,
When the switch SW1 is closed, the electric charge Q1 stored in the capacitor C1 of the integrator 1 becomes

[0006]

## EQU3 ## Q1 = (I2-I1) .times.T1. On the other hand, when the switch SW1 is open, the charge amount Q2 discharged from the capacitor C1 of the integrator 1 is

[0007]

## EQU4 ## Q2 = I1 × T2. Here, since the charge amounts Q1 and Q2 are equal,

[0008]

(I2−I1) × T1 = I1 × T2 I1 × (T1 + T2) = I2 × T1 Becomes Here, T1 is the frequency f _CLK of the pulse signal LK.
From T1 = 1 / f _CLK is constant. In addition, the-of the operational amplifier OP1 of the integrator 1
The input potential is the reference potential AG when the input offset voltage of the operational amplifier OP1 is zero, so that the current I2 is obtained from the minus reference potential VSS and the resistor R2.

[0009]

## EQU6 ## It is constant that I2 = VSS / R2. I1 is obtained from the input voltage E of the voltage / frequency converter and the resistor R1.

[0010]

## EQU7 ## I1 = E / R1. Therefore, the output frequency f of the voltage / frequency converter
Is

[0011]

(Equation 8) And the frequency is directly proportional to the input voltage E.

[0012]

The above-described conventional voltage /
In the description of the frequency converter, the input offset voltage of the operational amplifier OP1 is set to zero. However, the operational amplifier OP1 usually has an input offset voltage v. In this case, the negative input potential of the operational amplifier OP1 is v. Therefore, the output frequency f _E of the voltage / frequency converter is

[0013]

(Equation 9) And the linearity of the voltage / frequency converter deteriorates. Here, the input voltage E and the linearity error ERR when the operational amplifier OP1 has the input offset voltage, that is, (f _E
FIG. 10 shows the relationship of −f) × 100 / f.

When the polarity of the input voltage E is negative, the switch SW1 is opened when the output signal K of the JK flip-flop 3 is at a low level, and the current I3 flowing into the capacitor C1 of the integrator 1 is I3 = I1 (<0 ... since the polarity of the input voltage E is negative), and the integrator 1 starts integration in the positive direction. Therefore, integration in the reverse direction is not performed, and a frequency directly proportional to the input voltage E cannot be obtained.

As described above, when a voltage / frequency converter is used in an electronic watt-hour meter and the voltage obtained as a result of the power calculation is used as the input voltage E as it is, the polarity of the input voltage E is within one cycle of the power to be measured. Since the polarity of the input voltage E may be negative due to inversion, the voltage that is the power calculation result cannot be used as the input voltage E in the conventional example.

An object of the present invention is to provide a highly accurate voltage / frequency converter having a small linearity error. Another object of the present invention is to provide a voltage / frequency converter capable of eliminating the influence of the polarity of the input voltage.

[0017]

SUMMARY OF THE INVENTION In order to achieve the above object, the present invention provides a switching signal generating means for generating a switching signal at a predetermined period, and a reverse polarity input voltage signal having a polarity opposite to the input voltage signal. a polarity inverting means for, for the integral signal from the integration means becomes lower than the negative comparison voltage
A selection signal generating means for outputting a first selection signal for a predetermined period, the integration signal and outputs a second selection signal for a predetermined time period based on the became higher than the positive comparison voltage based, the switching signal generating means the from the switching signal and the selection signal generating means from 1, the input voltage signal based on the second selection signal, the reverse polarity input voltage signal, the
A composite signal of the input voltage signal and the plus reference voltage signal,
Combined signal of reverse polarity input voltage signal and plus reference voltage signal
Signal, synthesis of the input voltage signal and the negative reference voltage signal
Signal, the reverse polarity input voltage signal and the negative reference voltage signal
And selecting means for outputting any one of the synthesized signals to the integrating means, thereby reducing the influence of the offset voltage of the integrating means.

Further, based on the polarity of the input voltage signal and the first and second selection signals from the selection signal generating means, a frequency signal proportional to the input voltage signal or a frequency signal proportional to the absolute value of the input voltage signal is generated. Since the frequency signal switching means for obtaining either is provided, it is possible to eliminate the influence of the polarity of the input voltage signal.

[0019]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a circuit diagram of a voltage / frequency converter according to a first embodiment of the present invention. In FIG.
Reference numeral 1 denotes a voltage input terminal for inputting a voltage to be converted into a frequency. AG is a reference potential, VDD is a plus reference potential, VS
S is a negative reference potential. 5 is a pulse signal generating means for generating a pulse signal CLK at a predetermined cycle,
It is composed of a crystal oscillator and the like. 6 is a switching signal generating means 6 for generating a switching signal CNT at a predetermined cycle.
And comprises a crystal oscillator, a frequency divider, and the like. Reference numeral 7 denotes an inverting amplifier that generates an inverted polarity input voltage EN obtained by inverting the polarity of the input voltage E input from the voltage input terminal T1, and includes an operational amplifier OP2 and resistors R3 and R4. 4 is the input voltage E and the reverse polarity input voltage EN based on the switching signal CNT and the frequency signal F.
Switch which complementarily switches the voltage applied from the analog switch SW3, SW4, inverter IV
1, a D flip-flop D1. Reference numeral 8 denotes a selector for adding a combined current I3 of an input current I1 based on an input voltage and a reference current I2 whose energization is controlled to be on / off, and includes resistors R1 and R2 and switches SW1 and SW2. An integrator 1 integrates the current supplied from the selector 8 and outputs an integrated voltage A, and is composed of an operational amplifier OP1 and a capacitor C1. Reference numeral 9 denotes a selection signal generation circuit that outputs a selection signal FL based on a change point when the integrated voltage A becomes lower than the minus comparison voltage REFL, and outputs a selection signal FH based on a change point when the integration voltage A becomes higher than the plus comparison voltage REFH. Means, comparators CM1, CM2, resistors R5, R6, R7,
R8, JK flip-flops JK1, JK2, and OR gate OR1.

Next, the operation of the apparatus configured as described above will be described with reference to FIG. Here, a section in which the control signal PON is at a high level is called a plus integration cycle, and a section in which the control signal MON is at a high level is called a minus integration cycle.

In the voltage / frequency converter of this embodiment,
When the input voltage E is applied to the selection means 8 by the switching means 4, the charge accumulated by integrating the input current I1 based on the input voltage E is divided by the input voltage E and the minus reference voltage VS.
Discharge is performed with a combined current I3 based on S or the plus reference voltage VDD (plus integration cycle). When the switching means 4 applies the reverse-polarity input voltage EN to the selection means 8, the charge obtained by integrating the input voltage I1 based on the input voltage EN is divided by the input voltage EN and the plus reference voltage VDD.
Alternatively, discharging is performed with a combined current I3 based on the minus reference voltage VSS (minus integration cycle). The plus integration cycle and the minus integration cycle are repeated at predetermined time intervals based on the switching signal CNT. Since the time required for these charging and discharging is directly proportional to the input voltage E and the reverse polarity input voltage EN, respectively, the output cycle of the selection signal FL and the selection signal FH obtained by repeating this operation is directly proportional to the input voltage. Input voltage E and reverse polarity input voltage EN
Can be converted to a frequency corresponding to.

That is, in the plus integration period, since the control signal PON is at the high level, SW3 is closed and the resistor R
1, the input voltage E is input. When the output signal FL of the JK flip-flop JK1 is at a low level, the switch S
W1 opens, and the current I3 flowing into the capacitor C1 of the integrator 1 becomes

[0023]

I3 = I1 (> 0), and the integrator 1 starts integration in the minus direction. When the integrated voltage A of the integrator 1 becomes lower than the minus comparison voltage REFL, the output signal CMPL of the comparator CM1 goes high. The input of the JK flip-flop JK1 becomes J: high level K: low level (= Q output), and the output signal FL of the JK flip-flop JK1 becomes high level at the rise of the pulse signal CLK.
When the output signal FL of the JK flip-flop JK1 is at a high level, the switch SW1 is closed and the resistor R2 is connected to the minus reference potential VSS. The current I3 flowing into the capacitor C1 of the integrator 1 is

[0024]

I3 = I1-I2 (<0) This is because I1 <I2. The integrator 1 starts integration in the plus direction. Integrator 1 integration voltage A
Becomes higher than the negative comparison voltage REFL, the output signal CMPL of the comparator CM1 becomes low level. J
The input of the K flip-flop JK1 becomes J: low level K: high level (= Q output), and the output signal FL of the JK flip-flop JK1 becomes low level at the rise of the pulse signal CLK.
here,

[0025]

I1 = E / R1 I2 = VSS / R2 Therefore, the output frequency fp of the voltage / frequency converter having the plus integration period is

[0026]

(Equation 13) Becomes Next, in the minus integration cycle, the control signal MON
Is at a high level, SW4 is closed, and the reverse polarity input voltage EN is input to the resistor R1. When the output signal FH of the JK flip-flop JK2 is at a low level, the switch SW2 opens, and the current I3 flowing into the capacitor C1 of the integrator 1 becomes

[0027]

I3 = I1 (<0), and the integrator 1 starts integration in the plus direction. When the integrated voltage A of the integrator 1 becomes higher than the plus comparison voltage REFH, the output signal CMPH of the comparator CM2 becomes high level. The input of the JK flip-flop JK2 becomes J: high level K: low level (= Q output), and the output signal FH of the JK flip-flop JK2 goes high at the rise of the pulse signal CLK.
When the output signal FH of the JK flip-flop JK2 is at a high level, the switch SW2 is closed, and the plus reference potential VDD is connected to the resistor R2. The current I3 flowing into the capacitor C1 of the integrator 1 is

[0028]

I3 = I1-I2 (> 0) This is because I1> I2. The integrator 1 starts integration in the negative direction. When the integrated voltage A of the integrator 1 becomes lower than the plus comparison voltage REFH, the output signal CMPH of the comparator CM2 becomes low level. J
The input of the K flip-flop JK2 becomes J: low level K: high level (= Q output), and the output signal FH of the JK flip-flop JK2 becomes low level at the rise of the pulse signal CLK.
here,

[0029]

I1 = EN / R1 = -E / R1 I2 = VDD / R2 = -VSS / R2 Therefore, the output frequency fm of the voltage / frequency conversion device having a negative integration cycle is

[0030]

[Equation 17] Becomes Here, the switching from the positive integration period to the negative integration period is performed at the fall of the frequency signal F after the switching signal CNT changes from the high level to the low level.
This is performed when the control signal PON goes low and the control signal MON goes high. Switching from the minus integration period to the plus integration period is performed by changing the frequency signal F after the switching signal CNT changes from the low level to the high level.
Is performed when the control signal MON goes low and the control signal PON goes high at the falling edge of. By complementarily switching between the plus integration period and the minus integration period described above, the output average frequency f of the voltage / frequency converter becomes

[0031]

(Equation 18) And the frequency is directly proportional to the input voltage E. Here, when the operational amplifier OP1 of the integrator 1 has the input offset voltage v, the negative input potential of the operational amplifier OP1 becomes v. Therefore, the output frequency f _E of the voltage / frequency converter of the present invention is

[0032]

[Equation 19] Becomes As can be seen from this equation, the negative reference potential V
By making SS sufficiently larger than the input offset voltage v of the operational amplifier OP1, the influence of the input offset voltage v on the output frequency of the voltage / frequency converter can be reduced.

As described above, according to the first embodiment, the reverse polarity voltage EN obtained by inverting the polarity of the input voltage E can also be converted to the corresponding frequency. , It is possible to obtain a highly accurate voltage / frequency converter with very little linearity error.

FIG. 3 is a circuit diagram of a voltage / frequency converter according to a second embodiment of the present invention. In the figure, reference numeral 10 denotes a switching signal CNT and selection signals FL and FH.
Frequency signal switching means for determining the polarity of the input signal E based on
It comprises ND gates AN1, AN2, AN3, AN4 and OR gates OR2, OR3. T5 is a frequency f that is directly proportional to the input voltage when the polarity of the input voltage is positive.
Is a terminal for outputting the frequency signal FWD. T6 is a terminal that outputs a frequency signal REV having a frequency f that is directly proportional to the absolute value of the input voltage when the polarity of the input voltage is negative.

In such a configuration, in the frequency signal switching means 10, when the polarity of the input voltage E is positive, the frequency signal FWD having a frequency f directly proportional to the input voltage E
Can be obtained, and when the polarity of the input voltage E is negative, a frequency signal REV having a frequency f directly proportional to the absolute value of the input voltage E can be obtained.

Therefore, the frequency signal FWD and the frequency signal R
By calculating the difference between EVs, the present invention can also be used for an electronic watt-hour meter in which the polarity of the input voltage E may be inverted within one cycle of the measured power.

Here, a detailed description will be given with reference to FIG.
FIG. 4 is a time chart of the waveform of each part when the polarity of the input voltage in FIG. 3 is negative.

In the plus integration period, SW3 is closed because the control signal PON is at the high level, and the input voltage E is input to the resistor R1. When the output signal FL of the JK flip-flop JK1 is at a low level, the switch SW1 opens, and the current I3 flowing into the capacitor C1 of the integrator 1 becomes

[0039]

I3 = I1 (<0... Because the polarity of the input voltage E is negative), and the integrator 1 starts integration in the positive direction. When the integrated voltage A of the integrator 1 becomes higher than the plus comparison voltage REFH, the output signal CMPH of the comparator CM2 becomes high level. The input of the JK flip-flop JK2 becomes J: high level K: low level (= Q output), and the output signal FH of the JK flip-flop JK2 goes high at the rise of the pulse signal CLK.
When the output signal FL of the JK flip-flop JK2 is at a high level, the switch SW2 is closed, and the resistor R2 is connected to the plus reference potential VDD. The current I3 flowing into the capacitor C1 of the integrator 1 is

[0040]

I3 = I1-I2 (> 0) This is because I1> I2. The integrator 1 starts integration in the negative direction. When the integrated voltage A of the integrator 1 becomes lower than the plus comparison voltage REFH, the output signal CMPH of the comparator CM2 becomes low level. J
The input of the K flip-flop JK1 becomes J: low level K: high level (= Q output), and the output signal FH of the JK flip-flop JK2 becomes low level at the rise of the pulse signal CLK.

In the minus integration period, since the control signal MON is at the high level, the switch SW4 is closed, and the reverse polarity input voltage EN is inputted to the resistor R1. When the output signal FL of the JK flip-flop JK1 is at a low level, the switch S
W1 opens, and the current I3 flowing into the capacitor C1 of the integrator 1 becomes

[0042]

I3 = I1 (> 0 because the polarity of the reverse polarity input voltage EN is positive), and the integrator 1 starts integration in the negative direction. When the integrated voltage A of the integrator 1 becomes lower than the minus comparison voltage REFL, the output signal CMPL of the comparator CM1 goes high. The input of the JK flip-flop JK1 becomes J: high level K: low level (= Q output), and the output signal FL of the JK flip-flop JK1 becomes high level at the rise of the pulse signal CLK.
When the output signal FL of the JK flip-flop JK1 is at a high level, the switch SW1 is closed, and the resistor R2 is connected to the minus reference potential VSS. The current I3 flowing into the capacitor C1 of the integrator 1 is

[0043]

I3 = I1-I2 (<0) This is because I1 <I2. The integrator 1 starts integration in the plus direction. Integrator 1 integration voltage A
Becomes higher than the negative comparison voltage REFL, the output signal CMPL of the comparator CM1 becomes low level. J
The input of the K flip-flop JK2 becomes J: low level K: high level (= Q output), and the output signal FH of the JK flip-flop JK2 becomes low level at the rise of the pulse signal CLK.

Accordingly, when the polarity of the input voltage E is negative, the control signal PON based on the switching signal CNT and the selection signal FH become high level in the plus integration cycle, so that the frequency signal REV is output. In the minus integration cycle, the control signal MO based on the switching signal CNT is used.
Since N and the selection signal FL become high level, the frequency signal REV is output. Accordingly, a frequency signal REV having a frequency f directly proportional to the absolute value of the input voltage E having the negative polarity is obtained. FIG. 5 shows the relationship between the input voltage E, the frequency signal FWD, and the frequency signal REV.

As described above, according to the second embodiment, when the polarity of the input voltage E is negative, a frequency signal REV having a frequency f directly proportional to the absolute value of the input voltage E can be obtained. High-precision voltage /
A frequency converter can be obtained. That is, such a voltage / frequency converter can be used for an electronic watt-hour meter whose polarity of the input voltage may be reversed within one cycle of the measured power.

FIG. 6 is a circuit diagram of a voltage / frequency converter according to a third embodiment of the present invention. This is shown in FIG. 1 and FIG.
Instead of the inverting amplifier 7 shown in FIG. 7, a differential difference amplifier 12 for applying an input voltage E1 obtained by multiplying the input voltage E by a predetermined number and a reverse polarity input voltage E1N having a polarity opposite to the input voltage E1 is provided. . By multiplying the input voltage E by a predetermined number using the differential difference amplifier 12, the operational amplifier OP1 of the integrator 1
Is relatively small as compared with the input voltage E1, so that a highly accurate voltage /
A frequency converter can be obtained.

FIG. 7 is a circuit diagram of a voltage / frequency converter according to a fourth embodiment of the present invention. The inverting amplifier 7 shown in FIGS. 1 and 3 is not necessary when the reverse polarity input voltage EN having the polarity of the input voltage E is input, and the reverse polarity input voltage EN is not required.
Terminal T4.

[0048]

As described above, according to the present invention, switching signal generating means for generating a switching signal at a predetermined cycle, and polarity inverting means for generating a reverse polarity input voltage signal having a polarity opposite to that of an input voltage signal are provided. Outputting a first selection signal only for a predetermined period when the integration signal from the integration means becomes lower than the minus comparison voltage, and outputting a second selection signal only for a predetermined period when the integration signal becomes higher than the plus comparison voltage. A selection signal generating means for outputting a selection signal; an input voltage signal based on a switching signal from the switching signal generation means and first and second selection signals from the selection signal generating means;
Alternatively, since there is provided selection means for selectively outputting a synthesized signal of either of these signals and either the plus reference voltage signal or the minus reference voltage signal and supplying the combined signal to the integration means, the linearity error is small and the accuracy is improved. Can be planned.

Further, based on the polarity of the input voltage signal and the first and second selection signals from the selection signal generating means, a frequency signal proportional to the input voltage signal or a frequency signal proportional to the absolute value of the input voltage signal is generated. Since the frequency signal switching means for obtaining either is provided, it is possible to eliminate the influence of the polarity of the input voltage signal.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a first embodiment of a voltage / frequency converter according to the present invention.

FIG. 2 is a diagram for explaining the operation of the voltage / frequency converter in FIG. 1;

FIG. 3 is a circuit diagram showing a second embodiment of the voltage / frequency converter according to the present invention.

FIG. 4 is a diagram for explaining the operation of the voltage / frequency converter of FIG. 3;

FIG. 5 is a diagram for explaining the operation of the frequency signal switch 10 shown in FIG. 3;

FIG. 6 is a circuit diagram showing a third embodiment of the voltage / frequency converter according to the present invention.

FIG. 7 is a circuit diagram showing a fourth embodiment of the voltage / frequency converter according to the present invention.

FIG. 8 is a circuit diagram of a conventional voltage / frequency converter.

FIG. 9 is a diagram for explaining the operation of the voltage / frequency converter in FIG. 8;

FIG. 10 is a diagram showing a relationship between an input voltage of a conventional voltage / frequency converter and a linearity error.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Integrator, 4 ... Switcher, 6 ... Switching signal generator, 8 ... Selector, 9 ... Selection signal generator

──────────────────────────────────────────────────続 き Continued on the front page (58) Fields surveyed (Int. Cl. ⁷ , DB name) G01R 19/25-19/257 G01R 22/00 120 H03K 7/06 H03K 5/00

Claims (5)

(57) [Claims] A switching signal generating means for generating a switching signal at a predetermined cycle; a polarity inverting means for generating an input signal having a polarity opposite to that of the input voltage signal; to become lower than the voltage
A selection signal generating means for outputting a first selection signal for a predetermined period, the integration signal and outputs a second selection signal for a predetermined time period based on the became higher than the positive comparison voltage based, the switching signal generating means the from the switching signal and the selection signal generating means from 1, the input voltage signal based on the second selection signal, the reverse polarity input voltage signal, the
A composite signal of the input voltage signal and the plus reference voltage signal,
Combined signal of reverse polarity input voltage signal and plus reference voltage signal
Signal, synthesis of the input voltage signal and the negative reference voltage signal
Signal, the reverse polarity input voltage signal and the negative reference voltage signal
Selecting means for outputting any one of the synthesized signals of the above and supplying the signal to the integrating means. 2. A frequency signal proportional to the input voltage signal or an absolute value of the input voltage signal based on a polarity of the input voltage signal and first and second selection signals from the selection signal generating means. 2. A voltage / frequency converter according to claim 1, further comprising frequency signal switching means for obtaining one of the frequency signals. 3. A switching signal generating means for generating a switching signal at a predetermined cycle; a differential / differential amplifier for adding an input voltage signal and a reverse polarity input voltage signal; and an integrated signal from the integrating means being smaller than a minus comparison voltage. outputs a first selection signal for a predetermined time period based on the became low, and the selection signal generating means for said integration signal and outputs the second selection signal for a predetermined time period based on the became higher than the positive comparison voltage, first, the input voltage signal based on the second selection signal from the switching signal and the selection signal generating means from said switching signal generating means, said reverse polarity input voltage signal, said input voltage signal
And the plus reference voltage signal, the reverse polarity input voltage
A composite signal of the voltage signal and the plus reference voltage signal,
Composite signal of the voltage signal and the negative reference voltage signal,
Of the composite signal of the negative input voltage signal and the negative input voltage signal
Selecting means for outputting any one and supplying the output to the integrating means. 4. A first input terminal for obtaining an input voltage signal, a second input terminal for obtaining a reverse-polarity input voltage signal having a polarity opposite to that of the input voltage signal, and switching for generating a switching signal at a predetermined cycle. output signal generating means, a first selection signal for a predetermined period on the basis of the integration signal becomes lower than the negative comparison voltage from the integrating means, on the basis of the said integration signal is higher than the positive reference voltage Second only for a predetermined period
A selection signal generating means for outputting a selection signal, first, the input voltage signal based on the second selection signal from the switching signal and the selection signal generating means from said switching signal generating means, said reverse polarity input voltage Signal, the input voltage signal and
Composite signal with plus reference voltage signal, reverse polarity input voltage
A composite signal of the signal and the plus reference voltage signal, the input voltage
Composite signal of signal and negative reference voltage signal, reverse polarity
The composite signal of the input voltage signal and the minus reference voltage signal
Selecting means for outputting one of the shifts and supplying the output to the integrating means. 5. When the input voltage signal is obtained, the selection means outputs a composite signal of the input voltage signal and the minus reference voltage signal or the plus reference voltage signal and supplies the combined signal to the integration means. 5. The method according to claim 1, wherein when the signal is obtained, a combined signal of the reverse polarity input voltage signal and the plus reference voltage signal or the minus reference voltage signal is output and supplied to the integration means. A voltage / frequency converter according to any one of claims 1 to 3.