JPS6164674U - - Google Patents
Info
- Publication number
- JPS6164674U JPS6164674U JP14661084U JP14661084U JPS6164674U JP S6164674 U JPS6164674 U JP S6164674U JP 14661084 U JP14661084 U JP 14661084U JP 14661084 U JP14661084 U JP 14661084U JP S6164674 U JPS6164674 U JP S6164674U
- Authority
- JP
- Japan
- Prior art keywords
- output signal
- circuit
- signal
- pass filter
- level detector
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000001514 detection method Methods 0.000 claims description 4
- 238000010586 diagram Methods 0.000 description 2
Landscapes
- Digital Magnetic Recording (AREA)
- Signal Processing For Digital Recording And Reproducing (AREA)
Description
第１図は本考案の一実施例の構成を示すブロツ
ク図。第２図は従来の積分検出回路の構成を示す
ブロツク図。
１…ハイパスフイルタ、２…ローパスフイルタ
、３…微分等化回路、４…積分回路、５…平均レ
ベル検出器、６…比較器。
FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention. FIG. 2 is a block diagram showing the configuration of a conventional integral detection circuit. 1... High pass filter, 2... Low pass filter, 3... Differential equalization circuit, 4... Integrating circuit, 5... Average level detector, 6... Comparator.
Claims (1)
微分等化する微分等化回路と、微分等化回路の出
力信号を積分する積分回路と、積分回路の出力信
号を入力とするローパスフイルタと、積分回路の
出力信号を入力信号として入力しこの入力信号の
正、負両方をエンベロープ検波した出力信号を加
算して出力する平均レベル検出器と、ローパスフ
イルタの出力信号を比較入力としかつ平均レベル
検出器の出力信号を基準値とする比較器とを備え
、ローパスフイルタの遅延時間で平均レベル検出
器の検出遅れを補償することを特徴とする積分検
出回路。 A differential equalization circuit that differentially equalizes the reproduced signal from the magnetic recording medium on which the signal is recorded, an integrator circuit that integrates the output signal of the differential equalization circuit, a low-pass filter that receives the output signal of the integrator circuit, and an integrator. An average level detector that inputs the output signal of the circuit as an input signal, adds the output signals obtained by envelope detection of both positive and negative input signals, and outputs the sum, and an average level detector that uses the output signal of the low-pass filter as a comparison input. An integral detection circuit comprising: a comparator whose reference value is the output signal of , and which compensates for a detection delay of an average level detector using a delay time of a low-pass filter.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14661084U JPH0424530Y2 (en) | 1984-09-29 | 1984-09-29 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14661084U JPH0424530Y2 (en) | 1984-09-29 | 1984-09-29 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6164674U true JPS6164674U (en) | 1986-05-02 |
| JPH0424530Y2 JPH0424530Y2 (en) | 1992-06-10 |
Family
ID=30704845
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP14661084U Expired JPH0424530Y2 (en) | 1984-09-29 | 1984-09-29 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0424530Y2 (en) |
-
1984
- 1984-09-29 JP JP14661084U patent/JPH0424530Y2/ja not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0424530Y2 (en) | 1992-06-10 |
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