JPS6163997A - Memory device - Google Patents

Abstract

PURPOSE:To read and write data in plural directions by connecting the word and bit lines in common among memory cells arrayed in K and L directions. CONSTITUTION:A memory cell 19 consists of K units (K>=2, integer) of FET 22 and 23, K pieces word lines 24 and 25, L pieces (K>=L>=1, integer) of bit lines 26 and 27, and a 1-bit information holding means 21 containing an input/ output terminal. Then the M-th (K>=M>=1, integer) FET gate is connected to the M-th word line for K units of FET 22 and 23. Then the other end of the M-th FET is connected to an optional one of bit lines 26 and 27. Then plural units of cells 29 are distributed in an array form 28, and both word and bit lines are connected in common among cells 19 distributed in K and L directions. The cells are selected in the direction K; while data are written and read out in the direction L respectively.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a memory device that allows selection from multiple directions.

[Prior art]

Although various types of memory devices have been proposed in the past, a memory device suitable for selection from multiple directions, which is required in fields such as image recognition and character recognition, has not yet been obtained.

First, FIG. 11 shows a memory device constructed from a one-transistor type dynamic memory cell that has been proposed in the past.

As shown in FIG. 11(a), the memory cell 1 includes an information holding means by a capacitor 3 having - input/output terminals 2, a transistor 4 constituted by, for example, an n-channel MI3 type hidden field effect transistor, It has a signal line 5 and a signal line 6. The signal line 5 is a word line for selecting the memory cell 1, and the signal line 6Fi.

It is possible to transfer write data to memory cell 1 or read data from memory cell 1 (bin) l. The capacitor 5 has one end connected to the input/output terminal and the met4 terminal 2, and the other end grounded. The input/output terminal 2 of the capacitor 5 is connected to the focus line 6 via the transistor 4. On the other hand, transistor 4
The gate of the gate H is connected to the word line 5.

To write four pieces of data into the conventional memory cell 1 having such a configuration, the fourth position having the same phase as the data to be written is marked on the bit sand 6, and the word H5 is set to a high potential. Here, the logic value "1" corresponds to the digit f, and the logic value "0' corresponds to a low potential. Since the word line 5 is at a high potential, the transistor 4
turns on and becomes conductive, so bit line 6 411
: The capacitor 3 is charged and discharged so that the IJL voltage of the input/output terminal 2 becomes high, and data is acquired and input to the memory cell 1. Word, to keep all this data! 'j!
By setting the potential to 5k low and turning off the transistor 4, +yr between the input/output terminal 2 and the bit line 6 is made non-conductive, and the capacitor 3 and the focus signal 6 are disconnected.

To read out data tg, after precharging bit abt and setting it to high level 4, the word line 5t is set to high potential, the charge accumulated in capacitor 5 is transferred to bit line 6, and capacitor 5 is set to logic value "1". When " is written, the input/output terminal 2 is at a high potential, so the potential of the bit line 6, which is at a high potential, does not change, so that a logic value of "1" is read out.

On the other hand, when the logic 1 table "0" is written in the capacitor 3, the input/output terminal 2 is in the low position, so the high 'rd,
By lowering the potential of the bit line 6, which is at the current level, a logical value of "0" is read out.

# of memory cell jfi charge! Use R to perform dynamic operations that store information. Therefore, since the electric charge accumulated in the capacitor 3 over the course of one hour constitutes the data, rewriting must be performed at regular intervals. Further, since the amount of charge accumulated in the capacitor 5 decreases quickly when reading data, it is necessary to perform rewriting immediately after reading data.

Fig. 11 (memory cell k 1 of al, mX
n pieces are arranged to form the memory device 7 as shown in FIG. 11(b). 1st (1=1.2...,tn)
Address x1″f is selected corresponding to word line 5 of .

xl, x2. ..., bit 176f indicated by xn: Oll, which is memory cell 1, C112, ...,
Read and write data of C1n respectively.

Next, we will introduce a memory device consisting of a six-transistor type pseudo static memory cell that has been proposed in the past.
Shown in Figure 2.

As shown in FIG. 12 (al), the memory cell 8 includes an information holding means consisting of a pseudo-static twin flop 9 having - input/output terminals 2, and an information storage means such as an n-channel MIS.
A transistor 4 constituted by a pseudo-field effect transistor, a signal line 5, and a signal line 6 are provided.

The signal line 5 is a word line for selecting a memory cell 8, and the signal line 6 is a bit line for transferring old data to the memory cell 8 or data extracted from the memory cell 8.

The pseudo-static type Frisobfronf 9 consists of 5 hard-wired transistors 10-14, e.g.
Meta 10,11゜12ijn channel IJIs type step-up effect transistor, transistor 1s + 14Vip
This is a channel MIS type field effect transistor. Transistors 10 and 11 each have one end connected to transistor 1.
! i, 14, and the other end is commonly grounded. or,
The terminals of the transistors 13 and 14 that are not connected to the transistors 10 and 11 are commonly connected to the power supply terminal 15.

Are the two terminals of transistor 12 input/output terminal 2 and pseudo flip-flop? It is connected to the terminal 16 inside. The signal line 17 is a write control signal line and the transistor 12
The gate of the transistor 4 is connected to the word line 5. The write control signal line 17 is set at a low potential during writing, and set at a high potential at other times.

In order to grow data in the memory cell 8 having such a configuration tW, a potential in phase with the data to be written is applied to the bit line 6, and the total height of the word line 5 is set to the maximum height.

In this manner, the transistor 4 controlled by the word line 5 is turned on and conducts 4 bits, so that the potential of the bin 4t line 6 is transmitted to the input/output terminal 2 of the pseudo-static flip-flop 9. In this case, write control wholesale signal tightening 1
7 low'f! If it is set to J, the trans/stack will be in the off state, and the pseudo-static flimp 70 tubes? i
lt, the input/output terminal 2 and the terminal 16 are separated, forming an open loop. 9 pseudo-static type 7 lips 70 tubes 9 which form an open loop can easily accept the data input from terminal 2.
1st place is written. In this way, data is loaded into the memory cell 8. To hold this data, set the write control signal line 17 to the same potential and put the pseudo-static flip-flop 9 in a closed loop state. To read the data, as in the case of FIG. After t, the word line 5 is set to high potential. In this way, the potential of the terminal 2 of the static clip-flop 9 is transmitted to the focus line 6, and the data is transmitted while detecting the change in the level of the bit line.

Read out.

mXn memory cells are arranged in 8km'f'Tn rows, and the first
The memory device 18i is configured as shown in Figure 2 ft)l. Address X1 is selected corresponding to the first (i=1.2...+m) word line 5, and xl, x2 . ...
, xnTyT<S The data in the memory cells 8, 011, O12, . . . , C1n, are written visually through the focus line 6, respectively.

By the way, in fields such as image recognition and character recognition,
Reading and writing data from a button memory device that stores image and character data to be processed generally requires complicated processing or the addition of extensive hardware.

For example, in character recognition, as shown in Figure 15 (aJ), one character data is It is necessary to scan.

FIG. 13(b) shows that in the nine memory devices shown in FIG. 11 or 12, m=7. The case where four characters "F" are written into the button memory device with n=5 is shown. In this case, a 7 word by 5 bit single dimensional address memory device is used. Figure 13(t) Address Xl5X7 in l
, bit lines x1''-x5 are used with the same intent as in FIGS. 11 and 4312.

When scanning data in the X-axis direction Since the selection direction coincides with the word line direction of the memory device, one word of data in the X-axis direction can be read by selecting an address once.

For example, to read 5 bits of data on rK3 in ftJ in Figure 12, read bit line x1 at address X7, bit line x2 at address X6, and bit line g x at address X5.
5. At the address X4, bit 1jx4 and at address X5, the data of the bin) d x 5 are sequentially read out.

Therefore, in this case, one scan in the diagonal upper right direction requires five selections equal to the number of bits.

For example, in Figure 413 (5-bit data t on the 7? line of bl)
In order to read out data from the bit line x5 at address X7, the focus line x4 at address X6, the bit Gx5 at address X5, the bit line x2 at address line X4, and the focus line x1 at address X3, each data is sequentially read out. Therefore, in this case, one scan in the diagonal upper left direction requires five selections equal to the number of bits.

When scanning data in the Y-axis direction: Read out sequentially up to address X1Sx7 for a specific bit line to be scanned. Therefore, seven selections are required to scan once in the Y direction.

From the above, in general, in a single-dimensional address memory device with m rows and n columns, one scan in a direction different from the word line requires m selections at worst.

FIG. 14 shows an example in which a dedicated button memory device t is provided for each scanning direction in order to reduce the increase in scanning time seen in the example of FIG. 15. Figure 14 tarK shows 7 rows 5
The column memory device is a memory device for the X-axis direction. 14
The memory device arranged in 11 rows and 5 columns shown in FIG. 14 (bl) is a memory device for use in the diagonally upper right direction.

The memory device fi shown in FIG. 14 IC) with 11 rows and 5 columns is a memory device for use in the diagonally upper left direction. The memory devices in the 5th row and 7th column shown in Figure 414 (dJ) are the memory devices in the same month on the Y axis.

Here, data scanning in each direction can be performed by τf6 extraction of address selection to the general memory device, but in order to do so, character data must be arranged in advance according to the scanning direction as shown in FIG. 4 (additional operations and require more than 4 times as many memory devices. Note that the X marks in Figure 14 indicate unused memory devices). A memory cell is shown.

As mentioned above, using the conventional sheep-dimensional address memory device Z2, memo! If you try to scan data in a direction different from the direction of the word line specific to JS.

The number of selections to the memory device is equal to the number of bits to be scanned, and the access time to the memory device becomes enormous. In order to do this, the data should be stored in advance according to the scanning direction (memory device is required).
This not only increases the amount of hardware, but also requires rearranging the data in the scanning direction corresponding to each memory device in advance so that it can be read out with a single selection to the memory device. f) It has the disadvantage that it requires complicated operations to be performed.

[Purpose of the invention]

An object of the present invention is to provide a memory device that can read data from multiple directions.

[Structure and operation of the invention]

The present invention includes a memory cell including K transistors (K≧2, an integer), K word lines, L focus lines (K≧L≧1, an integer), and one input/output terminal. For each Ki transistor, the gate of the Mth transistor (K≧M≧1, integer) is connected to the Mth word line, and the other end of the Mth transistor is connected to the gate of the Mth transistor (K≧M≧1, integer). is connected to any one of the L bit lines.A number of these memory cells are arranged in an array, and are arranged in the seven direction and L direction of the word line and focus line, respectively. A group of memory cells are commonly connected, and the direction can be selected, and data can be read and written from the L direction.

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, embodiments of the present invention will be described in detail with reference to detailed drawings.

FIG. 1 shows a first embodiment of the invention. Figure 1 (2L)
2 shows a circuit diagram of the memory cell of the first embodiment.

Memory cell 19ij, information holding means by a capacitor 21 having - input/output terminals 20, and, for example, an n-channel M
It has transistors 22, 23 formed of IS type field effect transistors, two word lines 24, 25, and two bit lines 26, 27. Two word lines 24.2
5 is a first word line and a second word line that select the memory cell 19, respectively, and there are two pins) 4426.27.
are a first bit line and a second bit line that transfer write data to the memory cell 19 or read data from the memory cell 19, respectively. One end of the capacitor 21 is connected to the input/output terminal 20, and the other end is grounded. The input/output terminal 20 of the capacitor 21 is connected to the first bit l1i126 via the transistor 22, and
It is connected to the second bit line 27 via. Further, the gates of the transistors 22 and 23 are connected to a first word line 24 and a second word line 25, respectively.

To write data to the memory cell 19 having such a configuration, a potential in phase with the data to be written is applied to the first bit line 26, the first word line 24 is set to a high level, and the second word line 24 is set to a high level. Bring line 25 to a low potential. In this way, the transistor 22 controlled by the first word line 24 is turned on and conducts, so that the potential of the first bit line 26 and the potential of the input/output terminal 20 are at the same level. The capacitor 21 is charged and discharged. In this way, data is loaded into the memory cell 19. To hold this data, both the word machines 24 and 25 are set to a low potential, and the transistors 22 and 25 are each turned off.
The input/output terminal 20 and the other bit lines 26, 27 are made non-conductive, and the capacitor 21 and the bit lines 26, 27 are disconnected.
Separate from.

In the memory cell 19, the combination of the first word line and the first bit line and the combination of the second word line and the second bit line have a symmetrical configuration, so that the above explanation is possible. Similarly, the second word line 25 and the second bit line 2
7, data can be written in exactly the same way.

111:4 (Similar to the 1-transistor type dynamic memory cell shown in 1), after precharging the 1st pin HF926=1 to a high potential, ?P'p 24 *The electric potential stored in the capacitor 21 is transferred to the first focus line 26 by setting it to a high potential, and by detecting a change in this potential, data is read out. Similarly, 1.!PJ
Data can also be read by setting the word gland 25 to the full height. Here, the read operation by the combination of the first word line 24 and the first bit line 26 and the read operation by the combination of the 2g2 word line 25 and the second bit line 27 are completely independent. Row 5 can be done.

Further, while a write operation is performed by the combination of the first word line 24 and the first bit line 26, a read operation is performed by the combination of the second word line 25 and the second bit line 27. I can do it.

Similarly, while performing a 1 lead-in operation using the combination 0 of the 5g2 word line 25 and the second bit line 27, the first
It is also possible to perform a read operation using a combination of the first word line 24 and the first bit line 26.

With the above configuration, it is possible to configure a two-dimensional dynamic memory cell that can equally read data from two directions. Note that the /Mori cell 19 performs a dynamic operation of storing information by utilizing the accumulation of charge. Therefore, as with a normal dynamic memory cell, the charge in the capacitor 21 is discharged over time, so rewriting must be performed at regular intervals. Furthermore, since the amount of electric charge accumulated in the capacitor 21 decreases as data is read, rewriting must be performed immediately after data is read.

FIG. 1 (bl is the memory cell 19 shown in FIG. 1(a)
The first embodiment is a conceptual diagram of a memory device [28] having m×n arrays arranged in m rows and n columns. For the address circuit, block movement circuit, etc. required to configure the memory device 28, circuits similar to those used in conventional dynamic memory devices can be used. All are omitted.

The signal line 24 becomes a word line when the X@ direction is selected, and corresponds to the address X1. X2. ..., Xm is selected, and the signal line 25 becomes the word line when selected in the Y-axis direction, and the address y1. Y2. ..., select Yn and connect the signal line 26
represents the focus line when the x-m direction 91 is selected, and the signal line 27 represents the bit line when the Y-axis direction is selected.

When all addresses Xi (i=1.2, . . . +") are selected and extracted from the memory cells 19 arranged as shown in FIG. 1 (bl), the memory cells Gi1, O12, . . .

Gin data is obtained, C1j, C2j, ・=
, Cmj (j=j, 2..., n), select address Yj. In this way, data can be transferred from 20,000 times to 1+'F, which was impossible with the conventional single-dimensional address memory device Lr.
*It is possible to realize a two-dimensional dynamic memory device.

Figure 2 shows an example of Komei Moto's ↓32.

Figure 4g2 (Al shows the circuit diagram of the memory cell. The memory cell 29 includes information holding means by a pseudo-static type 7-lip 70-tube 30 having 20 input/output terminals, and an n-channel MIS type field effect transistor, for example. So 1:i
It has four transistors 22.25, two word lines 24.25, and two bit lines 26.27.

The two word lines 24° and 25 each correspond to memory cell 2? The word line A1 is the second word line, and the two bit lines 26 and 27 are the first focus line, which transfers write data to the memory cell 29 or read data from the memory cell 29, respectively. It comes from the second bit line. For question 1, the flip-flop 50 is a 51-wire transistor 31.
35, for example, transistors 51, 52,
551dn channel MIS type field effect transistor, transistors 54 and 55 are p channel MIS type field effect transistors. Transistors 51, 52 (fJ,,
One end thereof is connected to transistors 54 and 55, respectively, and the other end is commonly connected. Moreover, the transistors 54, 5
The terminals on the side not connected to the transistors 51 and 52 of No. 5 are commonly connected to the 11t source terminal 56. transistor 3
The 2 terminals of 3 & 1 and so on are set as 1 to the input/output terminal 2o and the terminal 37 in the pseudo flip-flop processor 0.

The line 19 line 38 is connected to the gate of the transistor 53 by the line 19. Assume that the input/output terminal 2 of the pseudo flip-flop is
0i,) is connected to the first bit line 26 via a transistor 22, and to the second bit line 27 via a transistor 23, while the gates of the transistors 22, 25 are connected to the first bit line 26, respectively. Word line 24, second word line 25
connected to.

When data is to be sown into the memory cell 29 having such a configuration, a potential in phase with the data to be written is applied to the 41 bit lines 26, and the first word line 24i is set to the high 1st position.
The second word line 25 and write control signal ~58 are set to low potential. In this way, mlJ is applied to the first word line 24.
The transistor 22 connected to ff1ll is turned on and conducts four signals, so that the potential of the first bit line 26 is transmitted to the input/output terminal 20 of the static flip-flop 50.

At this time, since the input control signal line 38 is at a low potential, the transistor 55 is in an off state, and the static type flip-flop 30 is connected to the input/output terminal 20 and the terminal 37.
are separated, forming an open loop.

The first position of the data input from the terminal 20 is easily written into the pseudo-static clip-flop 30Vi which is in an open loop. In this way, data is written into the memory cell 29. To hold this data, the write-only signal line 58i is set to a high potential and the pseudo-static flip-flop 30i is placed in a closed loop state. memory cell 29
Now, the combination of the first word line 24 and the first bit line 26, and the combination of the second word line 25 and the second bit line 27
Since the configuration is symmetrical to the combination of the second word line 25 and the second bit line 27, data can be written in exactly the same way as described above.

To read data ta, as in the first embodiment, pre-charge the bit line 26f of ho1 and set it to a high potential after fc.
The word lines for the first grade are set to 24 digits and 16'.

In this way, the potential of y;M+20 of the pseudo-static clip-flop 50 is transmitted to the first bit line 26, and data is read by detecting a change in the potential of this bit H. Similarly, the second focus line 27
Data can also be read by setting the word line 25 of the wire 2 to the high voltage level after re-yarning () to set it to a crystal potential. Here, the mU extraction operation by the combination of the first word line 24 and the first bit line 26,
The read operation can be performed completely independently of the read operation performed by the combination of the second word line 25 and the second bit line 27. In addition, the second word fl is activated by the combination of the word line 24 of the conduit 1 and the bit line 26 of the conduit 1. Extrusion operation 1 can be performed. Similarly, the second
The combination of the word line 25 and the second bit line 27 (
' While performing the -8 write operation, +il due to the combination of the first word line 24 and 41 bit lines 26
C protrusion operation can also be performed.

With the above configuration, it is possible to configure a two-dimensional pseudo-static memory cell that can equally read and write data from 2L times.

FIG. 2 (bl is the memory cell 2 shown in FIG. 2 (2L))
? tmh Second implementation in which mXn pieces are arranged in n columns]
FIG. 2 is a conceptual diagram of a memory device f59. Memory device 59
The same circuits as those used in conventional pseudo-static memory devices can be used for the address circuit and signal line NA movement circuit that are essential for configuring the memory device. Omitted: Signal line 24 is X1lj
If selected 10,000 times, the word M proverb becomes address X1
．． I2. ..., select Xm, (It publication cotton line 2
5 When selected in the Y-axis direction, this is the word line and the address Y
l, Y2. ..., Yn is selected, the signal line 26 represents the bit line when selected in the X-axis direction, and the signal line 27 represents the focus line when selected in the Y-axis direction. -I42
The memory cells 29 arranged as shown in the figure (bl) have the address X1 (1=1.2..-, m) f (selecting and reading the data of the memory cells C111, C12,..., Gin). , C1j , C2j,”・, Qmj (j
=' +2. ..., n-) data 'i +rjC
If the number is 3+4, address Yj should be selected. In this case, conventional single-dimensional address memory devices are no longer available (only data can be transferred from two directions;
The two-dimensional tests that can be carried out in '9 all the time can be performed using static memory.

Fig. 245 shows only 11,3 of the present invention.

,”! As shown in 14(1), the memory cell 40 has a fuse 41-1 and a fuse 41-1, for example, an n-channel MIS type, and d is an effect transistor. transistors 22 and 25, two word lines 24 and 25, and two bit lines 26,
27 and k 44. The two word lines 24 and 25 are used to select the memory cell 40, respectively, and the second word line selects the memory cell 40, and the two bits 26 and 27 are used to select the memory cell 40, respectively. Data only (T): Read data from the recell 40 (7) Transferring bit line 1, second focus r>J. Fuse 4
1-1 is connected to the upper input/output terminal 20 at one end, and 11! ! Ground the end. Input/output y of fuse 41-1: The curtain 20 is
The gates of the transistors 22.25 are connected to the first word line 24, the second bit line 27, respectively, through the transistor 22 and the second bit line 27 through the transistor 23, while the gates of the transistors 22. Connected to word line 25.

Is there an overcurrent in the fuse 41-1 of the memory cell 40? This is a read-only memory cell whose write state is fixed at at depending on whether or not it is completely blown out.

When reading data from the memory cell 40 having such a configuration, similarly to the first embodiment and the second embodiment, after precharging the first focus line 26i to a high potential, the first focus line 26i is precharged to a high potential. The word line 124 is brought to a high potential. In this way, when the transistor controlled by the first word line 24 is turned on and the fuse of the memory cell 40 is not melted, the input/output terminal 20 is grounded, so the precharged first Bit line 26 is pulled to a low potential. On the other hand, if the fuse is blown, the input/output terminal 20 is not grounded, so the precharged first bit line 26 remains at the high level. f like this
Data is read by detecting a change in the first bit line of 481 bit lines.

Similarly, after the second bit line 27 is precharged to a new potential, data can be read by setting the second word line 25 to a high potential. Here, the read operation by the combination of the first word line 24 and the first bit line 26 and the 1σC extraction operation by the combination of the second word line 25 and the bit line 27 of 42 are completely different. You can do it in a stand-up manner.

In the above explanation, a fuse is used as the information holding means, but as shown in FIG. A field effect transistor 41-2, a diode 41-5 with one end connected to the input/output terminal 20-1 and the other end grounded. Alternatively, the memory cell 40t-gf can be constructed using MrS type turtle field effect transistors 4l-4t- with one end connected to the input/output terminal 20 and the other end grounded and diode grounded. What these information retention methods have in common is that
By fixing the input/output terminals in a high impedance state when grounded, the binary logic value "1" is set to "O".
It is to read out. In addition, 70-Teing Game) M
As the state writing means to the gate of the rS type field effect transistor 41-2, writing means similar to FROM using a conventionally used floating gate MIS type field effect transistor can be used. is omitted.

With the above configuration, it is possible to configure a two-dimensional read-only memory cell that can equally read data from 20,000 times.

FIG. 3 (C1 is the memory cell 40 shown in FIG. 5 (&)
FIG. 4 is a conceptual diagram of a memory device 42 according to a fifth embodiment in which mXn cells are arranged in m rows and n columns. For the address circuit and signal group stripe circuit which are essential for configuring the entire memory device 42, circuits similar to those used in conventional read-only memory devices can be used. Everything is clear 1-.

The signal line 24 becomes a word line when selected in the X-axis direction, and serves as the address) l, X2 . , Xrn is selected, and the signal line 25 becomes the word line when selected in the Y-axis direction, and becomes the address Y1. Y2. ..., Yn is selected, and the signal line 26 is
Represents the bit line when selected in the axial direction, and the signal line 27
represents the bit line when Y@Tokata is selected. FIG. 3 (Memory cells 40 arranged as shown in C1 are located at address
1(i=1.2...,l1l)'! ! i-Select;
When the memory cells O1j, rj12 . ..., G
In data is obtained, C1j , C2j , .= ,
(If you want to read the data at jmj (j = 1.2, . . . +, n), you can select the address Yj t-. It is possible to realize a two-dimensional read-on memory device that can read data from one time to the next at the same time.

The first example, the second example, and the fifth example are as follows.

The memory device that can select data from 20,000 times is the same. The difference between each embodiment is - input/output terminals'
i-? This is due to the difference between a capacitor and a static 7-tube fluorocarbon as the information retention means. Therefore, in the following embodiments, a capacitor is used as a representative means for storing information in a memory cell.
Embodiments using similar pseudo-static flip 70 tubes, fuses, etc. will be omitted.

A fourth embodiment, a fifth embodiment, and a sixth embodiment of the present invention are shown in FIG. 4 and FIG. 5, respectively.

FIG. 4 shows a circuit diagram of a memory cell 45 common to the fourth, fifth, and sixth embodiments. The memory cell 45 includes a capacitor 45 having - input/output terminals 44.
information holding means, for example, an n-channel MrS type field effect transistor, and seven transistors 46, 47.
, two word lines 48.49, and focus #! 50 and 7M.

The two word lines 48 and 49 are a first word line and a second word line for selecting the memory cell 43, respectively, and the bit line 50 is used for writing data into the memory cell 45 or reading data from the memory cell 43. Use the focus line to transfer data. The capacitor 45 has one end connected to the input/output terminal 44 and the other end grounded. The input/output terminal 44 of the capacitor 45 is connected to the bit line 50 via the transistor 46.
It is connected to the bit line 50 via the transistor 47i.

The gates of the master transistors 46 and 47 are the first
word 948, second word line 4? are connected to each.

Data t-S is stored in the memory cell 45 having such a configuration.
To write data, apply a potential in phase with the data to be written to bit line 5.
0, set the first word line 48t to high level, and set the first word line 48t to high level.
The word line 49 of is set to a low potential.

In this way, the transistor 46 controlled by the first word line 48 turns on 714 and conducts, so that the potential of the bit line 50 and the input/output terminal 44 are at the same level. In this way, 4F of data is written into the memory cell 43. To hold this data, both word lines 48.4?'i are set to a low potential and transistors 46 and 47f are turned off. By setting the state, the input/output terminal 44 and the bit line 50 are made non-conductive, and the capacitor 45 and the bit line are separated.In the memory cell 45, the combination of the first word line and the bit line, Since the combination of the second word line and the bit line is symmetrical, the second word lIJ49 and bit II#s are similar to the above description.

Data can be written in exactly the same way by combining it with .

To read data, the first word line 48 is brought to a high potential after the bit line 50i is precharged to a high potential. At this time, the charge accumulated in the capacitor 45 is transmitted to the focus line 50, and data is read by detecting a change in this potential. Similarly, bit line 50
Data can also be read by precharging the word line 49 to a high potential and then setting the second word line 49 to a high sleep state.

With the above configuration, it is possible to configure a two-dimensional dynamic memory cell that can equally read data from two directions using one bit line. Note that the memory cell 43 is a dynamic system that stores information using accumulation of loads.
He made 11 works. Therefore, as with ordinary dynamic memory cells, the load in the capacitor 45 is discharged over time, so rewriting and rewriting must be performed with constant clarity.

2. Since the amount of charge accumulated in the capacitor 45 decreases as data is read, rewriting must be performed immediately after data is read.

FIG. 5 ta+ is the memory cell 45f shown in FIG.

FIG. 4 is a conceptual diagram of a memory device @51-1 in the fourth embodiment in which mXn memory devices are arranged in m61 columns. The address circuit and total signal drive circuit necessary to configure the memory device 51-1 can be the same circuits as those used in conventional dynamic memory devices, so they are all omitted in the fJs diagram ta+. Teruru.

The signal line 48 becomes a word line when the X-axis force direction is selected, and corresponds to addresses Xi, X2, . ...Select tXmk, signal line 4
9 i Y ill This is the word line when the direction is selected, and the address Y1. Y2. ..., Yn is selected, and the signal line 50 is the common bit i when selected for both the X axis and Y axis.
t represents. In the X and Y axis directions, the number of word lines remains m and n, respectively, but the number of bit lines becomes m+n-1. Therefore, if the memory device 51-1 is selected in the X direction, it becomes a memory device with m rows and m+n-1 columns, and Y
Selecting the direction results in a memory device with n rows and m+n-1 columns.

Memory cell Gij (1=m1.2.-, m j-1
,2,・-.

n) as shown in Figure 88 (2), the bit line/m1
．． .

/111-11. /m-21,-,115,121,
/11. /12゜/I S, -, /I n-2,11
The data transferred by n-1, 11n ft is shown in Figure 6 (
The corresponding distance when selecting each axis direction as shown in &)
The correspondence relationship is determined in the case of selecting the yarn or the Y-axis direction as shown in FIG. 6(b). Figure 6 (al, (b)
In the strict character of Olj, 1〉m or j＞n is 1
It is assumed that clj with η exists or does not exist. Figure 7 ta
r and tbl respectively indicate the results obtained by excluding the portion shown above the ground in FIG. 6 (al, tl) 1. Figure 7 (
aJ is the correspondence relationship when selected in the X-axis direction as variable t1'
, t21, ・,・, tnI,
Figure 7 (bl shows the correspondence relationship when selected in the Y-axis direction with respect to variables 11', 12'', =, /m''. Comparing Figure 7 (aJ and Figure 7 (bJ), Figure ta + t is rotated 90 degrees clockwise in Figure 7 (
b). That is, data for combinations of memory cells in different directions can be obtained from a common bit line depending on the word line selection direction. In this way, data i, jl: and '-1 from two orthogonal directions, which was impossible in conventional single-dimensional address memory devices, can be transferred to a common bit line by selecting the word line selection direction. A two-dimensional dynamic memory device can be realized.

Figure 45tb+ shows the memory cell 43 shown in Figure 4 as m6.
A fifth embodiment of the memory device in which mXn1 is fixedly arranged in one column! It is a conceptual diagram of α51-2. Memory device 51-2k
+:'j To form the address circuit, signal g drive circuit -, J? Since the same circuit as that used in the conventional YINAMINK memory device can be used, the fifth
All of them are omitted in Figure (b).

The signal line 48 becomes a word line when selected in the direction of X<ib and corresponds to the address X1. X2. ..., Xm is selected, and the signal side 49 is selected in a direction in which the memory cell row is displaced by 1 in the x-axis direction and 211 minutes in the Y-axis direction, which is the so-called Katsura horse-jumping direction. Word lines and addresses R11, R21, R12, R22, R15, R2
5゜..., Ran, R2n, Ran, -, R
mn f is selected, and the signal line 50 is a common bit line x1. x2
．． ...txnt".

As a result, there are m word lines in the X-axis direction, m -1-2n -2 word lines in the Keizai direction, and n bit lines. Therefore, if the memory device 51-2 is selected in the Y direction, it becomes a memory device with m61 columns,
When selecting the direction of the horse jump, it becomes a memory device with m-1-2n-2 rows and n columns.

In this way, data can be read from two directions, horizontally and diagonally upward to the right, which is impossible with conventional single-dimensional address memory devices, by changing the word line selection direction. A two-dimensional dynamic memory device can be realized using a common bit line.

FIG. 5(C) shows the memory cell 45 shown in FIG.
FIG. 12 is a conceptual diagram of a memory device 51-5 according to a sixth embodiment in which m61 columns are arranged in m×n arrays in the case of n. Memory device ff151-5 Since the address circuit, line 1a drive i1+Q circuit, etc. that are required to form the metal tΔ can be the same circuits as those used in conventional dynamic memory devices, the circuits shown in Figure 5 (cl. All of them have been omitted.

The signal line 48 becomes a word line when the xm direction is selected and corresponds to the address X1. X2. ..., select Xm and connect signal line 4
? is displaced by one memory cell row in the lx axis direction, and Y@
By connecting the signals selected in the diagonal direction and diagonal direction by one solid displacement in the direction, it becomes a word line that selects one cell per row of memory cells in the Y-axis direction, and addresses R1, R2, . . . +Rm ', and the signal line 50 is
Common bit line x1 when selected in two directions i-direction and diagonal direction. x2. ..., xnt-represents. As a result,
There are m word lines in the other x direction, m word lines in the diagonal direction, and n bit lines. Therefore, if the memory devices 5l-5tl--X-axis direction and diagonal direction are selected, the memory devices will both have m rows and n columns.

In this way, data can be read and written from two directions, horizontally and diagonally upward to the right, which was impossible with conventional single-dimensional address memory devices. A dynamic memory device assembly can be realized.

What can be said in common from the fourth embodiment, the fifth embodiment, and the sixth embodiment 1j is that if the word line connection relationship is one or less on the selected memory cell for each bit edition, , the connection relationship of the word lines can be arbitrarily selected.

FIG. 8 shows a seventh embodiment of the present invention.

The circuit diagram of the memory cell is shown in FIG. 188 (aJ).
m5! information holding means and, for example, an n-channel MIS type field effect transistor. J, broken transistor 55
~58, 4 words lFM59-62, and 2 bits? is6' + 6' and 7M.

Four word lines 59-1s 2 each correspond to a memory cell 5.
The first to fourth word lines 65 and 64 select the first to fourth word lines, respectively, and the two bit lines 65 and 64 select the first to fourth word lines 65 and 64, respectively. , the second bit line. The capacitor 54 has one end connected to the input/output terminal 53 and the other end grounded. The input/output terminal 55 of the capacitor 54 is connected to the transistors 55 and 57.
The focus line of 131 is 65VC, with the angle of 58°.
The transistor 56 is connected to the second bit line 64 through all the transistors 56 . The gates of transistors 55-58 are connected to word lines 59-62, respectively.

In order to write -N data into the memory cell 52 which is to be filled with -F, a potential in phase with the data to be read is applied to the focus position 63 of channel 1, and the first word line 59
Place the board in the east position, and set the other word lines 60 to 62 in the low position.
rank. In this way, the transistor 55 controlled by the word line 59 of 41 is turned on and traces; The capacitor 54 is charged so that the
4. In this way, data is loaded into the memory cell 52. Keep this data +'v
All words lol! ,'! 59-62'Jfl low potential. This is done by turning off all the transistors 55 to 58, so that the input/output terminal 55 and the first bit line 6
5. Make the area between the second focus line 64 non-exclusive,
This is to prevent the charge accumulated in the capacitor 54 from being dissipated. In the memory cell 52, the first word line and! -1
−81 bit line combination set, i, g2 word line and second bit line combination set, third word line and 51S1 focus line combination set, fourth word line and Since the combination with the first focus line has a sealed structure, similarly to the above explanation, the combination with the second word line 60 and the second focus line 64, Data can be written in the same way by the combination of the third word line 61 and the first bit line 63 and the combination of the fourth word line 62 and the first bit line 63.

To read one line of data, the first bit line 6'5 is set to the precharger 7, and the first word line 6'5 is set to the level CIL. If this is done, the capacitor 54 will be filled with a defective tl; Similarly (・
Data can also be spilled out by precharging the second bit acid 64 to make the quotient f 9th, and then setting the second word i 60 to the high iij position. Also, the first
After pre-charging all pit lines 65 and putting Akane in the position,
By setting the fifth word line 61'rM to the first position, or by setting the fourth word line 62 to the high 1E level while the first bit line 65 is fully precharged to the Hatake potential, Data can be read.

Here 1. , l', 1, culvert 3. Or read creation by the combination of the fourth word line and the first focus line, and f by the combination of the second word line and the second bit H
f1 (can be performed completely independently of the protrusion operation.Furthermore, the combination of the second word line and the second bit line
While the write operation (1) is performed, the read operation (7) can be performed using a combination of the first, third or fourth word line and the first pit line. Similarly, a write operation is performed by a combination of the first, third, or fourth word line and 41 focus lines, while a write operation is performed by a combination of the second word line and the second bit line. It is also possible to perform a l-extrusion operation.

With the above configuration, X in the first embodiment.

A memory cell that can be selected from two diagonal directions in addition to the Y2 direction can be constructed, and a two-dimensional dynamic memory cell that can equally read and write data from four directions can be constructed. Note that the memory cell 52 performs a dynamic operation of storing information using accumulation of charge. Therefore, like a normal dynamic memory cell, the charge in the capacitor 54 is discharged over time, so re-reading must be performed at a constant cycle. Also, the capacitor 54
Since the amount of memory accumulated in the memory decreases as data is read, it is necessary to rewrite the data immediately after reading the data.

FIG. 8 (bl is the memory cell 52 shown in FIG. 8 (al)
FIG. 12 is a conceptual diagram of a seventh embodiment of a memory device t65 in which mXn memory devices are arranged in zm rows and n columns. Memory device 6! l-4
! The address circuit, signal line drive circuit, etc. required for l1gy can be the same circuits as those used in conventional dynamic memory devices. be.

The signal line 59 has 4!77 addresses XI, X2. -, Xm kii3 is selected, and the signal line 60 is the word line when selected in the Y-axis direction. Y2, ・-, Yn t-select, signal? s61 is the word line when selected diagonally in the upper right direction, and addresses R+ +, R+ 2. -, Ftl n-1
, R+ n, R2n , =·, Rm n, and the signal line 62 becomes a word line when selected diagonally in the upper left direction, and addresses Lm +, Lm-12 . ....

L2 Ding, LI I, LI 2. -, LI
n\: selected, and the signal line 65 is pit line xi, x2. ...
, xn, and the pit lines y+, y2 . ...represents rYm. If the word line is addressed first and second, the word line is m + n.
-1 line, but the bit width of the data read and written is n
It remains a bit.

Therefore, if a memory array arranged in m rows and n columns is selected diagonally, it becomes a memory in m+n-1 rows and n columns. Also, Figure 8 (bl
The memory cells 52 arranged as shown in FIG.
-1, 2, -, +11) fr, when selected and read, the data of memory cells C11, C12, ..., Gin is obtained, and a1j+02 j+・+0m j (j-1, 2,
. , n), select address Yj.

In this way, in addition to the two directions of the X and Y axes, it is possible to select from two diagonal directions, and the data reading is X.

A memory device that can operate in two directions along the Y axis can be realized.

FIG. 9 shows an eighth embodiment of the present invention.

The circuit diagram of the memory cell is shown in FIG. 9 (al).
a transistor 69 constituted by, for example, an n-channel MIS type social effect transistor;
70.71, 74 to the three word lines 72, and 77 to the five focus lines 75.

Each of the three word lines 72, 7j, and 74 is a memory cell 66? Select the first word line, the second word line, and the fifth word line.
The three bits S75, 76, and 77 are respectively the write data to the memory cell 66, the read data from the memory cell 66, and the 1st focus line, the 2nd bit line, This is the fifth pi Bg. The capacitor 68 has one end connected to the input/output terminal 67 and grounded at the other end. The input/output terminal 67 of the capacitor 68 is connected to the first bit line 75 via a transistor 69, to the second bit line 76 via a transistor 707, and to the third bit line 77 via a transistor 71tJf'. while the gates of transistors 69, 70, and 71 are connected to a first word line 72, a second word line 75, and a fifth word line 74, respectively.

To write data to the memory cell 66 in such a configuration, a potential in phase with the data to be written is applied to the first focus line 75, the first word line 72 is set to high level, and the other word? Set #75 and 74 to low potential. In this way, the transistor 69-1)' which is controlled by the first word line 72 is turned on and turns on, so that
The capacitor 68 is charged and discharged so that the potential of the first bit line 75 and the input/output terminal 67 are at the same potential. In this way, data is written into the memory cell 66. To hold this data, all word lines 72 to 74 are set to a low potential, and all transistors 69 to 71 are turned off, thereby connecting input/output terminal 67 and other bit lines 75 to 77, respectively. This is to make the capacitor 68 non-conductive and to prevent the charge accumulated in the capacitor 68 from being discharged. In the memory cell 66, the combination of the first word line and the first bit a;
a combination of a second word line and a second bit line, a fifth
Since the combination of the word line 75 and the third bit line is symmetrical, the combination of the second word line 75 and the bit line 76 of rlZ2 is similar to the above explanation.
and B1 between the third word line 74 and the third bit line 77
Data can be written in exactly the same way by combining them.

K for reading data is the first word line 72 precharged to a high potential after precharging the first word line 75 to a high potential. In this way, the charge accumulated in the capacitor 28 is transferred to the first pin! I75 was informed that this IJ
Data is read by detecting all changes of the order of t. Similarly, after the second bit line 76 is precharged to a high potential, the second word K175 is set to a & potential, and after the fifth pit line 77 is precharged to a high potential, the third word K175 is precharged to a high potential. Data can also be solicited by setting the word 1fJ174 to a high potential. Here, a read operation is performed by a combination of a first word line and a first pit line, a read operation is performed by a combination of a second word line and a second pit line, and a read operation is performed by a combination of a third word line and a third word line. The read operation can be performed completely independently of the read operation in combination with the 30 bit lines. Further, while a read operation is performed by the combination of the word line and the first bit line of nest 1, a read operation is performed by the combination of the second word line and the second bit line, and a read operation is performed by the combination of the second word line and the second bit line, and the third bit line is A read operation can be performed using a combination of the word line and the fifth bit υ. Similarly, the second word line and the second bin I
While performing the 1F loading operation in combination with N,
A read operation can be performed using a combination of the third word line and the third bit line, and a read operation can be performed using the combination of the first word line and the first bit line.

Also, while performing a write operation using the combination of the third word line and the third bit line, the first word line and the first
A read operation can be performed in combination with the second word line and the second bit line, and a read operation can be performed in combination with the second word line and the second bit line.

With the above configuration, it is possible to form a three-dimensional dynamic memory cell tm that can equally read and write data in three directions. It should be noted that the memory cell 6B performs a tedious operation in which information is stored using the accumulation of data. Therefore, as in a normal mechanical memory cell, the charge in the capacitor 68 is discharged over time, so rewriting must be performed at regular intervals. Further, since the 1f accumulated in the capacitor 6B decreases by 1f when reading data, it is necessary to rewrite the data immediately after reading the data.

FIG. 9 (bJ is the memory cell 66 shown in FIG. 9 (al)
24 is a conceptual diagram of a memory device fe7B which is an embodiment of 24'l, f3 in which 27 24'l, f3 are arranged in 6 x 13 columns and 3 layers.

For the memory device 78 and the necessary address circuits and signal line 1 motion circuits, circuits similar to those used in the 6゛E American Dynabank Mechanical Device can be used. Figure 9 (In BL, it is all omitted.

Signals #72 to #74 represent word lines arranged in a concave shape, and signal lines #75 to #77 represent bits, respectively. The signal line 72 is r! when a metal plate perpendicular to the X-axis direction is selected. 41 words are narrowed down and the address is X.
i, X2. X3 is selected, and the signal line 76 becomes the second word line when the line perpendicular to the Y axis is selected, and the address Y1
．． Y2. Y3'i is selected, and the signal line 74 is the fifth word line when the circle r perpendicular to the Z axis is selected, /J, quad addresses Z1, Z2 . Select Z3 Line 1-113 7S represents the first bit line tray when the X-axis direction is selected, the signal line 76 represents the focus tray of the second bit line when the Y-axis direction is selected, and the signal line 77 represents the 3rd when Z-axis direction V is selected
bit line yz8. 27 fled memory (/l
/ C1jk (i, j, k = 1°2.3)'i Arrange as shown in Figure 9 (1) l. When address χ1 is selected and read, 0111°G112. from the first bit line. Gi
l 3. C121, C122, G123. Ui31.0
132. C; L33 data is obtained, 011 to 012k from the third bit line.

013, 021, 022, 025, 031,
If you want to read out the booter of 033k at 052, select address Zk. In this way, it is possible to realize a three-dimensional dynamic memory device that can perform readings from five directions 14 times, which was impossible with conventional single-dimensional address memory devices.

As described above, in the first embodiment, a two-dimensional dynamic memory device is used, in the second embodiment, a two-dimensional pseudo-static memory device, and in the third embodiment, a two-dimensional read-only memory device. In the case of the fourth embodiment, the fifth embodiment, and the sixth embodiment, the bin in one direction) +J is 2
In the case of a two-dimensional dynamic memory device in which the direction can be selected, in the seventh embodiment, the bins in two directions are selected. The case of a dimensional dynamic memory device is presented. As shown in these examples, the transistor and word line combination K 1126 and L
The book's focus line and a 1-bit information holding means with input/output terminals constitute a multidimensional memory cell that can be selected from K directions and can read/write data from L directions. Now, there is a multidimensional address memory characterized in that a plurality of these memory cells are arranged in an array, and data can be read/written from L directions using word lines, and data can be read/written from L directions using word lines. The equipment can be realized.

FIG. 10 shows an example in which the multidimensional memory device according to the present invention is applied to the button memory device in the example of FIGS. 13 and 14, which is referred to as V in the prior art section. 1 from the X, Y, two directions and two diagonal directions shown in Figure 10.
The multi-dimensional memory device of the present invention is shown in FIG.
: The address and focus line of the memory device #79 in FIG. 10 are used with the same g and j15 as the memory device @65.

When scanning data in the X-axis direction: X to address x1
7 and read from x5 to bit line x1.

Dress R11, R12, R13, F114. R15,
R25, R35° R45, R55, R65, R75 to select and read from bit lines x1 to x5 at once.

Dress L15.1,14. L, 13. L12. L
ll, L21. L31°L41. L51. Muro 1
．． Selected by L71 and read out from focus lines x1 to x5 at once.

The focus lines Y1 to Y5 are selected and read from the focus lines Y1 to Y7.

From the above, which direction should the data come from? Even when reading and writing, − selections are sufficient. That is, in a single-dimensional address memory device with mhn columns, when scanning in a direction different from the word line, m selections were necessary at worst, but this can be performed with - selections. Further, according to the present invention, the memory g ii"j 'z :II
Not only does this eliminate the need to rearrange the data in the memory device, but also eliminates the need to rearrange data for each scanning direction.9 This has the effect of significantly reducing the amount of hardware and selection time. There is.

In the above, only a small number of embodiments of the memory device have been described, but for example, in the memory device of the above embodiment in which a capacitor is used as the information retention means of the memory cell, the medium between the two magnetic poles of the capacitor is If a liquid crystal is used as a liquid crystal display, the present invention can realize a multidimensional memory device having a panel function using an optical display that can store data from multiple directions in a single function song with binary memory using 111 elements. Variations and changes to Jt+ can be made without breaking the spirit.

〔Effect of the invention〕

According to the memory device of the present invention, X
It is possible to realize a multidimensional memory device λ that can select from a plurality of directions, such as 1Y2 directions, X%Y2 directions, Z5 directions, and 4 directions including 2 diagonal directions in addition to the X and Y2 directions. By using the multidimensional memory device of the present invention when processing all data arranged in two or three dimensions, such as image processing or character recognition, it is possible to perform multidimensional processing that was not possible with conventional single-dimensional memory devices. It becomes possible to easily read data from any direction and input vI@.

[Brief explanation of drawings]

The MI diagram shows the first embodiment of the present invention, and FIG. 1 (al is a memory cell t, FIG. Figure 2 shows the second embodiment of the present invention.
FIG. 9 (1al) shows a memory cell, FIG. 2(bl) shows a memory device ii′t- using the memory cell of FIG. FIG. 9 (1al) shows the memory cell, FIG. 3 (bl shows another configuration of the memory cell in FIG. 3 (shrine), and FIG. Memos used!
(bl, +CI are unprinted figures of the memory devices of the '#, 4th, 5th, and 6th embodiments using the memory cells of FIG. 4, respectively.
Figure 6 (ILI, (bl), Figure 7 (al, (bl is the fifth
FIG. 8 (al) is a diagram for explaining the memory device r, FIG. 8 shows the seventh embodiment of the present invention, FIG. FIG. 9 shows an implementation 11 of 1-8 of the present invention, and FIG.
[U ("l is a diagram showing a memory device using memory cells of Figure 9 (al), Figure 10 is a diagram of a multidimensional pattern memory device for character data, Figure 1411 is tal, t
12(&;, tb+ respectively represent a conventional 6-transistor type pseudo static memory cell) 1 and a diagram showing a memory device using the same.
Figure 3 (al, (bl) is a diagram explaining the case where the pattern memory device for character data is 111i!il, 14th (¥1
(2L) ~ (dl is pattern memory device for character data +d
It is a figure explaining the case where i is 41 hard. 19... Two-dimensional dynamic memory cell 20... Input/output terminal 21... Capacitor 22.23... N-channel MIS type [a)'≠Effective transistor 24.25... Word-like 26.27 ...Bit line 28...Two-dimensional dynamic memory device is 29...2
Dimensional pseudo-static memory cell 30...pseudo-static type clip prongs 31-33...n-channel M
IS type field effect transistor! 54.55...p-channel MIS type field effect transistor 38...coupling control signal line 59...degree two-dimensional static memory device 40...
... Two-dimensional read-only memory cell 41 ... Read-only information holding means 41-1 ... Fuse 41-2 ... Floating goo) MIS type magnetic field effect transistor 41-5 ... Diode 41-4 ... Diode-connected MIS field effect transistor 42 ... Two-dimensional read-only memory loading 45
...Memory cell 44 with one selected two-direction focus line...
Input/output terminal 45...Capacitor 46.47...N-channel MIS type field effect transistor 48.49□...Word line 50...Bit line 51-1 to 51-3...2-dimensional f Select 2 direction bit line 1
Direction dynamic memory device 52... 82 memory cells 56 with 4-direction selection
... Input/output terminal 54 ... Capacitors 55 to 58 ... To n-channel MIS type field effect transistor 59 62 ... Word line 63.64 ... Bit line 65 ... Two-dimensional selection four-way bit Line two-way dynamic memory device 66... Three-dimensional dynamic memory cell 67... Input/output terminal 6 days... To capacitor 69 71... N-channel MIS type 4 (field effect transistor 72S74... Word To line 75 77...Bit line 78...Three-dimensional dynamic memory device 79...Multidimensional memory device for character data (b) ノ, Y2
Yn(α) (C) Y+ Yz Y
n] (b) Figure 3 (C) Y, Y2 Yn (α) (E)) Work 1 x, 2 Person n (
α) (F)> 14th = (α) (b) “ χ1 :L2χ3χ4 λ5

Claims (1)

[Claims] 1-bit information holding means comprising K transistors (K≧2, integer), K word lines, L bit lines (K≧L≧1, integer), and one input/output terminal; , and for each of the K transistors, the Mth (K
≧M≧1, an integer), the gates of the transistors are connected to the Mth word line, one ends of all the K transistors are connected to the input/output terminal of the information holding means, and A plurality of memory cells each having an end connected to an arbitrary one of the L bit lines are arranged in an array, and each of the word line and bit line is connected to one of the L bit lines.
A memory device characterized in that by commonly connecting memory cells arranged in the K direction and the L direction, it is possible to select from the K direction and to read, write, or read data from the L direction.