JPS6163034A - Controlling system for uniform thickness of oxide film in semiconductor manufacturing furnace - Google Patents

Controlling system for uniform thickness of oxide film in semiconductor manufacturing furnace

Info

Publication number
JPS6163034A
JPS6163034A JP59184617A JP18461784A JPS6163034A JP S6163034 A JPS6163034 A JP S6163034A JP 59184617 A JP59184617 A JP 59184617A JP 18461784 A JP18461784 A JP 18461784A JP S6163034 A JPS6163034 A JP S6163034A
Authority
JP
Japan
Prior art keywords
temperature
furnace
wafer
oxide film
furnace wall
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP59184617A
Other languages
Japanese (ja)
Inventor
Ikuo Matsuba
松葉 育雄
Kinji Mokuya
杢屋 錦司
Kuniaki Matsumoto
松本 邦顕
Tetsuya Takagaki
哲也 高垣
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP59184617A priority Critical patent/JPS6163034A/en
Publication of JPS6163034A publication Critical patent/JPS6163034A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02107Forming insulating materials on a substrate

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)

Abstract

PURPOSE:To reduce the number of defective wafers by a method wherein the furnace wall of a heating furnace is divided into zones in the direction of furnace axis, and temperature is controlled in such a manner that the function of evaluation, having the difference of the temperature in the direction of furnace axis of a wafer and the presumptive value of the oxide film thickness obtained from the wafer temperature and the target value is considered as an evaluated value, becomes the minimum. CONSTITUTION:A heating furnace 101 is cylindrical tube. A wafer 102 is placed on a boat 1020 located in the center part, conveyed into the furnace 101, a heat treatment is performed thereon, and the wafer 102 is discharged outside the furnace 101. The designed oxide film thickness tOX is inputted to an optimum calculating device 106, the target wafer temperature is calculated by the calculating device 106, and the temperature of the furnace wall of a zone 3, with which the wafer is uniformly heated by heaters 103, 104 and 105, is determined. The temperature of the furnace wall is determined using a non-linear distribution system model equation with which the temperature in the direction of furnace axis of the wafer is estimated from the temperature of the furnace wall, in such a manner that the function of evaluation, wherein the difference of non-linear model with which the thickness of an oxide film is estimated from the wafer temperature, the presumptive value and the target value are considered as the evaluation value, will become the minimum. Through the above- mentioned procedures, the number of defective wafers is reduced, and the uniformity of the thickness of the oxide film can be improved.

Description

【発明の詳細な説明】 〔発明の利用分野〕 本発明は半導体製造プロセスの酸化、拡散工程などで用
いられる炉内の温度の制御方式に係り。
DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a method for controlling the temperature inside a furnace used in oxidation, diffusion steps, etc. of semiconductor manufacturing processes.

特に炉内におかれた多数のウェハの炉軸方向の酸化膜厚
分布の均一化制御方式に関する。
In particular, the present invention relates to a method for controlling uniformity of oxide film thickness distribution in the axial direction of a large number of wafers placed in a furnace.

〔発明の背景〕[Background of the invention]

炉内の多数のウェハの酸化膜厚を設計で定められた値に
均一にするためには、ウェハの温度を均一にする必要が
ある。従来の炉は、炉壁面全体が一定温度になるように
制御されていたが、ウェハ自体の温度は炉軸方向に分布
をもっていることが実測値から分っている。炉内に温度
センサを装備すると酸化膜厚をばらつかせることになる
ので、炉壁温度より炉内部のウェハ温度を推定すること
のできるモデルの開発が要求される。従来のように炉壁
を一定温度で加熱する方法によると、ウェハの位置によ
り温度が異なり最終的に完成した半導体特性のばらつき
を生じ1歩留りを減少させる結果となる欠点を持つ。
In order to make the oxide film thickness of a large number of wafers in the furnace uniform to a value determined by design, it is necessary to make the temperature of the wafers uniform. Conventional furnaces are controlled so that the entire furnace wall surface has a constant temperature, but actual measurements have shown that the temperature of the wafer itself has a distribution in the axial direction of the furnace. If a temperature sensor is installed inside the furnace, the oxide film thickness will vary, so it is necessary to develop a model that can estimate the wafer temperature inside the furnace from the furnace wall temperature. The conventional method of heating the furnace wall at a constant temperature has the disadvantage that the temperature varies depending on the position of the wafer, resulting in variations in the characteristics of the final semiconductor and a reduction in yield.

〔発明の目的〕[Purpose of the invention]

本発明の目的は、炉内の軸方向のウェハ温度分布を、目
標温度分布(一定温度)に近づけて運転できるようにす
るための、半導体製造炉内の酸化膜厚分布均一化制御方
式を実現することにある。
The purpose of the present invention is to realize a control method for uniformizing the oxide film thickness distribution in a semiconductor manufacturing furnace so that the wafer temperature distribution in the axial direction in the furnace can be operated close to the target temperature distribution (constant temperature). It's about doing.

〔発明の概要〕[Summary of the invention]

炉内は1000℃以上の高温になっているため、耐久性
等の問題から通常のセンサ(たとえば熱電対)を炉内温
度のオンライン計測に利用することはできない。そこで
1本発明では炉壁温度から炉内部のウェハ温度を推定で
きる非線型分布系モデルを構築し、このモデルに基づい
てゾーン分割された炉壁温度分布を決定する制御方式を
与える。
Since the inside of the furnace is at a high temperature of 1000° C. or more, ordinary sensors (for example, thermocouples) cannot be used for on-line measurement of the temperature inside the furnace due to durability and other issues. Therefore, in the present invention, a nonlinear distribution model is constructed that can estimate the wafer temperature inside the furnace from the furnace wall temperature, and a control method is provided for determining the zoned furnace wall temperature distribution based on this model.

〔発明の実施例〕[Embodiments of the invention]

以下、本発明を実施例により説明する。 The present invention will be explained below using examples.

第1図は本発明を実施する半導体の酸化拡散装置の構成
を示す6炉内部状態を推定するモデルに基づき、加熱炉
壁温度を例えば炉壁に装置されたヒーターで調整するこ
とによりウェハを均一温度で加熱する制御手順について
説明する。@1図において、対象とする炉101は円筒
型のチューブでウェハ102はその中央部のボート10
20に乗せられて炉101内へ搬送され、熱処理を受け
、再び炉101外へ出て行く。問題となるのは炉軸(Z
軸)方向の炉内の温度分布の推定である。ボート中央部
にあるウェハは両隣りのウェハからの輻射及び炉壁から
の輻射により加熱されるので中央部のウェハは両端部の
ウェハより高温になる。
Figure 1 shows the configuration of a semiconductor oxidation diffusion device according to the present invention.Based on a model for estimating the internal state of the 6-furnace, wafers can be uniformly heated by adjusting the furnace wall temperature, for example, with a heater installed on the furnace wall. The control procedure for heating by temperature will be explained. In Figure @1, the target furnace 101 is a cylindrical tube, and the wafer 102 is in the boat 10 in the center.
20 and transported into the furnace 101, subjected to heat treatment, and then exited from the furnace 101 again. The problem is the furnace axis (Z
This is an estimation of the temperature distribution inside the furnace in the axial direction. The wafers in the center of the boat are heated by radiation from the wafers on both sides and by radiation from the furnace walls, so the wafers in the center become hotter than the wafers at both ends.

従って、ウェハを均一温度で加熱するための炉の温度制
御は以下のようにして行なわれる。たとえば、設計酸化
膜厚し。X′を最適計算装置106に入力し、内部でウ
ェハの目標ウェハ温度T1を計算し、後述する計算方法
によりウェハをヒータ、103.104、及び105で
均一加熱するような3ゾーンの炉壁温度を決定する。こ
の例では3ゾーンにしであるが、一般には何ゾーンでも
可能である。炉壁温度が決定されると、センサ108の
炉壁温度測定結果と上記a適計算装置106で決定され
た炉壁温度との差分を減算器100で計算してこの差分
に基づき、PIDコントローラ107を用いる事により
、電源109を調整し、前記ヒーター103,104お
よび105により所定の温度に加熱する。
Therefore, temperature control of the furnace for heating the wafer at a uniform temperature is performed as follows. For example, design oxide film thickness. X' is input to the optimum calculation device 106, and the target wafer temperature T1 of the wafer is calculated internally, and the furnace wall temperature in three zones is determined so that the wafer is uniformly heated by the heaters 103, 104, and 105 using the calculation method described later. Determine. In this example, there are three zones, but generally any number of zones is possible. When the furnace wall temperature is determined, the subtracter 100 calculates the difference between the furnace wall temperature measurement result by the sensor 108 and the furnace wall temperature determined by the a-optimal calculation device 106, and based on this difference, the PID controller 107 By adjusting the power supply 109, the heaters 103, 104, and 105 are heated to a predetermined temperature.

次に、炉壁温度を設定する手順の概略を示す。Next, the procedure for setting the furnace wall temperature will be outlined.

まず、入力t。−からT”に変換する関数を用意しなけ
ればならない。
First, input t. You must prepare a function to convert from - to T''.

T’  =F1  (tOX’  )        
   (1)目標ウェハ温度T”が求まると、ウェハ温
度T、(iはウェハ番号で、1からNまでの値をとる)
と炉壁温度分布T、(k)(k=1.2.3)との関数
関係が必要となる。
T' = F1 (tOX')
(1) Once the target wafer temperature T'' is determined, the wafer temperature T, (i is the wafer number and takes a value from 1 to N)
A functional relationship between and the furnace wall temperature distribution T, (k) (k=1.2.3) is required.

T、=F21 (’r、(k))        (2
)したがって、T、がT”に近づくような評価を考えれ
ばよいので、次のような評価関数を採用する。
T,=F21 ('r, (k)) (2
) Therefore, since it is only necessary to consider an evaluation in which T approaches T'', the following evaluation function is adopted.

J=Σ (”rt  −”r”  )”       
   (3)以上のアルゴリズムをまとめると、第2図
のようになる。まず201で(1)式に従って目標酸化
膜厚から目標ウェハ温度に変換し、202で適当な初期
炉壁温度を設定する。この値を用いて。
J=Σ("rt-"r")"
(3) The above algorithm can be summarized as shown in Figure 2. First, in step 201, the target oxide film thickness is converted into a target wafer temperature according to equation (1), and in step 202, an appropriate initial furnace wall temperature is set. using this value.

(2)式に従ってウェハ温度T1を求める。T、とT8
を評価式(3)に代入し、Jがある適当な微小値Eより
は大きいときは炉壁温度分布をJが小さくなるように設
定し直して、再び203でウェハ温度T、を計算する。
The wafer temperature T1 is determined according to equation (2). T, and T8
is substituted into the evaluation formula (3), and when J is larger than a certain appropriate small value E, the furnace wall temperature distribution is reset so that J becomes smaller, and the wafer temperature T is calculated again at 203.

もしJがεより小さいとき、ループ205を抜ける。こ
のときの炉壁温度分布が最適な炉壁温度分布となり、ウ
ェハ温度分布の均一化が得られる。
If J is less than ε, loop 205 is exited. The furnace wall temperature distribution at this time becomes the optimal furnace wall temperature distribution, and a uniform wafer temperature distribution can be obtained.

以下では(1)〜(3)式の具体的な表示を与える。Below, specific representations of equations (1) to (3) will be given.

(1)式としては、有名はDeal −Groveの式
を用いるtax”+A(T)tox=sD)t    
 (4)ここに、tは酸化時間を示し、A、Bは次のよ
うなアレニウス型の温度依存性をもつ。
As formula (1), the famous formula is Deal-Grove.tax"+A(T)tox=sD)t
(4) Here, t represents the oxidation time, and A and B have the following Arrhenius temperature dependence.

A(T)= alle X p (、at / T)B
(T)=bl、eXp (−b、/T)    (5)
右辺に表われる係数はすべて定数で、実験より定められ
るべきものである0次に、(2)式としては次のような
熱伝導方程式を用いる。
A(T)=alleXp(,at/T)B
(T)=bl, eXp (-b, /T) (5)
The coefficients appearing on the right side are all constants and are of the zeroth order, which should be determined experimentally.The following heat conduction equation is used as equation (2).

+、X *1 Ja i Wa TJ’、%。G、、J
dS。
+, X *1 Ja i Wa TJ', %. G,,J
dS.

−1ノ1L +、/’a i 、T、’ΣF、dS。-1 no 1L +, /’a i  ,T,’ΣF,dS.

+d i v (Kw−gradT、)    −・・
(6)ここで、TIはi番目ウェハ温度、CWはウェハ
比熱、σ、はウェハ密度、Q、はウェハ厚み、tは時間
、σはボルツマン・ステファン定数、aはウェハ熱吸収
率、ε、はウェハ輻射率、G、、」はウェハ間係態係数
で添字nは反射回数を表わす。
+d iv (Kw-gradT,) -...
(6) Here, TI is i-th wafer temperature, CW is wafer specific heat, σ is wafer density, Q is wafer thickness, t is time, σ is Boltzmann-Stefan constant, a is wafer heat absorption rate, ε, is the wafer emissivity, G is the inter-wafer coefficient, and the subscript n represents the number of reflections.

T、は炉壁温度、ε、は炉壁輻射率、F、はウェハの炉
壁間形態係数、K、はウェハ熱伝導度。
T is the furnace wall temperature, ε is the furnace wall emissivity, F is the wafer wall-to-wall view factor, and K is the wafer thermal conductivity.

dS、、dS、はそれぞれ炉壁面、ウェハ面の微小面積
片を表わす。また(6)式右辺については、第一項で自
己輻射損失、第二項で隣接ウェハからの輻射、第三項で
炉壁からの輻射、第四項で熱拡散を表わしている。
dS and dS represent minute area pieces of the furnace wall surface and wafer surface, respectively. Regarding the right side of equation (6), the first term represents self-radiation loss, the second term represents radiation from adjacent wafers, the third term represents radiation from the furnace wall, and the fourth term represents thermal diffusion.

(3)式の具体的なアルゴリズムとして、たとえば次の
ような単純な方法が考えられる。今、第2図の202で
設定する初期炉壁温度TWa(k)とするとループ20
5を1回まわったとき、次に設定すべき炉壁温度は’r
y’(k)+ΔT、’(k)となる。
As a specific algorithm for formula (3), for example, the following simple method can be considered. Now, if the initial furnace wall temperature TWa(k) is set at 202 in Fig. 2, loop 20
5, the next furnace wall temperature to be set is 'r
y'(k)+ΔT,'(k).

=こで、ATt。(k)=−kaJ/θT、(k)t’
ある。には適当な正の定数とする。Tt’(k)を最適
値T、”(k)に十分近い値を設定すると、このような
単純なアルゴリズムでも、十分精度のよい最適値が得ら
れる。
=Here, ATt. (k)=-kaJ/θT, (k)t'
be. Let be an appropriate positive constant. If Tt'(k) is set to a value sufficiently close to the optimum value T, ``(k), a sufficiently accurate optimum value can be obtained even with such a simple algorithm.

第3図に、炉壁温度を一定にした場合(a)と、上記の
ような計算手順にしたがって決定した炉壁温度分布より
求めた場合(b)のウェハ温度分布T、を示す。炉壁温
度を一定にした場合には、ウェハ列両端の数枚のウェハ
は温度が低くなっているが、3ゾ一ン分割した炉壁温度
分布のTF <1)とT、(2)を高温にすると、ウェ
ハの炉軸方向分布が均一化される。
FIG. 3 shows the wafer temperature distribution T when the furnace wall temperature is kept constant (a) and when it is determined from the furnace wall temperature distribution determined according to the calculation procedure described above (b). When the furnace wall temperature is kept constant, the temperature of several wafers at both ends of the wafer row is low, but the temperature distribution of the furnace wall divided into three zones is TF < 1) and T, (2). When the temperature is increased, the distribution of wafers in the furnace axis direction becomes uniform.

〔発明の効果〕〔Effect of the invention〕

本発明によれば、ウェハ温度が低い、つまり酸化膜厚が
薄いウェハ列両端の数枚の不良ウェハを減少させること
ができ、しかも均一性を向上できるので、大規模集積回
路の生産性向上、;5品質化の効果がある。
According to the present invention, it is possible to reduce the number of defective wafers at both ends of the wafer row where the wafer temperature is low, that is, the oxide film thickness is thin, and the uniformity can be improved, thereby improving the productivity of large-scale integrated circuits. ;5 It has the effect of improving quality.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の一実施例である酸化・拡散装置の構成
図、第2図は酸化膜厚均一化制御方式のアルゴリズムを
示す図、第3図はウェハ@度分布を表わす温度分布図で
ある。 101・・・酸化・拡散炉、102・・・ウェハ、10
3゜104.105・・・ヒータ、107・・・コント
ローラ。 語1図
Fig. 1 is a block diagram of an oxidation/diffusion device that is an embodiment of the present invention, Fig. 2 is a diagram showing the algorithm of the oxide film thickness uniformity control method, and Fig. 3 is a temperature distribution diagram showing the wafer @ temperature distribution. It is. 101... Oxidation/diffusion furnace, 102... Wafer, 10
3゜104.105...Heater, 107...Controller. word 1 diagram

Claims (1)

【特許請求の範囲】[Claims] 半導体製造プロセスの酸化あるいは拡散工程で用いられ
る炉における多数のウェハの目標値追値制御方式におい
て、加熱炉の炉壁を炉軸方向にゾーン分割し、該炉壁の
温度により上記のウェハの炉軸方向温度分布を推定する
非線型分布系モデル方程式、ウェハ温度から酸化膜厚を
推定する非線型モデル及び、該推定値と目標値との差を
評価値とする評価関数に基づき、この評価関数が最小と
なるように炉壁温度を決定することを特徴とする半導体
製造炉内の酸化膜厚分布均一化制御方式。
In a target value follow-up control system for a large number of wafers in a furnace used in the oxidation or diffusion process of a semiconductor manufacturing process, the furnace wall of the heating furnace is divided into zones in the furnace axis direction, and the temperature of the furnace wall is adjusted to control the number of wafers in the furnace. This evaluation function is based on a nonlinear distribution model equation that estimates the axial temperature distribution, a nonlinear model that estimates the oxide film thickness from the wafer temperature, and an evaluation function that uses the difference between the estimated value and the target value as the evaluation value. A control method for uniformizing oxide film thickness distribution in a semiconductor manufacturing furnace, characterized by determining the furnace wall temperature so that the temperature is minimized.
JP59184617A 1984-09-05 1984-09-05 Controlling system for uniform thickness of oxide film in semiconductor manufacturing furnace Pending JPS6163034A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP59184617A JPS6163034A (en) 1984-09-05 1984-09-05 Controlling system for uniform thickness of oxide film in semiconductor manufacturing furnace

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59184617A JPS6163034A (en) 1984-09-05 1984-09-05 Controlling system for uniform thickness of oxide film in semiconductor manufacturing furnace

Publications (1)

Publication Number Publication Date
JPS6163034A true JPS6163034A (en) 1986-04-01

Family

ID=16156358

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59184617A Pending JPS6163034A (en) 1984-09-05 1984-09-05 Controlling system for uniform thickness of oxide film in semiconductor manufacturing furnace

Country Status (1)

Country Link
JP (1) JPS6163034A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62147336U (en) * 1986-02-27 1987-09-17
US6730885B2 (en) 2000-07-06 2004-05-04 Tokyo Electron Limited Batch type heat treatment system, method for controlling same, and heat treatment method
JP2017005106A (en) * 2015-06-10 2017-01-05 東京エレクトロン株式会社 Thermal treatment apparatus, adjustment method for thermal treatment apparatus, and program

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62147336U (en) * 1986-02-27 1987-09-17
US6730885B2 (en) 2000-07-06 2004-05-04 Tokyo Electron Limited Batch type heat treatment system, method for controlling same, and heat treatment method
JP2017005106A (en) * 2015-06-10 2017-01-05 東京エレクトロン株式会社 Thermal treatment apparatus, adjustment method for thermal treatment apparatus, and program

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