JPS6162932A - Floating point arithmetic unit - Google Patents

Abstract

PURPOSE:To use input data without converting a large amount of data in exponential part fixed-length expression to variable length expression by using exponential part fixed length and exponential part variable length properly in floating point expression. CONSTITUTION:When the value (e) in an exponential part register 13 is within a range of -256<=e<=248, it is discriminated that the variable length expression is used in the arithmetic result and when not, it is decided that the fixed length expression is used. When the variable length expression is employed, the contents of the mantissa part register 12 are transferred to a floating point register 11. The sign bit 24 of a register 13 is inputted to the input 50 of a two-input logical circuit 16, the sign bit 22 of the register 12 is inputted to the input 51, and the output of the logical circuit 16 is inputted to a flip-flop 15. When the fixed-length expression is used, the sign bit 22 of the register 12 is used as a supply bit to shift the contents of the register 12 to right once and those of the register 14 to left once. Then, the value of the register 12 is transferred to a register 11.

Description

[Detailed Description of the Invention] [Field of Application of the Invention] The present invention relates to a floating-point number arithmetic device, and in particular to a floating-point number arithmetic device that can operate on numerical data in a fixed-length exponent representation format and a variable-length exponent representation format. This relates to arithmetic processing devices.

[Background of the invention]

Conventionally, as a discrete representation of continuous numerical data, a floating point representation with a fixed exponent part has been adopted in many electronic subtraction machines and is generally widely used.

This representation method is easy to handle because the exponent part is a fixed length, but it cannot represent numbers with extremely large or small absolute values, and the range of data that can be represented may be insufficient depending on the application. There was a drawback that it was not. Exponent variable length fJ
,! The PIJ decimal point representation format is JP-A-58-11482.
As stated in Publication No. 8 (it can represent a wider range of data than the two-finger fixed-length representation, and has a sufficient expressible range for actual applications. However, the exponent part variable-length floating point , since there is almost no commonality between the conventional fixed-length exponent representation and format -F, there is a problem that data stored in the conventional fixed-length exponent representation cannot be used unless it is converted to a variable-length exponent. was there.

[Purpose of the invention]

The purpose of the present invention is to improve the conventional drawbacks such as '), maintain the expression format of the conventional fixed-length exponent floating-point representation system, and expand the range of data that can be expressed using variable-length floating-point exponent. An object of the present invention is to provide a floating point arithmetic device using a floating point representation method that can be extended to a range equivalent to that of a decimal point representation method.

[Summary of the invention]

In order to achieve the objective 1-Note 1, the present invention provides a means for determining whether input data is a fixed-length exponent part expression or a variable-length exponent part expression, depending on the data range, The present invention is characterized in that it is provided with a means for calculating the manual data and determining whether the calculation result is in the range of the fixed exponent part 131 or the range of the variable length expression of the exponent part.

[Embodiments of the invention]

Hereinafter, embodiments of the present invention will be described with reference to the drawings.

First, the exponent part fixed-length floating point representation method (hereinafter referred to as "fixed-length representation", "fixed-length representation method") used in the arithmetic device of the present invention
It is called as. ) and exponent variable length floating point representation method (
Hereinafter, this will be referred to as "variable length representation" and "variable length representation method." ) will be explained in detail.

FIG. 2 is a diagram showing a fixed length representation used in this embodiment.

In Fig. 2, ] is 1 bit of code information of numerical data, 2 is the exponent value consisting of 7 bits 1-, 3 is the mantissa part, and 4 is the exponent part 2 and mantissa part 3. It is a boundary. In the fixed length representation, the boundary 4 is fixed.

Assume that a number X is expressed by an exponent e and a mantissa m as follows.

x=m·168 (1) where e is an integer and 1ml<1.

At this time, one bit of code information is 0 if m ) O.
, if m<O, it is set to 1. 7 bits 1- of the exponent part are e+6
This is the binary representation of 4. The mantissa is 16 for 1ml.
When expressed as a base number, the necessary length is extracted after the decimal point, and the number after the lowest value is rounded down or rounded down to the nearest 8.

The key point of the variable length representation system used in this embodiment is that the length of the exponent part is determined by the It_OIt sequence or the 1'' sequence preceding the exponent part, and is defined as follows.

(i) This variable length representation can represent the number O and infinity as follows.

0 is "OOO...0"...(2) Infinity is "100...0"...(3) Below,
Let's talk about other numbers.

(i]) Assume that a number X is expressed by an exponent e and a mantissa m as follows.

x = rn-2+ (4)
Here, e is an integer, and m is defined as follows according to the sign of X. m is also defined as follows.

a) When x>O, 1<, m<2. m=m-1...(5) b) When x<O, -2<m<-, 1, m=m+2...(6) Furthermore, beans are defined as follows.

) When e-en-, e = e + 1. −(
7) d) When e<O, then -=-e... (8) Furthermore,
n is defined as follows.

r+=[Qo g2e]+1--(9) However, the symbol [] is a Gauss symbol, and [X] represents the largest integer not exceeding X.

(jii) The bit arrangement of this variable length representation is basically the same as the arrangement shown in FIG. However, the length of the exponent part is variable and is 2n pi 1-.

(~) Bit 1 of code information is O when x > O, x <
It is 1 when it is 0 (same as fixed length expression).

(v) The exponent part is defined as follows.

a) The left n bits are the column of tr1r+.

b) The right n bits are a bit string of length n obtained by binary expansion of 7, with the left end changed to "0".

C) However, when X <-1 or O < x < 1, it is the one's complement of what is determined by c) and d) above.

(vi) The mantissa is defined as follows.

The binary expanded form of m is 0, b, b2b3・= −(10)
In this case, the length of the bit string "b, b2b3, . . . " is as long as necessary from the left.

The above definition uniquely determines the number represented by any bit string.

Next, the range of use of fixed-length representation and variable-length representation in the floating-point representation of data used in this embodiment is defined as follows. Assuming that the data to be expressed is X, (i) Infinity: variable length expression (i
i) x <--2"8: Variable length expression (jii) -22
411<x<-2-”': Fixed length expression Nv)
-2-"'< x <2-"': variable length expression (v)2-'! i'<x<2248. Fixed length representation (vi) 224″<x H
Variable length representation This rule means that when data is represented in variable length, the left 7 bits of the exponent part are all “0” or all 11.
It can also be interpreted as using fixed-length representation only for data that does not become 1 ++. Hereinafter, the floating point representation method according to the above usage will be abbreviated as the present representation method.

FIG. 1 is a block diagram showing the main parts of a floating point arithmetic device according to an embodiment of the present invention.

In FIG. 1, 11 is a floating point register, 12 is a mantissa register, 13 is an exponent register, 14 is a counter, 15 is a flip-flop, 16 is two human logic circuits,
17 is an index conversion circuit, and 25 is an inverter.

Floating point number register] The length of 1 is K + 1 bits. The shift register to the right, except for the sign bit 20, is a shift register that has the following functions.

(1, -1) Shifts to the left by 1 bit each time the left cyst l-rigger 31 is applied.

(1-2) Each time the right shift trigger 32 is applied, the right shift is performed by 1 bit.

(1-3) Transfer the value to the mantissa register 12.

(], -4) The value is decreased by 1 by the value decrease trigger 33.

(1-5) The complement trigger 34 inverts the values tIO11 and 111++ of each bit simultaneously.

The mantissa register 12 is a shift register having a length of 1 to 1, and has the following functions.

(1, -6) Each time the left shift 1- trigger 35 is applied, the bit is shifted to the left by one bit.

(1, -7') Each time the right shift trigger 36 is applied, the bit is shifted to the right by one bit.

(1, -8) Transfers the value to the floating point register 11.

(1-9) Decrease the value by 1 using the value decrease trigger 37.

(1, -10) Complement trigger 38 causes each pill to be triggered simultaneously.
Invert the values of ``O'' and ``1''.

The exponent register 13 is a register having bits in length, and has the following functions.

(1, -11) Each time the left shift trigger 39 is applied, one bit is shifted to the left.

(1-1,2) Each time the right shift trigger 40 is applied, the bit is shifted to the right by one bit.

(1-13) The value is increased by 1 by the value increase trigger 41-.

(1-14) The value is decreased by 1 by the value decrease trigger 42.

(1-15) The complement trigger 43 simultaneously inverts the seeds of each pit to "O" and "1'" (1-16) It is detected that all pits 1 are rr O++.

(1, -17) The value decrease trigger 44 decreases the value by 64.

(1-18) Detect whether the value (e) is within the range of -256<e<248.

When each of the shift transistors shifts 1~, unless otherwise specified, the overflowing P1-Q) information is lost, and the P1~ to be supplied is llO++.

The two-person logic circuit 16 generates an output as shown in FIG. 3 according to the values of inputs 50 and 5.

The exponent conversion circuit 17 has the following functions.

(1-19) Data value (e) in exponent register 1;3
Using, e' = C(e+3)/'1]-1-64...(
11) n = (e' -64) X 4-
e...(12) is calculated, the value e' is output to the exponent register 13, and a right shift trigger 32 is given to the n-times floating point register 11. However, [ ] is a Gauss symbol.

The operation of the apparatus of this embodiment having the above-mentioned configuration will be explained below.

Data calculations using this representation method are performed in the following steps.

(1) Counting the column of “0” or 111 II (2) Separating the exponent part and mantissa part () In the case of addition and subtraction, adjusting the value of the exponent part (4) Calculation (5) Normalization (6) Exponent part and the combination of the mantissa (7) How to insert the "O" or II II column, each of the above steps will be explained in detail.

m “O” or LL 1-II row count (a
) Set the value of counter 14 to 0. The values of the first bits 1 to 21 excluding the sign bit 2o of the floating point register] are set to 5.

(b) The first bit 21 of the floating point number register 11
into the input 50 of the logic circuit 16.

The value of the flip-flop 15 is input to the input 5 of the logic circuit 16.
Put it in. The counter 14 calculates the output (“1”) of the logic circuit 16 at this time. Using the first bit 21 of the floating point register 11 as the supply bit, the exponent register 13 is shifted to the left by the function (]---11,).

(c) The output of the logic circuit 16 is “0” in the next step (d).
”, and count the number of times with the counter 14.

(d) Floating point number register 11 is set to the above function (1-1)
Shift left by 1-. The value newly left-shifted to the first bit 21 is input to the input 50 of the logic circuit 16. Furthermore, using this first bit 21 as a supply bit, the exponent register 13 is shifted to the left by the function (1-11). The value of the flip-flop 15 is input to the input 5 of the logic circuit 16.
Put it in 1.

(2) Separation of exponent and mantissa parts (a) Counter] When the value of 4 is 7 or more, the value of floating point number 1 no register 11 is determined to be a variable length expression, and the next (b)
) to (, ]), and if the value of the counter 14 is less than 7, it is determined that it is a fixed length expression, and the next (10 to (r)
Process.

(b) -1 - Invert the value of the first bit 21 of the floating point register 11 resulting from step (1).

([,) Set the exponent part register 13 to "0".

(d) The first bit 21 of the floating point number register 11
The value of logical times i! 816 input 50. The value of flip-flop 15 is applied to input 51 of logic circuit 16. The value of the counter 14 is decremented by 1, and the output of the logic circuit 16 at this time is used as the supply bit, and the function (1-1
1), the exponent register 13 is shifted to the left.

(c) Next steps (f) and (g) are repeated while decrementing the value of the counter 14 by 1 until it becomes 0.

(f) Floating point register] 1 to the above function (1=1)
Shift to the left. The value newly shifted to the left by 1 to the []th bit 21 is input to the input 50 of the logic circuit 16. The value of flip-flop 15 is applied to input 51 of logic circuit 16.

(g) Using the output of the logic circuit 16 as the supply bit, shift the exponent register 13 to the left using the function (1-1, 1).

(h) When the value of the counter 14 becomes 0, the value of the exponent part register 13 is set to 1 by the function (1-14).
Reduce.

(i) Input the sign bit 2o and the value of the flip-flop 15 to the logic circuit 16, and if the output value tL i II is obtained, take the complement according to the function (1-15).

(j) Transfer the value of the floating point number 1 register 11 to the mantissa register 12 by the function (1, -3). Additionally, the value of sign bit 2o is also transferred to sign bit 22 of mantissa register 12, and the value of sign bit 20 is transferred to inverter 2.
The value inverted by 5 is transferred to the bit to the left of the decimal point position 23 of the mantissa register 12.

(k) Increase the value of the counter by 1 until the value of the counter 14 reaches 7, perform the next process (Q), and
Repeat the operation of checking the value of .

(Q) Floating point number register 11 is set to the above function (1-1)
Shift to the left. The value newly left-shifted to the first bit 21 is used as the supply bit, and the exponent register 13
is shifted to the left by the function (1-11).

(m) Exponent register 1 according to the function (1, -17)
The value obtained by subtracting 64 from the value in 3 is set in the exponent register 13.

(n) Exponent register] The value is multiplied by 4 by shifting 3 to the left twice using the function (1-11).

(0) Mantissa register 12 according to the function (1, -3)
The value of floating point register 11 is transferred to.

(p) Mantissa register 12 according to the function (1, -9)
Decrease the value of by 1.

(q) Take the complement according to the function (1-10).

(r) Transfer the value of sign bit 20 to sign bit 22 of mantissa register 12 and the pit to the left of decimal point position 23.

In this state, the value of e when the data is expressed in the m·2' format is stored in the exponent register 13 (negative numbers are integers that are two's complements), and the value of m is ( Negative numbers are stored in the mantissa register 12 (as decimal numbers that are two's complements).

Steps (3), (4), and (5) are the steps performed for the conventional exponent fixed-length floating point representation, so the explanation will be omitted and the explanation will proceed to step (6).

(6) Combining the exponent part and the mantissa part (a) The exponent part register 13 by the function (1-18)
When the value (e) in is outside the range of -256<e<248, it is determined that the calculation result uses variable length representation, and the following processes (b) to (g) are performed to ensure that -256<e < 2
If it is within the range of 48, it is determined that the fixed length representation is used for the calculation result, and the following processes (h) to (k) are performed.

(b) Transfer the contents from the mantissa register 12 to the floating point register 11 using the function (1-8).

(c) The sign bit 24 of the exponent register 13 is input to the input 50 of the logic circuit 16, the sign bit 22 of the mantissa register 12 is input to the input 51, and the output is input to the flip-flop 15.

(d) When the value of the sign bit 24 is “1”, the function (
], −15) to obtain the complement of the exponent register 13.

(e) Exponent register 13 according to the function (1-13)
Increase the value of by 1. Set the value of the counter 14 to O.

(f) While incrementing the value of the counter 14, the exponent register 1 is
Repeat until the value of 3 becomes O.

(g) Set the exponent register 13 to the above function (1, -1, 2)
Shift the overflow bit by 1 bit to the right by inputting the overflow bit to the input 50 of the logic circuit 16, inputting the value of the flip-flop 15 to the input 51 of the logic circuit 16, and transmitting the output to the floating point register '11 to the function described above. When shifting one bit to the right by (1-2), it is used as a bit supplied from the left end.

(h) Using code bits 1 to 22 of the mantissa register 12 as supply bits, the mantissa register 12 is shifted to the right once by the function (1-7). In addition, the above function (]--11
, ), the exponent part register 13 is shifted to the left once.

(i) Transfer the value of the mantissa register 12 by the function (1-8) to the floating point register 1]. Further, the value of the sign bit 22 is also transferred as is to the sign bit 2° of the floating point number register 11.

(j) Exponent conversion circuit of the function (1-1, 9)] By driving 7, the value of the exponent part register 13 is converted, and the value of the floating point register 11 is converted by 1 to RIGA 32 generated by the exponent part conversion circuit 17. shift to the right.

(k) When the exponent register 13 is shifted to the right using the function (1, -1, 2), the overflowing bit is shifted to the left end when the floating point register 11 is shifted to the right using the function (1'-2). Used as bits supplied from Repeat this operation 7 times.

(7) Inserting a column of “0” or “1” (a) Procedure (6
) Only when it is determined in step (a) that the calculation result is expressed in variable length, the following processes (b) to (d) are performed.

(b) Invert the value of the first bit 21 of the floating point number register 11.

(c) Value of the counter 14 (step (6)
Perform the next step (d) by f)).

(d) Using the value of the flip-flop 15 as the supplied bit, the contents of the exponent register 13 are shifted to the right by one bit by the function (1-8).

Due to the effects described above, the floating point arithmetic device of the present invention uses a conventional arithmetic device to perform calculations on data expressed in an expression format that uses fixed-length exponent part expression and variable-length exponent part expression depending on the data range. This makes it possible to put it into practical use.

It goes without saying that each component of the above embodiment can be replaced with other specific means having substantially equivalent functions.

[Effects of the Invention] As explained above, according to the present invention, the present arithmetic device has the following effects:
Depending on the data range, it is possible to use either fixed-length floating-point exponent representation or variable-length exponent floating-point representation, so large amounts of accumulated data that is conventionally expressed as fixed-length floating-point exponent parts can be converted into variable-length floating-point exponent representations. It can be used as input data without converting it into a representation, and can also be represented using the exponent variable length representation method, which can represent extremely large numbers and small numbers at the other end.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the main parts of a floating-point arithmetic device according to an embodiment of the present invention, FIG. 2 is a diagram showing the fixed-length floating-point representation of the exponent part, and FIG. 3 is the logic circuit of FIG. 1. FIG.

Claims (1)

[Claims] In a floating point arithmetic device, a means for determining whether input data is a fixed-length exponent part representation or a variable-length exponent part representation according to a data range, and calculating the input data determined by the determining means, 1. A floating-point arithmetic device comprising means for determining whether a result is in a range of fixed exponent length representation or a range of variable exponent length representation.