JPS6162880A - Performance test of printed circuit board - Google Patents

Performance test of printed circuit board

Info

Publication number
JPS6162880A
JPS6162880A JP59185821A JP18582184A JPS6162880A JP S6162880 A JPS6162880 A JP S6162880A JP 59185821 A JP59185821 A JP 59185821A JP 18582184 A JP18582184 A JP 18582184A JP S6162880 A JPS6162880 A JP S6162880A
Authority
JP
Japan
Prior art keywords
test
test program
printed circuit
memory
circuit board
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP59185821A
Other languages
Japanese (ja)
Inventor
Koji Kamimura
上村　孝二
Hirobumi Kawaguchi
博文 川口
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP59185821A priority Critical patent/JPS6162880A/en
Publication of JPS6162880A publication Critical patent/JPS6162880A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
    • G06F11/26—Functional testing
    • G06F11/273—Tester hardware, i.e. output processing circuits
    • G06F11/2733—Test interface between tester and unit under test
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
    • G06F11/26—Functional testing
    • G06F11/263—Generation of test inputs, e.g. test vectors, patterns or sequences ; with adaptation of the tested hardware for testability with external testers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/36—Data generation devices, e.g. data inverters

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Quality & Reliability (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Test And Diagnosis Of Digital Computers (AREA)

Abstract

PURPOSE:To reduce the testing time, by memorizing a test program into a memory of a substrate to be tested in testing. CONSTITUTION:A memory 3' for memorizing test programs is provided on a substrate to be tested. A test program stored into a floppy disc 7 on a data from an input unit 1 is memorized into a memory 3 temporarily as specified by a CPU 2 and sent to an I/O port 4' through an I/O port 4 and an input/output data line 8'. Then, a direction is provided to the CPU2' to memorize the test program into the memory 3'. Then, as specified by the CPU2', the test program memorized is used to check the operation of the substrate being tested.

Description

【発明の詳細な説明】 産業上の利用分野 本発明ｄ［、例えば溶接用ロボット等のようにキー操作
に基づいて一連の処理動作を遂行するプリント基板の動
作試験装置（以下、試験装置と称する）における動作ル
（験力法に関し、ＭＰ：製品状態のプリンｉ・基板（以
下、基板と称する）について試験時間の短縮ど精度の必
要な微小値の調整を容易に実現するものである。DETAILED DESCRIPTION OF THE INVENTION Industrial Field of Application The present invention relates to a printed circuit board operation testing device (hereinafter referred to as a testing device) that performs a series of processing operations based on key operations, such as a welding robot, etc. Regarding the mechanical force method (MP), it is possible to shorten test time and easily adjust minute values that require precision for printed circuit boards (hereinafter referred to as substrates) in the product state.

従来例の構成とその問題点 例えば、溶接用ロボット等を制御する基板の動作が正常
に行なわれるかどうか自動的に試験する場合、試験装置
と被試験基板をケーブルで接続し試験装置にあるテスト
パターンにより、試験基板の動作状態を電気的に検出し
てチェックし、精度の必要な微小値の調整には特別の精
度の高い６１１ｊ定装置を使用しているのが１般的であ
る。ところかこのように試験装置にテストパターンをも
つと、その都度テストパターンを被試験基板に送り試験
するために試験時間が長くかかってし−まう。又、精度
の必要な微小値の調整に精度の高い測定装置を使うこと
によるコストパーフォーマンスが問題になる。Conventional configuration and its problems For example, when automatically testing whether a board that controls a welding robot, etc. operates normally, the test equipment and the board under test are connected with a cable and the test equipment is connected to the test equipment. Generally, the operational state of the test board is electrically detected and checked based on the pattern, and a special highly accurate 611j measuring device is used to adjust minute values that require precision. However, if the test equipment has test patterns in this way, the test pattern will be sent to the board under test each time and the test will take a long time. Furthermore, cost performance is a problem when using a highly accurate measuring device for adjusting minute values that require accuracy.

第１図は従来の被試験基板と試験装置との試験動作部を
示すブロック図である。第１図について説明すると、１
はどのテスト項目を実行させるのか選択するだめの入力
装置、２は中央演算処理装置面゛（」ン、ト、ＣＰＵと
称する）、３はメモリ装置、４は被試験基（ルとの通栖
用Ｉ／Ｏポー１・装置、５はテスト結果及び誘導メソセ
ージ等の表示を行なう表示装置、６（ｌ、微小値の測定
装置でいず扛も試験装置に１・１属するものである。次
に被試験基板上にツイテ、２／　ｉ、−ｌ、ＣＰＵ、４
’は■／Ｏボー１・装置、８′は人出力データ線である
。以下２″、４″は２／　、　４／と同じで被試験基板
の数たけ存在するが、２／　、　４／を例にｄ）ａ明し
ていく。FIG. 1 is a block diagram showing a test operation section of a conventional board under test and a test device. To explain Figure 1, 1
is an input device for selecting which test item to execute, 2 is a central processing unit (referred to as CPU), 3 is a memory device, and 4 is a communication device with I/O port 1/equipment, 5 is a display device for displaying test results and guidance messages, etc., 6(l) is a micro value measuring device and belongs to the testing equipment.Next Tweet on the board under test, 2/i, -l, CPU, 4
' is the ■/O baud 1/device, and 8' is the human output data line. Below, 2'' and 4'' are the same as 2/ and 4/, and there are as many test boards as there are, but d) and a will be explained using 2/ and 4/ as examples.

従来、３のメモリ装置にあったテストパターン台・次々
と４のＩ／Ｏボートから８′の入出力データ線を通り４
′の１．／Ｏボートを介して、２のＣＰＵへ指示をＩＵ
え、被試験基板の動作チェックを行ない、その結果を４
′のＩ／Ｏポートから８′の入出力データ線を通り４の
Ｉ／Ｏボートを介して、２のＣＰＵに結果を知らせ、５
の表示装置を通して試験結果や調整指示等の表示を行な
っていた。この場合、試験時間に多大の時間を要した。Conventionally, the test pattern stand that was used in 3 memory devices.
'1. /IU sends instructions to CPU 2 via O boat
Well, check the operation of the board under test and report the results in 4.
The result is sent from the I/O port of ' through the input/output data line of 8' to the CPU of 2 via the I/O port of 4.
Test results, adjustment instructions, etc. were displayed through the display device. In this case, a large amount of time was required for the test.

このため、例えば多鼠生だ−の基板においては、そのチ
ェックのために時間がかかりすぎると製品コスＩ・にも
影響が出てくる。又、精度を必要とする微小値の調整に
対する負担も犬である。For this reason, for example, in the case of multi-layered boards, if it takes too much time to check, the product cost will also be affected. Furthermore, the burden of adjusting minute values that require precision is also significant.

発明の目的 本発明は、このような問題点を解消することを目的とす
るものである。OBJECT OF THE INVENTION The present invention aims to solve these problems.

発明の構成 このだめに本発明は被試験基板のハードウェア構成に着
目し、試験をする際にテストプログラムを試験装置から
被試験基板のメモリ装置に記憶させ、試験装置からは開
始信号を与えるだけで自動的に試験を行なうようにして
同一の動作試験において試験時間の短縮をはかり又、精
度を必要とする微小値の調整にはテストプログラムによ
り増巾できる範囲内で、調整が容易にできる値に変換し
て、特別な精度の高い測定装置を用いることなく調整が
できる装置を提供するととを目的としている。Structure of the Invention To this end, the present invention focuses on the hardware configuration of the board under test, and when testing, the test program is stored from the test equipment in the memory device of the board under test, and the test equipment only provides a start signal. We aim to shorten the test time in the same operation test by automatically performing tests with The purpose of the present invention is to provide a device that allows adjustment without using a special high-precision measuring device.

実施例の説明 以下、本発明の試験装置について第２図を用いて計則に
ｒｉｆｔ、　’Ｊ１する。第２図ｄ、本発明の一実施例
である被試験基板と試験装置との試験動作ｇＢを示すブ
ロック図である。第２図において１〜５．２’。DESCRIPTION OF EMBODIMENTS Hereinafter, the test apparatus of the present invention will be rifted and 'J1' using FIG. FIG. 2d is a block diagram showing a test operation gB of a board under test and a test device according to an embodiment of the present invention. 1 to 5.2' in Figure 2.

４’　、　６’については第１図に説明したものと同一
である。３′は被試験基板」二のメモリ装置でテストプ
ロゲラｌ、の記憶に使っている。７はフロノビーデ、ｆ
スフ装置で、被試験基板に記憶させるためのテストプロ
グラムを格納している。4' and 6' are the same as those explained in FIG. 3' is a memory device of the board to be tested, which is used for memory of the test programmer l. 7 is Fronobide, f
This is a standard device that stores a test program to be stored on the board under test.

次に、本発明の装置の動作について説明する０第２図に
おいで、入力装置１からの入カテータによりフロッピー
ディスク装置７に格納されているテストプログラムをＣ
ＰＵ２の指示によりいったんメモリ装置３に記憶し、そ
こからＩ／Ｏボート４と８′の入出力データ線を通して
Ｉ／Ｏボート４′に送ら扛る。ぞ１〜てＣＰＵ２′に指
示を与え被試験基板−１−のメ七り装置３′にテストプ
ログラムを記憶させる。ＣＰＵ２によりテストフログラ
ムがメモリ装置３′に格納されたことを判断し、ＣＰ　
Ｕ　２’に指示を与えＣＰ　Ｕ　２’によりメモリ装置
３′内のテストプログラムに」：り被試験基板の動作チ
ェックが行なわれる。又、精度の必要な微小値の調整時
はテストプログラムによりＣＰ　Ｕ　２’で増巾させ精
度を向上させ調整を容易にしている。試験結果等はｃｐ
Ｕ　２’カら工／Ｏポー１・４′を通してＩ／Ｏポート
４に送られＣＰＵ２により表示装置５に送られ表示され
る。従来と本発明のフローチャートを第３図、第４図に
示す。Next, in FIG. 2, which explains the operation of the apparatus of the present invention, the test program stored in the floppy disk device 7 is inputted into the C.
The data is temporarily stored in the memory device 3 according to instructions from the PU 2, and sent from there to the I/O boat 4' through the input/output data lines of the I/O boats 4 and 8'. At step 1, an instruction is given to the CPU 2' to store the test program in the memory device 3' of the board under test -1-. The CPU 2 determines that the test program has been stored in the memory device 3', and the CPU 2 determines that the test program is stored in the memory device 3'.
An instruction is given to the CPU 2', and the CPU 2' executes a test program in the memory device 3' to check the operation of the board under test. Further, when adjusting minute values that require precision, the test program is used to increase the amplitude in the CPU 2' to improve precision and facilitate adjustment. Test results etc. are CP
The signal is sent from the U2' to the I/O port 4 through the I/O port 1 and 4', and sent to the display device 5 by the CPU 2 for display. Flowcharts of the conventional method and the present invention are shown in FIGS. 3 and 4.

発明の効果 以上の説明から明らかなようにテストプログラムを被試
験基板」二のメモリ装置に記憶させることにより基板の
動作試験時間の短縮がはかれ、テストプログラムによる
増ｌ］で精度を必要とする微小値の調整を容易にするこ
とが実現でき、全体的に特別のハードウェア構成を追加
することなく基板の動作試験が短縮でき、かつ精度の必
要な微小値の調整もできて実用」二の利点が多大である
。Effects of the Invention As is clear from the above explanation, by storing the test program in the memory device of the board under test, the time required to test the operation of the board can be shortened, and the test program increases accuracy. This makes it possible to easily adjust minute values, shorten board operation tests without adding any special hardware configuration, and make it practical as it also allows adjustment of minute values that require precision. The benefits are enormous.

【図面の簡単な説明】[Brief explanation of drawings]

第１．図は従来の試験装置と被試験基板との試験動作部
を示すブロック図、第２図は本発明による試験装置と被
試験基板との試験動作部を示すブロツク１シ１、第３図
は従来方法のフローチャート図、第４図は本発明の一実
施例のフローチャー１・図である。 １・　入力装置、２　　・ＣＰＵ、３　・・・メモリ装
置、４−−　Ｉ　／　Ｏボート装置、５・−表示装置、
６−　微小値乙用定装置、７・・・フロッピーディスク
装置、２′　・ＣＰＵ、３′　・・メモリ装置、４′・
・・Ｉ／Ｏボート装置、８′・・・・・・入出力データ
線である。 代即人の氏名　弁理士　中　尾　敏　男　ほか１名第１
図 ？８ＷＩ昭６ｌ−６２８８０（４） 第４図 ｒ￥六〇〜 ］二ミ４ノ１ノ ９　　　テスト琴ｌ右 テスへブでゲラへΣ 秘しとり メモリに〔１１３ 名り橋 ｐηう乍　試１験 ７°υゲラ４＋＜エリ　　　　　　　９１克ｒｙ３　Ｘ
う′！Ｌ）大ご〈 うｖ１定兼界 ！３ ■■苓１1st. The figure is a block diagram showing a test operation section between a conventional test device and a board under test, FIG. 2 is a block diagram showing a test operation section between a test device according to the present invention and a board under test, and FIG. Flowchart diagram of the method, FIG. 4 is a flowchart diagram 1 of an embodiment of the present invention. 1. Input device, 2. CPU, 3. Memory device, 4. I/O boat device, 5. Display device.
6- Setting device for minute value B, 7... Floppy disk device, 2' CPU, 3' Memory device, 4'
. . . I/O boat device, 8' . . . Input/output data line. Name of representative Patent attorney Toshio Nakao and 1 other person 1st
figure? 8WI Showa 6l-62880 (4) Figure 4 r ￥60~ ] Nimi 4 no 1 no 9 Test koto l Right Teshebu to galley Σ In secret memory [113 Narigashi pη U乍 Exam 1 7°υ Galley 4 + < Eli 91kry3 X
cormorant'! L) Daigo〈Uv1 Sadakanekai! 3 ■■ Rei 1

Claims (1)

【特許請求の範囲】[Claims] 入力装置、入出力データバス、中央演算装置、メモリ装
置、Ｉ／Ｏポート装置、表示装置から成るプリント基板
の動作試験装置を作用し、動作試験用テストプログラム
をプリント基板試験装置から被試験基板上のメモリ装置
に記憶させると共に、被試験基板上でテストプログラム
を走らせると共に、微小値をテストプログラムにより増
巾させるプリント基板の動作試験方法。A printed circuit board operation test device consisting of an input device, an input/output data bus, a central processing unit, a memory device, an I/O port device, and a display device is activated, and a test program for operation testing is transferred from the printed circuit board test device to the board under test. A method for testing the operation of a printed circuit board, in which a test program is stored in a memory device, a test program is run on the board under test, and minute values are amplified by the test program.
JP59185821A 1984-09-05 1984-09-05 Performance test of printed circuit board Pending JPS6162880A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP59185821A JPS6162880A (en) 1984-09-05 1984-09-05 Performance test of printed circuit board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59185821A JPS6162880A (en) 1984-09-05 1984-09-05 Performance test of printed circuit board

Publications (1)

Publication Number Publication Date
JPS6162880A true JPS6162880A (en) 1986-03-31

Family

ID=16177466

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59185821A Pending JPS6162880A (en) 1984-09-05 1984-09-05 Performance test of printed circuit board

Country Status (1)

Country Link
JP (1) JPS6162880A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62245341A (en) * 1986-04-16 1987-10-26 Fuji Heavy Ind Ltd Engine control device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62245341A (en) * 1986-04-16 1987-10-26 Fuji Heavy Ind Ltd Engine control device

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