JPS6162267A - Receiving system of serial data - Google Patents

Abstract

PURPOSE:To correct out of synchronism between received clock and received data quickly, and enable to receive data correctly at the time of receiving next data by taking synchronism of received clock and received data again after receiving serial data. CONSTITUTION:When received clock 1-2 arrives in excess by one clock due to noise etc., while receiving b2 of received serial data 1-1, a carrier signal is outputted from a counter 42 of a point B, that is, the 7th pulse of normal received clock, and data of a serial/parallel converting circuit 3 at this time are latched by a register 41. As control section 5 outputs clock 12 from a clock pulse generator 12 successively after input of error data. In this case, a counter 42 outputs a carry signal when one clock is inputted from normal received clock 2 to the counter 42, and clock signals for 7 pulses from the generator 12 are inputted to the counter 42. as the value of the register 42 at this time is neglected, data sent in following the data at point B inputted by mistake are received correctly.

Description

[Detailed Description of the Invention] [Technical Field] The present invention relates to a serial data reception method, and in particular to an apparatus that receives serial data in synchronization with simultaneously sent reception clocks and converts the received serial data into parallel data for processing. This relates to a serial data reception method.

[Prior Art] Conventionally, in data transfer between a host side and a terminal side, for example, a printer device, the status of the printer is sent to the host side (hereinafter referred to as a controller), and instructions and data are sent from the controller to the printer side. When sending data, convert it to serial data and use one bidirectional signal line for both sending and receiving, or one tree for each signal line for sending and receiving, and one tree for clock lines for converting serial data into parallel data. and exchanged data.

In this case, eight clocks are required for converting serial data into parallel data for 8-bit data, and 16 clocks for 16-bit data. This clock is often sent from the outside (second controller side) via an interface signal line, and noise may enter the signal line and the number of clocks may increase. Therefore, it is difficult to convert serial data to parallel data. For example, if the received data is 8 bits and 9 pulses are sent, not only will the received data be erroneous data, but it will also be incorrectly converted into 8 bits. Even if pulses are sent, it is determined that the next data is being received at the point where 7 pulses have reached the 2nd speed, and in the end, 7 pulses are used for the current data, and the received data is shifted 1 bit at a time. It was taken in as such. In this way, once the clock and data are out of synchronization, there is a drawback that all subsequent data cannot be received correctly.

[Objective] The present invention was made in view of the above-mentioned drawbacks of the prior art, and
It is an object of the present invention to propose a serial data reception method that can immediately correct synchronization deviation between received serial data and the reception timing of the serial data.

- [Example] Hereinafter, an example of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram of an embodiment according to the present invention.

In the figure, 100 is a data transmission/reception unit of a printer which is a terminal device, and 200 is an external controller.

Further, 1-1 is serial data for reception, 1-2 is a clock for reception, 1-3 is serial data for transmission, 1-4 is a clock for transmission, 2-1 to 2-4 are buffer circuits, and 3 is a serial clock. Parallel conversion register A, 4 is a reception buffer circuit, 5 is a control unit, 6 is an OR circuit, 7 is a reception buffer full signal, 8 is a reception ACK signal, 9 is a parallel-to-serial conversion register B, 10 is a transmission buffer register, 11 is an OR circuit, and 12 is a clock pulse generator.

A signal from the external controller 200 is sent to the printer 100 via an interface signal l. These are, for example, control commands and print data from the external controller 200 to the printer 100, and signals from the printer 100 to the external controller 200 are ready signals indicating the internal status of the printer 100, various warning signals, etc. , each of these statuses is represented by serial data and transmitted and received.

Serial data 1-1 from external controller 200 is input to serial-to-parallel conversion register A3 constituted by a shift register via buffer circuit 2-1. Further, the receiving serial clock 1-2 passes through a buffer circuit 2-2.

The signal is input to the OR circuit 6, and its output is input to the serial/parallel conversion register A3. The serial-to-parallel conversion register A3 shifts the input serial data one by one each time the clock from the OR circuit 6 is input.

The reception buffer circuit 4 simultaneously counts the clock from the OR circuit 6, and when it reaches 8, receives the reception data converted into 8-bit parallel data from the serial/parallel conversion register A3, and sends a reception breadth full signal to the control unit 5. Send out.

The control unit 5 can read the output data of the reception buffer register 4 when the reception buffer full signal 7 is input, and can take in the correct data. When a reception ACK signal 8 is sent from the control section 5 to the reception buffer circuit 4 as a confirmation signal, the reception ACK signal 7 is cleared.

Details of the reception buffer circuit 4 are shown in FIG.

In the figure, 41 is a parallel-in/parallel-out register, 42 is a counter, and 43 is a flip-flop circuit. When a clock pulse is input from the OR circuit 6, it is counted by the counter 42 and 8 passes t2. ,, Kara 7
．． □Yo5. ';;<514□+: /< /l/ X
l<M ”□, 11, the output data of the serial/parallel conversion register A3 is latched.The output is input to the control unit 5.At the same time, the output of the counter 42 is input to the flip-flop circuit 43, which converts it into 1 ”. The output is a reception buffer full signal 7, which is input to the control section 5. When the reception ACK signal 8 is input from the control unit 5 to the flip-flop circuit 43, the flip-flop is reset and the reception buffer full signal 7 is set to °°0'.
to °.

After sending out the reception ACK signal 8, the control section 5 drives the clock pulse generator 12 and operates it until the reception buffer full signal 7 is output. At this time, it only sends out the reception ACK signal 8 and does not receive data.

On the other hand, when sending data from the printer 100 to the external controller 200, 8-bit data is sent from the control section 5 to the transmission buffer 10, and then the data is sent to the parallel-to-serial conversion register B9. Thereafter, the transmission clocks 1-4 for parallel-to-serial conversion are sent from the external controller 200 to the buffer circuits 2-4, passed through the OR circuit 11, and input to the parallel-to-serial conversion register B9, where they are converted into serial data. The signal is sent to the external controller 200 via the buffer circuit 2-3.

The operation upon receiving the above-mentioned serial data will be explained in detail with reference to the timing chart of FIG.

In the figure, the received data (1) is received serial data 1-1 from the external controller 200.

The reception clock in (2) is the reception clock 1-2°, and the shift clock in (6) is the output of the OR circuit 6.

FIG. 3(A) shows the data reception timing during normal operation, and shows the data reception timing from the received data (1) input from the buffer circuit 2-1 to the serial/parallel conversion register A3
They will be sent sequentially from 8 onwards. At the same time, the reception clock (2) is input, and when 8 pulses are input, a carry signal is output from the counter 42 of the reception buffer circuit 4, and the contents of the serial/parallel conversion register A3 at this time are transferred to the register 4.
It is latched to 1. This is point A in FIG. 3(A).

The contents of the serial/parallel conversion register at this time are (1
1000010), and the flip 7 knob 43 is set by the carry signal from the counter 42, and a reception buffer full signal (7) is output to the control a11 section 5. When the control section 5 receives this reception buffer full signal (7), it takes in the contents of the register 41, that is, the parallel 8-bit reception data, outputs a reception ACK signal (8), and resets the flip-flop 43.

Then, the pulse output of the clock pulse generator is enabled, the counter 42 outputs the carry signal again, and the clock (12) from the clock pulse generator 12 is output until the reception buffer full signal (7) is output. Then, when the reception buffer full signal (7) is output, the output of the clock (12) is stopped, and then the reception buffer full signal (7) is output.
Outputs CK signal (8). The control unit 5 does not take in the data in the register 41 at this time, and prepares for the next received data.

Next, Figure 3 (B
) When the received data (1) similar to that shown in FIG. An example in which the number of clocks has reached more will be explained.

In this case, at point B, that is, at the seventh pulse of the regular reception clock, the counter 42 outputs carry number 4g, and the data of the serial-parallel conversion circuit 3 at this time is latched into the register 41. The value of the serial/parallel conversion register at this time is (11000011).

Following the input of this erroneous data, the control section 5 outputs a clock (12) from the clock pulse generator 12.

In this case, one clock is input to the counter 42 from the regular reception clock (2), and when the clock signal (12) from the clock pulse generator 12 is input to the counter 42 for seven pulses, the counter 42 outputs a carry signal. (Figure 3 (B) point C). Since the value of register 41 at this time is ignored, this erroneously input B
The data sent following the data at point (11000011) can be received correctly.

In the above explanation, data reception is terminated when the count value of the counter 42 reaches 8, and the synchronization difference between the data and the shift clock is corrected using the clock from the clock pulse generator 12, but the reception interval of the received data is long. In some cases, the clock pulse generator 12 may output the clock from the clock pulse generator 12 as the end of the data after a certain period of time has elapsed since receiving the received data.By doing this, any synchronization deviation (for example, clock omission or addition or reduction of a large number of clocks)
can also be quickly corrected.

[Effects] As explained above, according to the present invention, the reception clock and reception data are resynchronized after receiving serial data, so even if a synchronization difference between the reception clock and reception data occurs, it can be quickly corrected. , it is possible to provide a highly reliable serial data reception system that can correctly receive data when receiving requested data.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an embodiment according to the present invention, FIG. 2 is a detailed circuit diagram of a reception buffer circuit of this embodiment, FIG. 3A is a timing chart showing normal reception operation of this embodiment, FIG. 3 CB) is a timing chart showing the reception operation when a reception error occurs in this embodiment. In the figure, 1...interface signal, 1-1...receiving serial data, 1-2 receiving clock, 1-3 transmitting serial data, 1-4... transmitting clock, 2-1~
2-4...Buffer circuit, 3...Serial/parallel conversion register A, 4...Reception buffer circuit, 5...
・Control unit, 6.11... OR circuit, 7... Reception buffer full signal, 8... Reception ACK signal, 9... Parallel/serial conversion register B, 10... Transmission buffer register, 12 ...clock pulse generator,
41...Register, 42...Counter, 43...
It is a flip-flop circuit.

Claims (1)

[Claims] A serial data reception method that receives serial data sent together with a reception clock signal indicating the timing of data acquisition, wherein the reception device includes a conversion means that converts the received serial data into parallel data in synchronization with the reception clock. a detection means for counting the reception clock and detecting that the serial-to-parallel conversion by the conversion means is completed; an end detection means for detecting the end of reception of the received data; and a detection means for detecting the end after the end detection by the end detection means. A serial data receiving method comprising clock output means for outputting a counting clock to the converting means and the detecting means until the completion of conversion of the means is detected, and resynchronizing the received data and the received clock at the end of the received data. .