JPS6161489A - Method of producing printed circuit board - Google Patents
Method of producing printed circuit boardInfo
- Publication number
- JPS6161489A JPS6161489A JP18272984A JP18272984A JPS6161489A JP S6161489 A JPS6161489 A JP S6161489A JP 18272984 A JP18272984 A JP 18272984A JP 18272984 A JP18272984 A JP 18272984A JP S6161489 A JPS6161489 A JP S6161489A
- Authority
- JP
- Japan
- Prior art keywords
- catalyst layer
- substrate
- plating
- manufacturing
- printed wiring
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/03—Use of materials for the substrate
- H05K1/0313—Organic insulating material
- H05K1/0353—Organic insulating material consisting of two or more materials, e.g. two or more polymers, polymer + filler, + reinforcement
- H05K1/0373—Organic insulating material consisting of two or more materials, e.g. two or more polymers, polymer + filler, + reinforcement containing additives, e.g. fillers
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
- H05K3/18—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using precipitation techniques to apply the conductive material
- H05K3/181—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using precipitation techniques to apply the conductive material by electroless plating
- H05K3/182—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using precipitation techniques to apply the conductive material by electroless plating characterised by the patterning method
Landscapes
- Chemically Coating (AREA)
- Manufacturing Of Printed Wiring (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、化学メッキ法を用いて、片面プリント配線板
、両面プリント配線板、多層プリント配線板、フレキシ
ブル配線板等を製造するプリント配線板の製造方法に関
するものであり、さらに具体的:二云えば、導体回路を
無電解メッキを施すこと(二より形成させるアディティ
ブ方式口よるプリント配線板の製造方法(=関するもの
である。[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to printed wiring boards for manufacturing single-sided printed wiring boards, double-sided printed wiring boards, multilayer printed wiring boards, flexible wiring boards, etc. using a chemical plating method. More specifically, it relates to a method of manufacturing a printed wiring board using an additive method in which conductive circuits are formed by electroless plating (two steps).
従来、プリント基板の導体回路の形成はエツチングによ
る方法、あるいは電解メッキによる方法等(二より行な
われている−このエツチング方法による導体回路の形成
は、具体的にはプリント基板上に成層した金属導体の非
エツチング部分にスクリーンやオフセット等の印刷によ
りインキレジストを設けるか、又は感光性樹脂の硬化膜
層を設けたのち、不必要な部分をエツチングし、非エツ
チング部分のレジスト等を除去することにより導体回路
を形成する方法である。これによれば金属の導体をエツ
チングによって除去する為、省資源的ではなく、さら(
−レジスト等の形成、除去を必要とする為に工程数が多
いという欠点があった。又電解メッキによる方法は導体
基板上の非メッキ部分にインキレジスト、感光性樹脂の
硬化層を設は電解メッキを施して導体回路を形成し、こ
の導体回路を所定の絶縁基板上に移すという方法である
が、この方法では非常(=複雑な工程となる。Conventionally, conductor circuits on printed circuit boards have been formed by etching or electrolytic plating. By applying an ink resist to the non-etched areas by screen or offset printing, or by providing a cured film layer of photosensitive resin, etching unnecessary areas and removing the resist, etc. from the non-etched areas. This is a method of forming conductor circuits.This method removes the metal conductor by etching, which is not resource-saving and also (
-There was a drawback that the number of steps was large because it required formation and removal of resist, etc. In the electrolytic plating method, a hardened layer of ink resist and photosensitive resin is applied to the non-plated parts of a conductive substrate, electrolytic plating is applied to form a conductive circuit, and this conductive circuit is transferred to a predetermined insulating substrate. However, this method is a very (=complicated) process.
一方、上記口広の欠点を解決する為に無電解メッキ)二
よって導体回路を形成するアディティブ法がある。これ
にはCC−4法、PSMD法が一般的で、CC−4法で
は絶縁基板上)ニメッキ触媒性の付与された接着剤層を
形成し、その非メッキ部分にレジスト等の硬化層を設は
無電解メッキ(二より導体回路を形成するものである。On the other hand, in order to solve the problem of the wide mouth, there is an additive method in which a conductive circuit is formed by electroless plating. Commonly used for this are the CC-4 method and the PSMD method. In the CC-4 method, an adhesive layer with Ni-plating catalytic properties is formed on an insulating substrate, and a hardened layer such as resist is applied to the non-plated parts. is electroless plating (forms a two-strand conductor circuit).
又、PSMD法(Photo 5elective M
etal Deposition )は絶縁基板上にメ
ッキ触媒層を形成し、その非メッキ部分に紫外線を照射
し、その紫外線によってその部分に相当するメッキ触媒
層を非触媒化した後、無電解メッキを施し導体回路を形
成するものである。In addition, PSMD method (Photo 5elective M
etal Deposition) forms a plating catalyst layer on an insulating substrate, irradiates the non-plated parts with ultraviolet rays, de-catalyzes the plating catalyst layer corresponding to that part with the ultraviolet rays, and then performs electroless plating to form a conductor circuit. It forms the
本発明は無電解メッキ法;二よって導体回路を形成する
アディティブ法の改良である。The present invention is an improvement of the electroless plating method and the additive method of forming conductor circuits.
CC−4法(−おいては基板に接着剤層を形成し、その
上にレジスト等の形成を必要とするという不便があり、
又PSMD法ではレジスト等の形成を省略できるが、紫
外線処理した後、導体回路を形成するという製造上むず
かしい方法である。The CC-4 method (-) has the inconvenience of forming an adhesive layer on the substrate and then forming a resist on top of it.
Although the PSMD method can omit the formation of a resist, etc., it is a difficult manufacturing method in which a conductor circuit is formed after ultraviolet treatment.
本発明はこれらの欠点を除去すると同時(ユまったく新
しいアディティブ法によるプリント配線板の製造方法を
提供するものである。The present invention eliminates these drawbacks and at the same time provides a completely new method for manufacturing printed wiring boards using an additive method.
本発明の製造方法は、甑縁基板(=無電解メッキな施す
ことにより導体回路を形成し、プリント配線板を製造す
るもので、前記基板の表面にメッキ触媒層を形成処理す
る第1工程と前記第1工程で処理された前記基板の表面
上の非導体回路部分の触媒層を熱により非触媒化処理す
る第2工程と前記第2工程で処理された前記基板の表面
の触媒層を活性化処理する第3工程と前記第3工程で処
理された前記基板の表面に無電解メッキを施し所望の導
体回路を形成する第4工程とから成ることを特徴とする
ものである。The manufacturing method of the present invention is to manufacture a printed wiring board by forming a conductor circuit by applying electroless plating to a printed circuit board, and the first step is to form a plating catalyst layer on the surface of the board. a second step of thermally decatalyzing the catalyst layer of the non-conductor circuit portion on the surface of the substrate treated in the first step; and activating the catalyst layer on the surface of the substrate treated in the second step. This method is characterized by comprising a third step of chemically treating the substrate, and a fourth step of applying electroless plating to the surface of the substrate treated in the third step to form a desired conductor circuit.
メッキ触媒層は一般的(=使用されている塩化バラジク
ムー塩化第1スズの混合錯溶液(例えば、H8l0IB
、 日立化成工業株式会社製品)を使用し、上記溶液
への基板の浸漬あるいは溶液の塗布、吹付等(二上って
形成する。上記工程に先立って基板表面を適当な方法で
凹凸にする事(二より、触媒層の形成効果はより向上す
る。この方法には、ホーニング処理等の物理的粗面化方
法や、酸化性溶液による化学的粗面化方法が上げられる
。The plating catalyst layer is a general (= used mixed complex solution of Baladicum chloride and stannous chloride (for example, H8l0IB
, a product of Hitachi Chemical Co., Ltd.), by dipping the substrate in the above solution, applying the solution, spraying, etc. (Secondly, the effect of forming the catalyst layer is further improved. Examples of this method include physical roughening methods such as honing treatment, and chemical surface roughening methods using an oxidizing solution.
触媒層の非触媒化処理の方法は非導体回路部分に相当す
る触媒層を熱によって不活性化するものである。例えば
加熱接触体の該部への接触(=よって行うことができる
。加熱接触体としては、金属板、セラミック板等が上げ
られる。金属板等の加熱方法には金属板等の内部にヒー
ターを内蔵させるか、金属板自体をニクロム等の発熱抵
抗金属で製造するか、あるいは赤外線等で間接的に加熱
する方法がある。The method of decatalyzing the catalyst layer is to deactivate the catalyst layer corresponding to the non-conducting circuit portion by heat. For example, it can be carried out by contacting the part of the heating contact body. Examples of the heating contact body include a metal plate, a ceramic plate, etc. To heat the metal plate, etc., a heater is placed inside the metal plate, etc. There are two methods: to build it in, to manufacture the metal plate itself from a heat-generating resistance metal such as nichrome, or to indirectly heat it with infrared rays.
触媒層の活性化方法としては一般的(=使用されている
メッキ触媒活性化液(例えば、フッ化水素酸−塩酸系水
溶液、商品では0PC−5557クセレータ、奥野製薬
工業■製品)を使用し、上記溶液への基板の浸漬、ある
いは溶液の塗布、吹付等によって行なう。As a method for activating the catalyst layer, use a common plating catalyst activation solution (for example, a hydrofluoric acid-hydrochloric acid aqueous solution, product 0PC-5557 Xelator, Okuno Pharmaceutical Co., Ltd. product), This is carried out by dipping the substrate in the solution, or by applying or spraying the solution.
無電解メッキ液としては無電解ニッケルメッキ液、無電
解銅メッキ液等が上げられる。Examples of the electroless plating solution include an electroless nickel plating solution and an electroless copper plating solution.
次に本発明によるプリント配線板の製造方法を添付の図
面に基づいて説明すると、まず第1図炙−示す様に、基
板1(図示していないが、スルホール部を含むものでも
よい。)の表面にメッキ触媒液を浸漬等によって付着さ
せ、水洗の後、赤外線電球又は熱風等:二より乾燥し、
メッキ触媒層2を形成させる(第1工程)。次(=第2
図)二示す様(=メッキ触媒層2の上に非導体回路部分
と同一形状の加熱された金属板6を密着させ、その部分
を非触媒化させ非触媒化層4を形成する(第2工程)。Next, the method for manufacturing a printed wiring board according to the present invention will be explained based on the attached drawings. First, as shown in FIG. Apply plating catalyst solution to the surface by immersion, wash with water, dry with infrared light bulb or hot air, etc.
A plating catalyst layer 2 is formed (first step). next (=second
As shown in FIG. process).
次に第6図に示す様に導体回路部分のメッキ触媒層2を
メッキ触媒活性化液へ基板を浸漬等すること(二より活
性化層5を形成させる(第3工程)。Next, as shown in FIG. 6, the plating catalyst layer 2 of the conductor circuit portion is immersed in a plating catalyst activation solution (to form an activation layer 5 from the second step (third step)).
次にこれを通常の方法(=よって無電解メッキを施すと
、第4図(−示す様(=活性化層5の上に還元メッキ金
属6が析出され(第4工程)、所望のプリント配線板が
製造される。Next, when this is subjected to electroless plating using the usual method (=therefore, electroless plating is applied), as shown in FIG. A board is manufactured.
第1工程に於る赤外線電球、又は熱風等による乾燥温度
は高すぎるとメッキ触媒層が非触媒化するので、60℃
以下の温度で乾燥するのが望ましい。If the drying temperature using an infrared light bulb or hot air in the first step is too high, the plating catalyst layer will become non-catalytic, so the drying temperature should be 60°C.
It is desirable to dry at the following temperatures:
さらに第2工程に於る金属板等の温度は、低すぎると非
触媒化が進行しなく、第3工程での活性化で非触媒化層
が活性化層に反応する危険がある。Furthermore, if the temperature of the metal plate, etc. in the second step is too low, decatalyticization will not proceed, and there is a risk that the non-catalyzed layer will react with the activated layer during activation in the third step.
又高すぎると基板の軟化、溶解等の危険性がある為、1
00℃〜300℃、特には200℃が望ましい。Also, if it is too high, there is a risk of softening or melting the board, so
00°C to 300°C, preferably 200°C.
又密着する時間は、金属板等の温度及び基板材質等によ
り適宜決定されるが、1分〜10分が望ましい。The time for close contact is appropriately determined depending on the temperature of the metal plate, the substrate material, etc., but is preferably 1 minute to 10 minutes.
以下実施例(二より本発明を具体的に説明する。The present invention will be explained in detail from Example 2 below.
実施例
厚さ200μmのポリエステルフィルムをホーニング処
理し、2μmの表面粗さの基板を得た。この基板を、H
8l0IB (B立化成工業株式会社製品)。Example A polyester film having a thickness of 200 μm was honed to obtain a substrate with a surface roughness of 2 μm. This board is
8l0IB (B Ritsukasei Kogyo Co., Ltd. product).
濃塩酸、水を1 : 5 : 10の割合で混合して得
られたメッキ触媒液に室温で10分間浸漬し、その後1
〜2分水洗し、50℃の熱風で完全に乾燥させメッキ触
媒層を得た。この表面上に、非導体回路部分が導体回路
部分に対し5%突き出た形状の厚さ10%程度の鉄板に
クロムメッキを10μm施した温度200℃の非触媒化
用の金属板を1分間密着させる。次(二上記基板を0P
C−555アクセレータ(奥野製薬工業■製品)の20
容量%の水溶液(=室温で3分間浸漬し、水洗1〜2分
の後、無電解ニッケルメッキ液としてシ互−マS 68
0 (硫酸ニッケルー次亜すン酸ソーダ系1日本カニゼ
ン■製品)の20容量%の70℃水溶液に10分間浸漬
し無電解ニッケルメッキを施したところ、ニッケルの金
属によるフレキシブルプリント配線板が得られた。It was immersed in a plating catalyst solution obtained by mixing concentrated hydrochloric acid and water in a ratio of 1:5:10 for 10 minutes at room temperature, and then immersed in it for 10 minutes.
It was washed with water for ~2 minutes and completely dried with hot air at 50°C to obtain a plating catalyst layer. On this surface, a non-catalytic metal plate made of a 10% thick steel plate with a 10 μm chrome plating and a temperature of 200°C, with the non-conductor circuit part protruding 5% from the conductor circuit part, is attached for 1 minute. let Next (2) 0P the above board
20 of C-555 Accelerator (Okuno Pharmaceutical Product)
Volume % aqueous solution (= immersed at room temperature for 3 minutes, washed with water for 1 to 2 minutes, then used as an electroless nickel plating solution.
When electroless nickel plating was applied by immersing it in a 20% by volume aqueous solution of 0 (nickel sulfate-sodium hyposulfite 1 Nippon Kanigen ■ product) at 70°C for 10 minutes, a flexible printed wiring board made of nickel metal was obtained. Ta.
前記実施例ではフレキシブルプリント配線板(二ついて
例を上げたが、他の全てのプリント配線板;二も適用出
来る、又ポリエステルフィルムにかぎらず他の基板、例
えばポリカーボネート基板、ガラスエポキシ基板等(=
も適用出来ることは云うまでもない。In the above embodiments, flexible printed wiring boards (two examples were given, but all other printed wiring boards; two can also be applied, and are not limited to polyester films, but can also be applied to other substrates, such as polycarbonate substrates, glass epoxy substrates, etc.)
Needless to say, it can also be applied.
〔発明の効果〕
以上の様に本発明によれば、熱によってメッキ触媒層を
非触媒化し無電解メッキによってプリント配線板を製造
するという比較的単純な工程で、しかもエツチング、レ
ジスト等の形成、ハクリを必要とせず、安価で大量のプ
リント配線板を製造する方法に於てその効果は多大であ
る。又本発明の製造方法(=よって、フレキンプルプリ
ント配線板を製造する場合、帯状のプラヌチックフイル
ムを基板とすることで連続フープ方式の製造も可能なら
しめる。[Effects of the Invention] As described above, according to the present invention, the plating catalyst layer is decatalyzed by heat and a printed wiring board is manufactured by electroless plating, which is a relatively simple process, and in addition, etching, resist formation, etc. This method is highly effective in manufacturing printed wiring boards in large quantities at low cost without requiring peeling. Further, the manufacturing method of the present invention (=Thus, when manufacturing a flexible printed wiring board, a continuous hoop type manufacturing is also possible by using a band-shaped planutic film as a substrate.
第1〜4図は本発明の製造方法の工程を示す逐次段階の
部分拡大図である。
1・・・基板、2・・・メッキ触媒層、6・・・加熱さ
れた金属板、4・・・非触媒化層、5・・・活性化層、
6・・・無電解メッキ金属。
但し、各層厚は説明の為、適当に拡大されている。1 to 4 are partially enlarged views of successive steps showing the steps of the manufacturing method of the present invention. DESCRIPTION OF SYMBOLS 1... Substrate, 2... Plated catalyst layer, 6... Heated metal plate, 4... Non-catalyzed layer, 5... Activated layer,
6... Electroless plated metal. However, the thickness of each layer is appropriately enlarged for explanation.
Claims (1)
を形成し、プリント配線板を製造する方法に於て、前記
絶縁基板(以下基板と云う)の表面にメッキ触媒層を形
成処理する第1工程、前記第1工程で処理された前記基
板の表面上の非導体回路部分の触媒層を熱により非触媒
化処理する第2工程、前記第2工程で処理された前記基
板の触媒層を活性化処理する第3工程、前記第3工程で
処理された前記基板の表面に無電解メッキを施し所望の
導体回路を形成する第4工程とから成ることを特徴とす
るプリント配線板の製造方法。 2、該第2工程における非触媒化処理を加熱接触体と非
導体回路部分の触媒層との接触によつて行うことを特徴
とする特許請求の範囲第1項記載のプリント配線板の製
造方法。[Claims] 1. In a method for manufacturing a printed wiring board by forming a conductor circuit by applying electroless plating to an insulating substrate, a plating catalyst layer is provided on the surface of the insulating substrate (hereinafter referred to as the substrate). a first step of forming a catalyst layer on the surface of the substrate treated in the first step, a second step of decatalytizing the catalyst layer of the non-conductor circuit portion on the surface of the substrate treated in the first step; A print characterized by comprising a third step of activating the catalyst layer of the substrate, and a fourth step of applying electroless plating to the surface of the substrate treated in the third step to form a desired conductor circuit. Method of manufacturing wiring boards. 2. The method for manufacturing a printed wiring board according to claim 1, characterized in that the decatalytic treatment in the second step is performed by contacting a heating contact member with a catalyst layer of a non-conducting circuit portion. .
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP18272984A JPS6161489A (en) | 1984-09-03 | 1984-09-03 | Method of producing printed circuit board |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP18272984A JPS6161489A (en) | 1984-09-03 | 1984-09-03 | Method of producing printed circuit board |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS6161489A true JPS6161489A (en) | 1986-03-29 |
JPH0337878B2 JPH0337878B2 (en) | 1991-06-06 |
Family
ID=16123420
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP18272984A Granted JPS6161489A (en) | 1984-09-03 | 1984-09-03 | Method of producing printed circuit board |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6161489A (en) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5414925A (en) * | 1992-09-02 | 1995-05-16 | Sumitomo Electric Industries, Ltd. | Mechanism for inserting wired terminals into connector housing |
US5581873A (en) * | 1994-03-03 | 1996-12-10 | Sumitomo Wiring Systems, Ltd. | Temporary holding member for a wiring assembly manufacturing apparatus |
US7867686B2 (en) | 2004-02-10 | 2011-01-11 | Plastic Logic Limited | Metal deposition |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2017025345A (en) * | 2013-12-10 | 2017-02-02 | アルプス電気株式会社 | Electroless plating method |
-
1984
- 1984-09-03 JP JP18272984A patent/JPS6161489A/en active Granted
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5414925A (en) * | 1992-09-02 | 1995-05-16 | Sumitomo Electric Industries, Ltd. | Mechanism for inserting wired terminals into connector housing |
US5581873A (en) * | 1994-03-03 | 1996-12-10 | Sumitomo Wiring Systems, Ltd. | Temporary holding member for a wiring assembly manufacturing apparatus |
US7867686B2 (en) | 2004-02-10 | 2011-01-11 | Plastic Logic Limited | Metal deposition |
EP1714532B1 (en) * | 2004-02-10 | 2019-03-27 | Flexenable Limited | Metal deposition |
Also Published As
Publication number | Publication date |
---|---|
JPH0337878B2 (en) | 1991-06-06 |
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EXPY | Cancellation because of completion of term |