JPS6161433A - Manufacture of isolating groove - Google Patents
Manufacture of isolating grooveInfo
- Publication number
- JPS6161433A JPS6161433A JP18391884A JP18391884A JPS6161433A JP S6161433 A JPS6161433 A JP S6161433A JP 18391884 A JP18391884 A JP 18391884A JP 18391884 A JP18391884 A JP 18391884A JP S6161433 A JPS6161433 A JP S6161433A
- Authority
- JP
- Japan
- Prior art keywords
- polycrystalline silicon
- groove
- film
- oxide film
- silicon film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
- H01L21/76205—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO in a region being recessed from the surface, e.g. in a recess, groove, tub or trench region
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
- H01L21/76227—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials the dielectric materials being obtained by full chemical transformation of non-dielectric materials, such as polycristalline silicon, metals
Abstract
Description
【発明の詳細な説明】 （技術分野） 本発明は溝分離の製造方法に関するものである。[Detailed description of the invention] (Technical field) The present invention relates to a method for manufacturing groove isolation.
（従来技術）
従来、シリコン集積回路における素子分離法としては、
シリコン窒化膜をマスクにした選択酸化法が広く用いら
れている。しかし、この方法では、バーズビークと呼ば
れる横方向への酸化膜くい込みが生じ、分離領域がマス
ク設計寸法よシも広くなってしまうという不都合が生ず
る。(Prior art) Conventionally, element isolation methods for silicon integrated circuits include:
A selective oxidation method using a silicon nitride film as a mask is widely used. However, this method has the disadvantage that the oxide film intrudes in the lateral direction, called a bird's beak, and the isolation region becomes wider than the mask design dimension.
例えば分離領域の酸化膜厚が１μｍの場合、酸化膜のく
い込み量はおよそ０．５μｍである。従って、分離中が
１μｍ以下の素子分離をこの方法で実現することは困難
である。For example, when the oxide film thickness in the isolation region is 1 μm, the amount of penetration of the oxide film is approximately 0.5 μm. Therefore, it is difficult to achieve element isolation with a separation length of 1 μm or less using this method.
一方、微細素子分離法として、シリコン基板に溝を形成
し、この溝内部に絶縁物を埋め込む、いわゆる「溝分離
法」が広く検討されている。溝分離法では、シリコン基
板に異方性エツチングによシ溝を形成し、溝内部に多結
晶シリコンあるいはシリコン酸化膜を埋め込む方法が用
いられている。On the other hand, as a fine element isolation method, a so-called "trench isolation method" in which a trench is formed in a silicon substrate and an insulator is buried inside the trench has been widely studied. In the groove isolation method, a groove is formed in a silicon substrate by anisotropic etching, and a polycrystalline silicon or silicon oxide film is buried inside the groove.
気相成長多結晶シリコン膜はステップカバレンジが良好
であることと、熱的および弾性的性質が単結晶シリコン
基板とほぼ同一であることから、溝内の埋め込み材とし
て良く用いられる。ところが、多結晶シリコ〉は絶縁物
でないため、表面を熱酸化する必要がある。この熱酸化
を行うときに、上記方法で問題となった酸化膜くい込み
が生ずる。A vapor-grown polycrystalline silicon film is often used as a filling material in a trench because it has good step coverage and has almost the same thermal and elastic properties as a single-crystal silicon substrate. However, since polycrystalline silicon is not an insulator, its surface must be thermally oxidized. When this thermal oxidation is performed, the oxide film penetration, which is a problem in the above method, occurs.
この酸化膜くい込みは、横方向ばかシでなく、溝側面に
沿って縦方向にも進行する。この縦方向の酸化膜くい込
みは、シリコン基板にストレスを生じ結晶欠陥発生の原
因となる。This oxide film penetration not only progresses in the horizontal direction, but also progresses in the vertical direction along the side surfaces of the groove. This vertical penetration of the oxide film causes stress in the silicon substrate and causes crystal defects.
゛ 表面だけを酸化して溝内部に多結晶シリコンを残
しておくと、外部から電荷が酸化膜を通して注入され、
この電荷によって多結晶シリコンが帯電する。この帯電
によって多結晶シリコンに電位が生じ、溝とシリコン基
板の界面に反転層を形成し易くなシ、電気的不安定性の
原因となる。゛ If only the surface is oxidized and polycrystalline silicon is left inside the trench, charges will be injected from the outside through the oxide film,
This charge charges the polycrystalline silicon. This charging generates a potential in the polycrystalline silicon, making it difficult to form an inversion layer at the interface between the groove and the silicon substrate, causing electrical instability.
溝内に酸化膜を埋め込めば、この様な問題はなくなる。If an oxide film is buried in the trench, this problem will disappear.
しかし、気相成長酸化膜は一般にステップカバレッジが
悪いため、微細な溝内部を完全に埋め込むことは困難で
ある。さらに、気相成長酸化膜はエツチング速度が早い
ため、後工程での膜減りが大きくなるという欠点がある
。However, since a vapor-phase grown oxide film generally has poor step coverage, it is difficult to completely fill the inside of a fine groove. Furthermore, since the etching rate of the vapor-grown oxide film is fast, there is a drawback that the film is greatly reduced in subsequent steps.
（発明の目的）
本発明の目的は、上記の欠点をなくした溝分離の製造方
法を提供することである。OBJECTS OF THE INVENTION It is an object of the present invention to provide a method for producing groove separations that eliminates the above-mentioned drawbacks.
（発明の構成）
本発明の製造刃゛法は、シリコン単結晶基板の−主面上
の、ＭＯＳトランジスター等の素子を分離すべき領域に
、溝を形成する工程と、前記溝が形成された前記基板表
面に、熱酸化膜とシリコン窒化膜と前記溝の深さのおよ
そ半分の膜厚の多結晶シリコン膜を順次形成する工程と
、前記溝内部にのみ前記多結晶シリコン膜を残す工程と
、前記溝内に残された多結晶シリコン膜を熱酸化して酸
化膜に変換する工程よシ構成される。上記の工程を具備
することによシ、シリコン単結晶基板内に埋′ 設さ
れた酸化膜によりて分離された領域が、はぼ平坦な表面
形状を有して実現される。(Structure of the Invention) The manufacturing method of the present invention includes a step of forming a groove on the main surface of a silicon single crystal substrate in a region where elements such as MOS transistors are to be separated; a step of sequentially forming a thermal oxide film, a silicon nitride film, and a polycrystalline silicon film with a thickness approximately half the depth of the groove on the surface of the substrate; and a step of leaving the polycrystalline silicon film only inside the groove. , a step of thermally oxidizing the polycrystalline silicon film left in the groove to convert it into an oxide film. By implementing the above steps, the regions separated by the oxide film embedded in the silicon single crystal substrate can have a substantially flat surface shape.
（発明の効果）
本発明の製造方法に従えば、溝内部に形成される熱酸化
膜表面は、シリコン単結晶基板表面とほぼ等しくなる。(Effects of the Invention) According to the manufacturing method of the present invention, the surface of the thermal oxide film formed inside the groove becomes approximately equal to the surface of the silicon single crystal substrate.
また、シリコン窒化膜で凹まれた溝内部の多結晶シリコ
ンだけが酸化され、膜厚方向にだけ体積膨張が起こるた
め、基板のストレスが増加することはなく、結晶欠陥は
発生しない。In addition, only the polycrystalline silicon inside the groove formed by the silicon nitride film is oxidized and volumetric expansion occurs only in the film thickness direction, so stress on the substrate does not increase and crystal defects do not occur.
本発明は、溝内部が絶縁膜のみで構成されるため、多結
晶シリコンの帯電により界面が不安定になるという問題
がない。In the present invention, since the inside of the groove is composed only of an insulating film, there is no problem that the interface becomes unstable due to charging of polycrystalline silicon.
さらに、シリコン基板はシリコン窒化膜で被われている
ため、多結晶シリコンの酸化においても基板側に酸化膜
が食い込むことはない。Furthermore, since the silicon substrate is covered with a silicon nitride film, the oxide film does not dig into the substrate side even when polycrystalline silicon is oxidized.
従りて、マスク寸法通シの分離中が実現できるため微細
化が容易である。 。Therefore, it is possible to achieve separation throughout the mask dimensions, making it easy to miniaturize. .
（実施例）
素子分離の製造工程順に本発明を説明する。本説明では
、分離領域の形成過程だけを説明する。(Example) The present invention will be explained in order of the manufacturing process of element isolation. In this explanation, only the process of forming the separation region will be explained.
従りて、ＭＯ８′！Ｅ界効果トランジスターあるいはバ
イポーラトランジスター等の素子を製造するのに必要な
工程は、分離領域の形成過程前後あるいは形成過程中に
適宜挿入されるべきものとする。Therefore, MO8′! The steps necessary to manufacture elements such as E-field effect transistors or bipolar transistors should be inserted as appropriate before, during, or after the process of forming the isolation region.
第１ｃｌ（ａ）に示すように、単結晶シリコン基板１に
溝２を形成する。溝は、例えばフォトレジスト膜をマス
クにして、ＳＦｍあるいはＣＣｌ４等のプラズマ中でリ
アクティブイオンエツチングすることによシ、マスクパ
ターン通シの寸法で加工することができる。As shown in the first cl(a), a groove 2 is formed in a single crystal silicon substrate 1. The groove can be processed to have dimensions through the mask pattern, for example, by using a photoresist film as a mask and performing reactive ion etching in SFm or CCl4 plasma.
次に、第１図の）に示すように、５００に程度の熱酸化
膜３を形成する。次に気相成長により１０００λ程度の
シリコン窒化膜４を形成する。この上に、多結晶シリコ
ン５を気相成長する。この多結晶シリコン膜厚は、溝の
深さの約１／２とする。Next, as shown in FIG. 1), a thermal oxide film 3 having a thickness of about 500 mm is formed. Next, a silicon nitride film 4 having a thickness of about 1000λ is formed by vapor phase growth. Polycrystalline silicon 5 is grown thereon in a vapor phase. The thickness of this polycrystalline silicon film is approximately 1/2 of the depth of the groove.
次に、第１図（Ｃ）に示すように、溝部分の多結晶シリ
コンだけを残してエツチングするためのマスク６を形成
する。これは、溝２を形成したときのマスクパターンを
反転したマスクパターンｔ−用いることによって、容易
に実現できる。Next, as shown in FIG. 1C, a mask 6 is formed for etching leaving only the polycrystalline silicon in the groove portion. This can be easily realized by using a mask pattern t-, which is an inversion of the mask pattern used when forming the groove 2.
ところで、多結晶シリコンを第１図（ｄ）に示すように
、溝内部にのみ残すためには、多結晶シリコンのエツチ
ングに工夫がいる。By the way, in order to leave the polycrystalline silicon only inside the groove, as shown in FIG. 1(d), it is necessary to devise a technique for etching the polycrystalline silicon.
第１の方法は、マスク６として膜厚が０．２〜１．０μ
ｍ程度の気相成長酸化膜を用いる。多結晶シリコンのエ
ツチングに弗酸・硝酸・氷酢酸の混合液を用いると、気
相成長酸化膜もエツチングされる。In the first method, the mask 6 has a film thickness of 0.2 to 1.0 μm.
A vapor-phase grown oxide film with a thickness of about m is used. When a mixed solution of hydrofluoric acid, nitric acid, and glacial acetic acid is used to etch polycrystalline silicon, a vapor-phase grown oxide film will also be etched.
多結晶シリコン膜とマスク酸化膜とのエツチング速度比
を１に近ずけると、多結晶シリコン膜はテーパーエッチ
されるから、溝内に多結晶シリコン７を表面がほぼ平坦
になるように残すことができる。When the etching rate ratio of the polycrystalline silicon film and the mask oxide film approaches 1, the polycrystalline silicon film is tapered etched, so the polycrystalline silicon 7 should be left in the groove so that the surface is almost flat. I can do it.
第２の方法は、マスク６としてフォトレジスト膜を用い
る。多結晶シリコンエツチング液とフォトレジストの密
着性は一般に悪いため、テーパーエッチが行なわれる。The second method uses a photoresist film as the mask 6. Taper etching is performed because the adhesion between polycrystalline silicon etching solution and photoresist is generally poor.
第３の方法としては、マスク６として酸化膜マスクを用
いる。この酸化膜マスク６をマスクとして、リンを熱拡
散あるいはイオン注入によシ、丁度エツチングによシ除
去したい領域にだけリンが拡散されるようにする。リン
が高濃度に含まれると、多結晶シリコンのエツチング速
度が大きくなるから、溝内部にのみ多結晶シリコンを残
すことが容易になる。As a third method, an oxide film mask is used as the mask 6. Using this oxide film mask 6 as a mask, phosphorus is diffused only in the region to be removed by thermal diffusion or ion implantation, or by etching. When phosphorus is included in a high concentration, the etching rate of polycrystalline silicon increases, making it easy to leave polycrystalline silicon only inside the groove.
第４の方法としては、多結晶シリコン５０表面だけイオ
ン注入によフダメッジ層を形成し、エツチング速度を大
きくしてやる。すると、マスク６と多結晶シリコン５の
界面で、エツチングが早く進行するため、テーパーエツ
チングが行なわれる。As a fourth method, a fumarium ridge layer is formed by ion implantation only on the surface of the polycrystalline silicon 50, and the etching rate is increased. Then, etching progresses quickly at the interface between mask 6 and polycrystalline silicon 5, so that taper etching is performed.
その結果、はぼ平坦な形状で溝内に多結晶シリコンを残
すことができる。As a result, polycrystalline silicon can be left in the groove in a substantially flat shape.
上記第１から第４の方法、あるいはこれらの組み合せに
よシ、はぼ図１（ｄ）に示すような断面形状を得る。By using the first to fourth methods described above or a combination thereof, a cross-sectional shape as shown in FIG. 1(d) is obtained.
次に、多結晶シリコン７を１０００℃程度の温度で熱酸
化する。多結晶シリコン膜厚は、溝深さの約１／２であ
るから、酸化後には、第１図（ｅ）に示されるように、
酸化膜８の表面は基板表面とほぼ一致する。Next, polycrystalline silicon 7 is thermally oxidized at a temperature of about 1000°C. Since the polycrystalline silicon film thickness is approximately 1/2 of the trench depth, after oxidation, as shown in FIG. 1(e),
The surface of the oxide film 8 almost coincides with the substrate surface.
次に、第１図（ｆ）に示すように、窒化膜４および酸化
膜３を順次エツチングする。この様にして形成された分
離領域によって囲まれた領域９に、素子を形成する。Ｍ
Ｏ８電界効果トランジスターの場合には、ゲート酸化膜
を形成する工程がこれに続く。Next, as shown in FIG. 1(f), the nitride film 4 and the oxide film 3 are sequentially etched. Elements are formed in region 9 surrounded by the isolation region thus formed. M
In the case of O8 field effect transistors, this is followed by the step of forming a gate oxide.
（発明のまとめ）
本発明では、シリコン窒化膜で囲まれた多結晶シリ°コ
ンを酸化するので、シリコン基板に結晶欠陥を発生させ
ない。多結晶シリコン膜厚を溝深さの約１／２にするこ
とによシ、平坦な表面が得られる。溝内は絶紛物で充積
されているため、電気的に完壁な分離が実現できる。ま
た絶縁分離中は自由である。さらに、横方向への広がシ
がないなど、従来の分離法の欠点をすべて解決している
。(Summary of the Invention) In the present invention, since polycrystalline silicon surrounded by a silicon nitride film is oxidized, no crystal defects are generated in the silicon substrate. A flat surface can be obtained by making the thickness of the polycrystalline silicon film approximately 1/2 of the depth of the groove. Since the inside of the groove is filled with powder, complete electrical separation can be achieved. Also, it is free during insulation separation. Furthermore, it solves all the drawbacks of conventional separation methods, such as the absence of lateral spread.
第１図は本発明の詳細な説明するための素子断面図であ
る。
１・・・・・・単結晶シリコン基板、２・・・・・・溝
、３・・・・・・酸化膜、４・・・・・・シリコン窒化
膜、５・・・・・・多結晶シリコン膜、６・・・・・・
酸化膜、７・・・・・・多結晶シリコン、８・・・・・
・酸化膜、９・・・・・・素子領域。
・′°−−、１・FIG. 1 is a sectional view of an element for explaining the present invention in detail. 1... Single crystal silicon substrate, 2... Groove, 3... Oxide film, 4... Silicon nitride film, 5... Polymer Crystalline silicon film, 6...
Oxide film, 7... Polycrystalline silicon, 8...
- Oxide film, 9...Element region.・′°−−, 1・
Claims (4)
べき領域に溝を形成する工程と、前記溝が形成された前
記基板表面に熱酸化膜とシリコン窒化膜と前記溝の深さ
のおよそ半分の膜厚の多結晶シリコン膜とを順次形成す
る工程と、前記溝内部に前記多結晶シリコン膜を残すよ
うに他の部分を除去する工程と、前記溝内に残された多
結晶シリコン膜を熱酸化して酸化膜に変換する工程とを
含むことを特長とする溝分離の製造方法。(1) Forming a groove in a region to be isolated on one main surface of a silicon single crystal substrate, and adding a thermal oxide film and a silicon nitride film to the surface of the substrate where the groove is formed, and the depth of the groove. a step of sequentially forming a polycrystalline silicon film with a thickness approximately half of the thickness of the polycrystalline silicon film, a step of removing the other portions so as to leave the polycrystalline silicon film inside the trench, and a step of removing the polycrystalline silicon film remaining in the trench. 1. A trench isolation manufacturing method characterized by comprising the step of thermally oxidizing a silicon film to convert it into an oxide film.
おいて、前記多結晶シリコン膜エッチング用マスクとし
て酸化膜が用いられ、前記酸化膜をマスクとして前記多
結晶シリコン膜に、リンが、エッチングされるべき多結
晶シリコンの領域とほぼ一致して導入されていることを
特徴とする特許請求の範囲第（１）項記載の溝分離の製
造方法。(2) In the step of leaving the polycrystalline silicon film inside the groove, an oxide film is used as a mask for etching the polycrystalline silicon film, and phosphorus is etched into the polycrystalline silicon film using the oxide film as a mask. 2. The method of manufacturing trench isolation according to claim 1, wherein the groove isolation is introduced substantially in alignment with the region of polycrystalline silicon to be formed.
おいて、前記多結晶シリコン膜表面に内部よりもエッチ
ング速度の大きな領域が形成されていることを特徴とす
る特許請求の範囲第（１）項記載の溝分離の製造方法。(3) In the step of leaving the polycrystalline silicon film inside the groove, a region is formed on the surface of the polycrystalline silicon film where the etching rate is higher than that inside the groove. The method for manufacturing the groove separation described in Section 1.
おいて、前記多結晶シリコン膜エッチング用マスクとし
て気相成長酸化膜を用いることを特徴とする特許請求の
範囲第（１）項記載の溝分離の製造方法。(4) The groove according to claim (1), characterized in that in the step of leaving the polycrystalline silicon film inside the groove, a vapor-grown oxide film is used as a mask for etching the polycrystalline silicon film. Separation manufacturing method.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18391884A JPS6161433A (en) | 1984-09-03 | 1984-09-03 | Manufacture of isolating groove |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18391884A JPS6161433A (en) | 1984-09-03 | 1984-09-03 | Manufacture of isolating groove |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6161433A true JPS6161433A (en) | 1986-03-29 |
Family
ID=16144088
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP18391884A Pending JPS6161433A (en) | 1984-09-03 | 1984-09-03 | Manufacture of isolating groove |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6161433A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5914517A (en) * | 1996-07-16 | 1999-06-22 | Nippon Steel Corporation | Trench-isolation type semiconductor device |
| CN1121064C (en) * | 1996-06-27 | 2003-09-10 | 现代电子产业株式会社 | Method for manufacturing semiconductor device |
| US11075123B2 (en) * | 2019-09-16 | 2021-07-27 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method for forming isolation structure having improved gap-fill capability |
-
1984
- 1984-09-03 JP JP18391884A patent/JPS6161433A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1121064C (en) * | 1996-06-27 | 2003-09-10 | 现代电子产业株式会社 | Method for manufacturing semiconductor device |
| US5914517A (en) * | 1996-07-16 | 1999-06-22 | Nippon Steel Corporation | Trench-isolation type semiconductor device |
| US11075123B2 (en) * | 2019-09-16 | 2021-07-27 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method for forming isolation structure having improved gap-fill capability |
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