JPS6160155A - Memory subsystem - Google Patents

Abstract

PURPOSE:To attain the replacement of data during a copying action by controlling the replacement of data for the 1st and 2nd memories in response to the process of the copying action. CONSTITUTION:An instruction execution circuit 202 sets the address of the data to be written to a replacement address memory circuit 203 by an access request given from a central subsystem 1. The address of the next data to be copied is set to a copy address memory circuit 205 if no access request is given. This action is repeated to perform a copying action to the 2nd memory circuit 212 from the 1st memory 211. An address comparator 204 compares the contents with each other between circuits 203 and 205. Then the writing actions are given to both memories 211 and 212 when the coincidence is obtained between both contents or in the case of 203<205. While the writing action is given to the memory 211 only in the case of 203>205 respectively.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a storage subsystem that performs dual writing to two storage devices, and particularly relates to a recovery method after repair when one storage device fails. .

BACKGROUND ART In a storage subsystem that performs dual writing to two storage devices, if one of the storage devices fails, after repairing it, write the other storage device as a pair before incorporating the storage device into the storage subsystem. It is necessary to copy the contents of one storage device to that storage device.

Conventionally, this type of storage subsystem has had the disadvantage that it has been impossible to access the storage device that is being used for copying, and therefore the job has to be temporarily interrupted during the copying process.

Purpose of the Invention The present invention, when performing scouring on a pair of storage devices, performs ★ smearing on both storage devices for a portion that has already been copied,
For the uncopied parts, by committing only to the storage device where the original information to be copied is stored,
This is a storage subsystem that makes it possible to access a paired storage device in parallel with copying.

Structure of the Invention In order to achieve the above object, a storage subsystem according to the present invention includes a first storage device and a second storage device that store information, and a second storage device that sequentially stores information in the first storage device. a first memory circuit that temporarily stores the content of the information read in a fixed unit from the first memory device when copying to the apparatus; a second memory circuit that stores the address of the information at a point in time; an address comparison circuit that compares the address of the first storage device to be updated and the content of the second storage circuit when updating the contents of the storage device;
When updating the contents of the first storage device by interrupting the operation of copying the contents of the storage device to the second storage device, the output of the address comparison circuit is used to compare the contents of the first storage device with the first storage device. When updating the information copied in the second storage device, it updates the contents of the first storage device and the second storage device, and if it is not copied, only the contents of the first storage device are updated. It is characterized by

Embodiment of the Invention Next, a preferred embodiment of the present invention will be specifically explained with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention. In the figure, reference numeral 1 indicates a central processing subsystem, 2
1 and 2 respectively show storage subsystems according to the present invention.

In FIG. 1, copying from the first storage device 211 to the twenty-eighth memory device 212 is performed in the following order in units of 3i data, starting from the address with the smallest address.

The instruction execution control circuit 202 sets the address of the data to be read from the first storage device 211 in the copy address storage circuit 205 through the signal line 304, and also sets the address of the data to be read from the first storage device 211 into the copy address storage circuit 205 through the signal line 304.
21, a read operation instruction and an address of data to be read are transferred to the first storage device 211. Data read from the first storage device 211 is stored in the data storage circuit 201 through the signal line 311. Next, the instruction execution control circuit 202 connects the second storage device 212 through the signal line 322.
Instructs the write operation and transfers the address of the data to be written. First storage device 21 in data storage circuit 201
The data read from 1 is passed through signal line 312 to the second
The data is transferred to the storage device 212 and written in a designated area.

Next, the instruction execution control circuit 202 checks whether there is a data access request from the central processing subsystem 1 through the signal line 301, and if there is no access request, the next data to be copied to the copy address storage circuit 205 is determined. By setting the address and repeating the above process, data is sequentially copied from the first storage device 211 to the second storage device 212.

When an access request is received from the central processing subsystem 1 through the signal line 301, the instruction execution control circuit 202
01 from the central processing subsystem 1, and if the command is a data update command, then the address of the data to be pledged is received and set in the update address storage circuit 203 through the signal line 302. The address comparison circuit 204 compares the contents of the update address storage circuit 203 sent through the signal line 305 and the contents of the copy address storage circuit 205 sent through the signal line 306, and sends the comparison result to the instruction execution control circuit 202 through the signal line 303. Notice.

If the contents of the update address storage circuit 203 are equal to or smaller than the contents of the copy address storage circuit 205, the instruction execution control circuit 202 sends the instruction execution control circuit 202 to the first storage device 2 through the signal line 321.
11, the address of the data to be written, which is an instruction for a write operation, is transferred. Subsequently, data sent from the central processing subsystem 1 through the signal line 301 is sent to the data storage circuit 2.
01, the data is simultaneously transferred to the first storage device 211 through the data storage circuit 201 and the signal line 311, and written into the designated area. Subsequently, the instruction execution control circuit 202 transfers an instruction to perform a pledge operation and the address of the data to be pledged to the second storage device 212, and transfers the address of the data to be pledged from the central processing subsystem 1 stored in the data storage circuit 201. The data is transferred to the second storage device 212 and written to the designated area.

If the contents of the update address storage circuit 203 are larger than the contents of the copy address storage circuit 205, writing is performed only to the first storage device 211 in the same manner as described above.

When the write operation specified by the command from the central processing subsystem 1 is completed, the original copying operation is resumed and the first
This process is repeated until all the contents of the storage device 211 are copied to the second storage device 212.

Effects of the Invention As explained above, the present invention is configured to control the updating of data in the first storage device and the second storage device according to the progress state of the five copying operations, thereby making it possible to update data during the copying operation. It has a pressing effect.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing one embodiment of the present invention.

Claims (1)

[Claims] A first storage device and a second storage device that store information, and when the information in the first storage device is sequentially copied to the second storage device, the content of the information read from the first storage device in a fixed unit. a first memory circuit for temporarily storing information, a second memory circuit for temporarily storing an address of information, an address of the first memory device to be updated when updating the contents of the first memory device, and the second memory circuit; an address comparison circuit that compares the contents of the storage circuit, and when updating the contents of the first storage device by interrupting the operation of copying the contents of the first storage device to the second storage device, the address comparison circuit compares the contents of the storage circuit. When updating information in which the contents of the first storage device have already been copied to the second storage device using the output of the comparison circuit, update the contents of the first storage device and the second storage device; A storage subsystem characterized in that only the contents of the first storage device are updated if the contents have not been copied.