JPH0196734A - Stack control system - Google Patents

Abstract

PURPOSE:To assure the executing sequence of command data even when the command data received from plural systems are stored in one stack by using a means which can stop temporarily only the processing carried out based on the command data received from the system issuing a halt instruction. CONSTITUTION:When an A system, for example, issues a halt instruction, the contents of an executing address register 2 (value is address 01) are stored into a saving register 3. Thus the A system is held. While data are read out of a B system and the V bits of the corresponding address of a stack 32 are set at 0 when the processing is through. Thus the command data of a system B are successively processed and the V bits are set at 0. When a start command is produced from the A system, the address 01 is written into the register 2 and the data are read out of the stack 32. These data are processed based on the data on the A system.

Description

[Detailed Description of the Invention] [Summary] Regarding a stack control method in which command data from multiple systems is stored in one stack, and the command data stored in the stack is retrieved and executed, in this type of stack control method, A stack that stores command data, valid bits, and system code, with the purpose of guaranteeing the order of command data execution; a write address register used when writing command data to the stack; and a stack command. Execution address register used when executing data, save address register, halt state storage means that indicates which system command data is in a halt state among command data in the stack, save execution address register Cohering means for copying to the address register, restoring means for restoring the save address register to the execution address register, write processing means for writing command data to the stack, inside the stack A structural requirement is to include an execution processing means for executing the command data.

[Industrial application field]

The present invention is a stack control method in which command data such as commands sent from multiple systems and data indirectly specifying commands is stored in one stack, and the command data stored in the stack is retrieved and executed. It is related to.

[Conventional technology]

FIG. 8 is a diagram showing a conventional stack control method. In the figure, 50 is a stack, 51 is a write address register, 52 is an execution address register, 53 is a command data register, 54 is an execution order determination circuit, 55 is a halt state storage unit, and 56 is an execution register. It shows. As systems, there are A system, B system, . . . , n system. Portions 51 to 56 exist for each system.

The stack 50 stores command data and execution order codes sent from the corresponding system. Command data means a command or data that indirectly instructs a command. Write address register 51 is used when writing command data to stack 50. Execution address register 52 is used when executing command data in stack 50.

The command data register 53 is set with command data sent from the corresponding system. The execution order determination circuit 54 determines the order in which command data is received.For example, if the order in which command data is received is A-system command data, B-system command data, etc., then A The system's execution order determining circuit 54 determines that its own data reception order is the first (first) and generates an execution order code representing the first, and the B system's execution order determining circuit 54 determines that its own data reception order is the first (first) For example, the state value of the halt state storage unit 55 of system A is determined to be the second command data reception order and generates an execution order code representing the second command data. It becomes a halt value (on) when it is sent, and a non-halt value (off) when a start instruction is sent.
become. When the value of the A-system halt state storage unit 55 indicates the halt value, reading from the A-system stack 50 is not performed.
The command data read from is set.

When command data is sent from the A system, the command data is written to the stack 50 and the write address register 51 is incremented by 1. At this time, the reception order (as a whole including A system, B system, ... n system) is determined by the execution order determination circuit 54, and an execution order code is generated.
This execution order code is also written to the stack 50. A similar action occurs in the B series.

. . . This is also carried out for the n-series.

When activated, command data and execution sequential code are read from the stack 50. The same applies to other systems. Command data read from the A-system stack 50, command data read from the B-system stack 50,
. . . Processing is performed based on command data read from the n-system stack 50, and the execution order follows the value of the read execution order code.

[Problem that the invention seeks to solve]

In conventional technology, a stack is prepared for each system, and command data from multiple systems is stored in the corresponding stack in order, retrieved and executed in order, and halt and start instructions are issued for each system. In order to maintain the sequential execution of command data for each system even when a halt command or a start command is issued, it is necessary to store the stack for each system and the order of command data between systems. This had the disadvantage of requiring additional functions and increasing hardware.

The present invention was created in view of this point, and provides a stack control method that stores command data from multiple systems in one stack and also guarantees the order of command data execution. is intended to provide.

[Means for solving problems]

FIG. 1 is a diagram showing the principle of the present invention. The stack control method of the present invention includes a write address register 1, an execution address register 2, a save address register 3, halt state storage means 10 and 11, and a stack 32. , valid bit generation means 60, system code generation means 61, copying means 6
2. Restoring means 63, writing processing means 64, execution processing means 6
5. Update means 66 and 67 are provided. stack 3
2 stores command data from the two systems A and B, and also stores a valid bit and a system code indicating the system that issued the command data. Write address/
Register l is used when writing command data etc. to stack 32. The updating means 66 updates the write address register 1, and the execution address register 2:
It is used, for example, when executing command data in the stack 32. The update means 67 updates the execution address register 2. The save address register 3 is used to save the value of the execution address register 2.

The valid bit generating means 60 generates an on valid bit and an off valid bit.

System code generation means 61 generates a system code indicating the command data issuing system.

The halt state storage means 10 takes a halt value when a halt instruction is sent from the A system, and takes a non-halt value when a start instruction is sent from the A system.

The halt state storage means 11 becomes a halt value when a halt instruction is sent from the B system, and becomes a non-halt value when a start instruction is sent from the B system.

The copying means 62 performs a process of copying the value of the execution address register 2 to the save address register 3.

The restoring means 63 performs processing to restore the value of the save address register 3 to the execution address register 2. The write processing means 64 performs processing to write command data etc. to the stack 32. The processing means 65 performs processing for executing command data stored in the stack 32.

The copying means 62 performs the following operations: (1) When one system A issues a halt instruction while the other system B's halt state storage means 11 is in a non-halt value state, (1) the halt state storage means 10 of one system A When a halt instruction is issued from the other system B under a non-halt value state, ■ both of the two halt state storage means 10 and 11 are the halt value, and the value of the execution address register 2 is the save value. Under the condition that the value of address register 3 is greater than or equal to
If the value of save address register 3 is restored to execution address register 2, the value of execution address register 2 is restored to save address register 2.
Perform processing to copy to register 3.

The restoring means 63 restores the halt state of one system A under a state in which the halt state storage means 10 of one system A indicates a halt value and the halt state storage means 11 of the other system B indicates a non-halt value. Under the condition that the storage means 10 indicates a non-halt value or the halt state memory means 11 of the other system B indicates a halt value and the halt state memory means 11 of one system A indicates a non-halt value. On condition that the halt state storage means 11 of the other system B indicates a non-halt value, processing is performed to restore the value of the save address register 3 to the execution address register 2.

When command data is sent from the system, the write processing means 64 stores the command data, the ON valid bit, and the system code of the command data issuing system in the stack 3.
2 to the address indicated by write address register 1, and then processing for updating write address register 1 is performed.

The execution processing means 65 reads data from the address indicated by the execution address register 2 in the stack 32; (1) If the valid bit in the read data is off, it updates the execution address register 2 and writes the 1. If the halt state storage means 10 or 11 specified by the system code of the read data indicates a halt value, the execution address register 2 is updated. (1) The valid bit in the read data is on and the halt state storage means 10 or 11 specified by the system code of the read data has a non-halt value. If indicated,
It executes processing based on command data in the read data, turns off the valid bit at the address indicated by execution address register 2 after the processing is completed, and then performs processing for updating execution address register 2.

〔Example〕

FIG. 2 is a diagram showing an overview of an embodiment of the present invention, FIG. 3 is a diagram explaining stack execution, FIG. 4 is a diagram explaining writing of data to the stack and execution based on stack data, and FIG. FIG. 5 is a block diagram of an embodiment of the present invention, FIG. 6 is a diagram showing the generation of control signals, and FIG. 7 is a diagram showing the operation when a halt instruction is issued and then a start instruction is issued. In the figure, 1 is a write address register, 2 is an execution address register, 3 is a save address register, 4 is a command address register on the system A side, 5 is a command address register on the system B side,
6 is the read V bit, 7 is the read S bit, 8 is the execution register, 10 to 15 are flip-flops, 16 is the halt release signal, 17 is the C0PY signal, 19 to 22 are AND
circuit, 23 is an OR circuit, 24 and 25 are an AND circuit, 26
is an OR circuit, -27 is an AND circuit, 28 is an OR circuit, 3
0 is the adapter operation register on the system A side, 31 is the adapter operation register on the system B side, 32 is the stack, 3
3 is a command buffer, 40 is a common memory adapter, 41 is a common memory, and G1 to 614 are gate conditions.

First, FIG. 2 will be explained. The common memory adapter 40 connected to the common memory 41 is a device for quickly switching to the slave system when the main system is down in a duplex system, and the common memory 41 stores information necessary for switching. There is. When system A issues a command address, this command address is set in command address register 4, then written to stack 32, and write address register 1 (see Figure 5) is set to +1. be done. When writing the command address of system A, the V bit of “1°” and the S bit of “0” are also written to the same location (5th
(see figure) 0 Then, for example, when system B issues a command address, this command address is set in command address register 5, then written to stack 32, and write address register l is incremented by 1. Ru. When writing the command address of system B, the v bit of "1" and the S bit of "1" are written to the same location. Writing of the command address to the stack 32 is performed as described above.

The 5TART/HALT command issued by the system is not a start signal for reading commands in the stack, but rather indicates whether to execute the command or whether to wait. In fact, reading the data in the stack is managed by the microprogram, and the stack 32 reads commands according to instructions from the microprogram.
The read data (consisting of command address, V bit and S bit) read from address X of execution register 8
etc. is set. If the S bit of the read data is “O” and the V bit is “1”, the system A
The command is read out from the address indicated by the command address in the main memory of , and the read command is stored in the command buffer 33.

As shown in Figure 3, the command is a command code,
It consists of byte count, common memory address, main memory address, etc.

Command codes include 1ead and -rite.

After fetching the command into the buffer 33, the common memory adapter 40 transfers data between the common memory 41 and the main memory of system A according to the command code. After the data transfer is completed, the V bit at address is “0”
It is said that A similar operation is performed when system B sends a start instruction.

When System A issues a HALT instruction, the HALT instruction is set in adapter operation register 30 and data transfer based on System A's command address stored in stack 32 is interrupted. If System B issues a halt indication, data transfer based on System B's command address stored in stack 32 is interrupted.

FIG. 4 is a diagram illustrating writing of data to the stack and execution based on the data in the stack.

When data is written to command address register 4 or 5, 5TKRQIA (stack request) or 5TKRQIB is turned on. 5TKRQIA
When turned on, gate G5 (see FIG. 5) opens and the data in command address register 4 is written to stack 32. Similarly, when 5TKRQIIB turns on, gate G6 (see FIG. 5) opens and the data in command address register 5 is written to stack 32. If both 5TKRQ A and 5TKRQIB are not on, data is read from the stack 32, and if the read data is valid, processing based on the read data is executed. Note that the processing in FIG. 4 is realized by a microprogram.

FIG. 5 is a block diagram of an embodiment of the present invention.

If system A sends a halt instruction before system B, bit AI will turn on and system B will
If a halt instruction is sent earlier than , bit BH turns on. The combination of bits AI and BH is called the H code. Gate G1 is opened when stacking the command address, gate G2 is opened when data transfer based on the command address is completed, gate G3 is opened when stacking the command address of system A, and gate G4 is opened when stacking the command address of system A. Gate G5 is opened when stacking the command address of system A, gate G5 is opened when stacking the command address of system A, and gate G6 is opened when stacking the command address of system A.
Open when stacking command addresses.

Gate G7 opens when signal C0PY is turned on.

Gate G8 opens on condition that the halt release signal is turned on. Gate G9 is “0” V bit is stack 3
2, when data transfer based on a command address is completed, or when the S bit and H code of data read from the stack match. Gate G1
0 is opened when command address writing is instructed. Game) Gll is a write address that opens when instructed to execute data transfer based on a command address.
Register 1 is incremented by 1 each time a command address is written to stack 32. If a write is instructed, the address of write address register 1 is sent to stack 32. The contents of execution address register 2 are incremented by 1 when gate G9 opens.

Also, when G7 opens, the execution address register 2
The contents of are copied to save address register 3. When gate G8 opens, the contents of save address register 3 are restored to execution address register 2. When execution is instructed, the address of the execution address register 2 is sent to the stack 32 via the GLL, and data is read from the stack 32. When the A system sends a command address, this command address is set in register 4, gate G5 is opened, and the command address in register 4 is applied to the data input terminal of stack 32. Similarly, when the B system sends a command address, this command address is set in register 5, gate G6 is opened, and the command address in register 5 is applied to the data input terminal of stack 32. When a command address is written to the stack 32, Gl is opened, the V bit of "1" is also written, and furthermore, when the A system stack is written, the S bit of "0° is written to the stack 32, and the S bit of 0° is written to the B system stack. When “
An S bit of 1' is written to the stack 32.

When data is read from address X of the stack 32, the command address in the read data is stored in the execution register 8.
, the V bit is set in the read V bit section 6, and the S bit is set in the read S bit section 7. When the data transfer based on the read command address is completed, gate G2 is opened and the V bit at address X of stack 2 is set to "0".

FIG. 6 is a diagram illustrating generation of control signals.

In the figure, 10.11.15 indicates a J- flip-flop, and 12 to 14 indicate a D flip-flop.

As shown in FIG. 6(a), when the A-system halt instruction is issued, the flip-flop IO is set to J-, and the signal HALTA is turned on. When the A-system start instruction is issued, the flip-flop 10 is reset to J-, and the signal HALTA is turned off. Similarly, when a B-system halt instruction is issued, the flip-flip 11 is set to J-, and the signal HALTB is turned on. When the B system start instruction is issued, the flip-flop 11 is reset to J-, and the signal HALTB is turned off. When signal HALTA and signal HALTB are both turned on, signal Wll is turned on. The ON signal -H indicates that a halt instruction has been issued from both the A system and the B system.

As shown in FIG. 6° C.), when the signal HALTA is on and the signal HALTB is on, the signal All is turned on. Similarly, the signal HALTB is high and the signal H
When ALTA is on, signal BH is on. When the signal HALTA turns on while the signal AI is on, the halt release signal turns on, and when the signal BH turns on, the signal 11. The halt release signal also turns on when ALT B turns on.

As shown in FIG. 6(C), execution address register 2
When the contents of the save address register 3 become equal to the contents of the save address register 3, the flip-flop 15 is set to J-;
Signal 11: A, SA turns on. And signal C0P
When Y is turned on, flip-flop 15 is reset to J- and signal EA=SA is turned off.

As shown in FIG. 6(d), the signal HALTB is turned on (B
When an A-system halt instruction is issued under a condition (not a system-system halt), the signal C0PY is turned on. In addition, the signal HAL
When a B-system halt instruction is issued while TA is on (not an A-system halt), the signal C0PY is turned on. Furthermore, the halt release signal is turned on, the signal WH is turned on, and the signal E is turned on.
The signal cop is also activated when the condition that A=S^ is on is met.
y turns on.

Next, the operation of the embodiment shown in FIG. 5 will be explained.

When storing command addresses in the stack 32, the command addresses are stored in the stack 32 in the order in which they are sent, regardless of whether they are sent from the A system or the B system, and the execution address
Update register 2 by +1.

At this time, in addition to the command address,
A V bit of °1" indicating that the address is valid is written to the same location on the stack 32, and if the command address is from the A system, an S bit of "0" is written, and an S bit of "0" is written if the command address is from the A system. For example, an S bit of “1” is written to the same location on the stack 32.

During execution, execution address register 2 is used. If the V bit of the data read from the stack 32 is "l", the command address is considered valid, processing is performed for the A system or B system, and when the processing is completed, the V bit is set to 0° and stored in the stack 32. and updates execution address register 2 by +1. When data is read from the stack 32, if the V bit of the read data is "0", the data is invalidated, and the execution address register 2 is updated until data with the V bit of "1" is retrieved.

FIG. 7 is a diagram explaining the operation when a halt instruction is issued and then a start instruction is issued. In the figure, EAR indicates the execution address register and SAR indicates the save address register. There is. Also, AIH
ALT indicates that the A system is in the halt state, and Al5T
ART indicates that the A system has issued a start instruction, and the B system
IIIALT indicates that the B system is in the halt state, and B
ISTART means that the B system has issued a start instruction.

FIG. 7(a) is a diagram showing the operation when the A system issues a halt instruction and then the A system issues a start instruction. When the A system issues a halt instruction, the contents of execution address register 2 at that time are stored in save address register 3, and the A system enters the halt state.0 In the illustrated example, when a halt instruction is issued, It is assumed that the value of execution address register 2 indicates address 01. Since no halt instruction has been issued from the B system, data is read from address 01 of the stack 32. Since this read data is from the B system, processing is performed based on the read data, and after the processing is completed, the data is read from address 01. The V bit of the address is set to '0°.0 Next, the data at address 02 is read out, and since this read data is from the A system, the data at address 03 is read out next.
Since this read data is also from the A system, no processing is performed based on the read data, and the data at address 04 is read. Since the data at address 04 is from the B system, processing is performed based on this data, and after the processing is completed, the V bit at address 04 is set to 0'' and the value of execution address register 2 is updated to address 05. At this time, when a start instruction is issued from the A system, address 01 saved in save address register 3 is written to execution address register 2, and address 01 of stack 32 is written to execution address register 2.
Data is read from the address and processing is performed based on the data of the A system. In this case, since the V bit of the command addresses of the B-systems that have already been processed has been reset to "0", no processing is performed based on the command addresses of these B-systems.

FIG. 7(B) is a diagram illustrating the operation when the A system issues a halt instruction, then the B system issues a halt instruction, and then a start instruction is issued. When the A system issues a halt instruction while the execution address register is pointing to address 01, signal AI is turned on and address 01 is saved in save address register 3. If the B system issues a halt instruction when execution address register 2 points to address 04,
Since both the A system and the B system have issued a halt instruction, updating of execution address register 2 is stopped and reading of data from stack 32 is also stopped. Under this condition, when the B system issues a start instruction, the value of execution address register 2 is input to the address terminal of stack 32, and data reading from stack 32 is resumed. The subsequent steps are the same as in the case of FIG. 7(a).

The execution address (address 01) at the time when the A system issues the halt instruction is present in save address register 2, and the execution address (address 04) at the time the B system issues the halt instruction is the execution address. Under the state existing in register 2, if the A system issues a start instruction first, address 01 stored in save address register 3 is written to execution address register 2 at the same time. Address 04 stored in execution address register 2 is written to save address register 3. Then, the data at address 01 is read, but
Since the data at address 01 has been processed, the data at address 02 is read out, and processing is performed based on this read data, and after the processing is completed, the V bit of the data at address 02 is set to "0".

Similarly, processing is performed based on the data at address 03.

Since the data at address 04 belongs to the B system and the B system is in a halt state, no processing is executed based on this data. Since the data at address 05 is from the A system, processing is performed based on the data at address 05. Since the data at address 06 is from the B system, no processing is performed based on this data.

When the execution address points to address 07, when a start instruction is sent from the B system, address 04 saved in save address register 3 is written to execution address register 2, and the data at address 04 is The reading is performed.

In this case, if the B system starts when the address of execution address register 2 is smaller than the address of save address register 3, the address between save address register 3 and execution address register 2 will be For example, if both A and B systems are in a halt state, save address register 3 holds address 01, and execution address register 2 holds address 04. Assume that there is.

When the halt state of system A is released, the contents of execution address register 2 are saved in save address register 3, and the contents of save address register 3 are restored to execution address register 2. As a result, the contents of save address register 2 become address 04, and the contents of execution address register 2 become address 01. Next, when the B-system halt state is released and the contents of save address register 3 (address 04) are restored to execution address register 2, if there are A-system commands at addresses 02 and 03, then In order to prevent this, when both systems are in the halt state (signal Wll is on) and one system releases the halt state, the save address register 3 is If the contents are smaller than the contents of execution address register 2, the contents of execution address register 2 are saved to save address register 3.
Such an operation, which is not copied to the original, is realized by the circuit shown in FIG. 5(d). In other words, when the contents of save address register 3 are smaller than the contents of execution address register 2, the EA=SA bit will not turn on.
The AND condition of the AND circuit 27 is not satisfied, and the contents of the execution address register 2 are not copied to the save address register 3.

〔Effect of the invention〕

As is clear from the above description, according to the present invention,
(b) When a halt instruction is issued, only the processing based on the command data from the system that issued the halt instruction can be temporarily interrupted; C) If there is no halt instruction, the command data will be read out according to the storage order of the command data, and processing will be performed based on the command data.Even if a start instruction is given after a halt instruction is given, It is possible to achieve remarkable effects such as being able to read command data from the stack and execute processing based on the command data without disturbing the order in which command data is stored in each system.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing the principle of the present invention, FIG. 2 is a diagram showing an overview of an embodiment of the present invention, FIG. 3 is a diagram explaining stack execution, and FIG. 4 is a diagram showing writing of data to the stack and stack operation. 5 is a block diagram of an embodiment of the present invention; FIG. 6 is a diagram illustrating generation of control signals; FIG.
This figure is a diagram for explaining the operation when a halt instruction is issued and a start instruction is issued thereafter, and FIG. 8 is a block diagram of a conventional stack control system. l...Write address register, 2...Execution address register, 3...Save address register,
4... Command address register on the system A side, 5... Command address register on the system B side, 6... Read V bit, 7... Read S bit, 8
...Execution address register, 10 to 15...Flip-flop, 16...Holt release signal, 17.
...C0PY signal, 19 to 22...AND circuit, 2
3...OR circuit, 24 and 25-AND circuit, 26 ・
OR circuit, 27...AND circuit, 28...OR circuit, 30...system A side adapter operation register, 3
1... Adapter operation register on the system B side, 32.
...Stack, 33...Command buffer, 40...
・・Common memory adapter, 41 ・・Common memory, G
1 to G14...Gate. Figure 1: The stack of bamboos is placed in the bamboo chamber. Figure 5: The bottle! Figure 4 Implementation of the present invention Figure 5 Figure 6

Claims (1)

[Scope of Claims] Two systems (A, B), a stack (32) for storing a plurality of words consisting of command data, valid bits, and a system code indicating the system that issued the command data; a write address register (1); an update means (66) for updating the value of the write address register (1); an execution address register (2); and an update means (66) for updating the value of the execution address register (2). an updating means (67); a save address register (3) for saving the value of the execution address register (2); and a valid bit generating means (60) for generating an on valid bit and an off valid bit. and a system code generation means (61) for generating a system code indicating the command data issuing system.
A halt value has a one-to-one correspondence with each system, and becomes a halt value when a halt instruction is sent from the corresponding system, and becomes a non-halt value when a start instruction is sent from the corresponding system. A plurality of state storage means (1
0, 11), copying means (62) that performs processing to copy the value of the execution address register (2) to the save address register (3), and The copying means (62) comprises a restoring means (63) that performs processing for restoring to the execution address register (2), a writing processing means (64), and an execution processing means (65), and the copying means (62) comprises: [1] Holt state storage means (1) of the other system (B)
When a halt instruction is issued from one system (A) under the condition where 1) is a non-halt value, [2] The halt state storage means (1) of one system (A)
0) is a non-halt value and a halt instruction is issued from the other system (B), [3] The two halt state storage means (10, 11) both have a halt value and are not executed. Address register (2)
If the value of the save address register (3) is restored to the execution address register (2) under a condition where the value of is greater than or equal to the value of the save address register (3), then the execution address register is The restoring means (63) is configured to perform processing for copying the value of (2) to the save address register (3); Under the condition where the halt value is indicated and the halt state memory means (11) of the other system (B) indicates the non-halt value, the halt state memory means (10) of one system (A) indicates the non-halt value. or under a condition in which the halt state storage means (11) of the other system (B) indicates a halt value and the halt state memory means (11) of one system (A) indicates a non-halt value. Provided that the halt state storage means (11) of the other system (B) indicates a non-halt value, the value of the save address register (3) is saved to the execution address register (2).
), and when command data is sent from the system, the write processing means (64) stores the command data, the ON valid bit, and the command data issuing system. Execution processing means is configured to write the system code to the address indicated by the write address register (1) in the stack (32), and then perform processing for updating the write address register (1). (65) reads data from the address indicated by the execution address register (2) in the stack (32), and [1] If the valid bit in the read data is off,
performs processing to update the execution address register (2) and read the next data from the stack (32); [2] halt state storage means (10 or 11) specified by the system code of the read data; If indicates a halt value, update the execution address register (2) and perform processing to read the next data from the stack (32). [3] If the valid bit in the read data is If it is on and the halt state storage means (10 or 11) specified by the system code of the read data indicates a non-halt value, the process is executed based on the command data in the read data, and A stack control characterized in that it is configured to turn off a valid bit at an address indicated by an execution address register (2) after completion, and then perform processing for updating the execution address register (2). method.