JPS6159771A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS6159771A
JPS6159771A JP59180359A JP18035984A JPS6159771A JP S6159771 A JPS6159771 A JP S6159771A JP 59180359 A JP59180359 A JP 59180359A JP 18035984 A JP18035984 A JP 18035984A JP S6159771 A JPS6159771 A JP S6159771A
Authority
JP
Japan
Prior art keywords
substrate
semiconductor device
spacer
photoelectric conversion
resist film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP59180359A
Other languages
Japanese (ja)
Inventor
Toshiro Yamamoto
俊郎 山本
Shuji Watanabe
渡辺 修治
Yuichiro Ito
雄一郎 伊藤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP59180359A priority Critical patent/JPS6159771A/en
Publication of JPS6159771A publication Critical patent/JPS6159771A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657Stacked arrangements of devices
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503Stacked arrangements of devices
    • H01L2225/06513Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503Stacked arrangements of devices
    • H01L2225/06575Auxiliary carrier between devices, the carrier having no electrical connection structure
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/0002Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

PURPOSE:To attach two sheets of substrates accurately without damage by forming a spacer in such a structure that a negative resist layer is provided between the lowest and highest positive resists to the periphery of the one substrate of them. CONSTITUTION:A positive photo resist film 29A and a negative photo resist film 29B are formed to the entire part of a p type silicon substrate 21 allowing formation of n<+> type region 23 to which charges are injected. Thereafter, patterning is carried out by exposing and developing the peripheral region of film 29B having the predetermined width. Next, after forming a positive photo resist film 29C to the entire part, a spacer is formed by patterning the films 29C and 29A. A substrate 21 having the photoelectric conversion part is arranged on the fixing base, a pusher of flat plate is pressurizingly placed in contact with the rear surface of substrate 31, coupling the electrode 27 and bump 34.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、ハイブリッド型光センサと呼ばれている半導
体装置を製造するのに好適な方法に関する。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method suitable for manufacturing a semiconductor device called a hybrid optical sensor.

(従来の技術〕 第7図は従来のハイブリッド型光センサを分解して表し
た要部切断側面図である。
(Prior Art) FIG. 7 is an exploded side view of the main parts of a conventional hybrid optical sensor.

図に於いて、1及び2は光電変換部分、3はp型インジ
ウム・アンチモン(InSb)基板、4は二酸化シリコ
ン(SiOz)からなる絶縁膜、5及び6はn+型領領
域7及び8はインジウムからなるバンプ、11及び12
は電荷注入処理部分、13はシリコン(Si)基板、1
4は二酸化シリコンからなる絶縁膜、15及び16はn
+型領領域17及び18はインジウムからなるバンプを
それぞれ示している。
In the figure, 1 and 2 are photoelectric conversion parts, 3 is a p-type indium antimony (InSb) substrate, 4 is an insulating film made of silicon dioxide (SiOz), 5 and 6 are n+ type regions 7 and 8 are indium bumps consisting of 11 and 12
1 is a charge injection treated portion, 13 is a silicon (Si) substrate, and 1
4 is an insulating film made of silicon dioxide, 15 and 16 are n
+ type regions 17 and 18 respectively represent bumps made of indium.

第7図では、光電変換部分1及び2等を有する光電変換
半導体装置と電荷注入処理部分11及び12等を有する
電荷注入半導体装置とは離隔した状態で示されているが
、実際には、インジウムからなるバンプ7及び8.17
及び18に81械的圧力を加え、対応するそれぞれを結
合することに依り光電変換半導体装置と電荷注入半導体
装置の両者を貼り合わせて用いる。
In FIG. 7, the photoelectric conversion semiconductor device having the photoelectric conversion parts 1 and 2, etc. and the charge injection semiconductor device having the charge injection processing parts 11 and 12, etc. are shown separated, but in reality, the indium bumps 7 and 8.17 consisting of
By applying mechanical pressure 81 to and 18 and bonding the corresponding parts, both the photoelectric conversion semiconductor device and the charge injection semiconductor device are used.

この半導体装置の動作は良く知られているが、その概略
を説明すると、p型インジウム・アンチモン基板3の裏
面から光が入射するとn+型領領域5び6とに依り生成
されているpn接合で電荷が発生し、その電荷はインジ
ウムのバンプ7及び8.17及び18を介してn+型領
領域15び16に注入され、注入された電荷は例えば電
荷結合素子(charg6  cgupled  de
vice:ccD)等に依り転送して検出するようにし
ている。
The operation of this semiconductor device is well known, but to briefly explain it, when light enters from the back surface of the p-type indium antimony substrate 3, a pn junction formed by the n+ type regions 5 and 6 is formed. A charge is generated, and the charge is injected into the n+ type regions 15 and 16 through the indium bumps 7 and 8, 17 and 18, and the injected charge is transferred to a charge coupled device, for example.
vice:ccD) or the like for detection.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

前記説明したように光電変換半導体装置と電荷注入半導
体装置と貼り合わせる場合、それ等半導体装置の表面が
傾斜していると種々の問題を生ずる。
As described above, when a photoelectric conversion semiconductor device and a charge injection semiconductor device are bonded together, various problems occur if the surfaces of the semiconductor devices are inclined.

第8図はそのような場合を説明する為の光電変換装置並
びに電荷注入半導体装置の要部側面図である。
FIG. 8 is a side view of essential parts of a photoelectric conversion device and a charge injection semiconductor device for explaining such a case.

図に於いて、50は光電変換半導体装置、50′は電荷
注入半導体装置、51はインジウムからなるハンプをそ
れぞれ示している。
In the figure, 50 indicates a photoelectric conversion semiconductor device, 50' indicates a charge injection semiconductor device, and 51 indicates a hump made of indium.

図示されているように光電変換半導体装置5゜及び電荷
注入半導体装置50′の表面は傾斜している。
As shown, the surfaces of the photoelectric conversion semiconductor device 5° and the charge injection semiconductor device 50' are inclined.

一般に、この種の半導体装置では、特に光電変換装置側
の基板裏面を研磨して全体的に薄くすることが行われて
いるが、この際、研磨を均等に行なって、基板の厚みを
全体に亙り一定に維持する点での歩留りは甚だ低いもの
となっている。
Generally, in this type of semiconductor device, the back surface of the substrate, especially on the photoelectric conversion device side, is polished to make it thinner overall. The yield, which is maintained constant over time, is extremely low.

このように、基Fi扉裏面研磨して厚みを同一にするこ
とができない場合、結果的には表面が1頃斜しているこ
とになる。
As described above, if it is not possible to polish the back side of the Fi-base door to make the thickness the same, the result will be that the front surface is slanted.

このような状態にある両者を貼り合わせると、図に向か
って左側に位置するバンプ51は接触するが、右側に位
置するバンプ51は接触することができない旨の欠点を
生ずる。
When these two parts are bonded together in such a state, the bumps 51 located on the left side in the figure come into contact with each other, but the bumps 51 located on the right side cannot come into contact with each other.

また、右側のバンプ51が接触するように無理に貼り合
わせると、左側のバンプ51が潰れて隣接したものどう
しが接触する旨の欠点を生ずる。
Furthermore, if the bumps 51 on the right side are forcibly pasted together so that they are in contact with each other, the bumps 51 on the left side will be crushed, resulting in the disadvantage that adjacent bumps 51 will come into contact with each other.

本発明は、光電変換部分を存する基板及び電荷注入処理
部分を存する基板それぞれの表面に於ける傾斜の有無に
関係なく、それ等基板を確実に且つ損傷などを発生する
ことなく貼り合わせることができるようにする。
According to the present invention, regardless of whether or not the surfaces of the substrate including the photoelectric conversion portion and the substrate including the charge injection processing portion are inclined, the substrates can be bonded together reliably and without causing damage. Do it like this.

〔問題点を解決するための手段〕[Means for solving problems]

本発明に於ける半導体装置の製造方法では、光電変換部
分を有する基板と該光電変換部分で発生した電荷を注入
し処理する機能を持つ電荷注入処理部分を有する基板と
を結合させるに際し、少なくとも一方の基板に於ける周
辺に最下層及び最上層がポジ型レジスト膜で且つそれ等
の間に少なくとも一層のネガ型レジスト膜が介挿された
スペーサを形成し、次いで、前記基板の表面に在る軟質
金属からなるバンプに圧力を加える・ことに依り基板ど
うしを貼り合わせ、次いで、前記スペーサを除去する工
程が含まれてなるようにしである。
In the method for manufacturing a semiconductor device according to the present invention, when a substrate having a photoelectric conversion portion and a substrate having a charge injection processing portion having a function of injecting and processing charges generated in the photoelectric conversion portion are combined, at least one of the substrates is bonded to the substrate having a photoelectric conversion portion. A spacer is formed on the periphery of the substrate, the bottom layer and the top layer are positive resist films, and at least one negative resist film is interposed between them, and then a spacer is formed on the surface of the substrate. This method includes the steps of applying pressure to bumps made of soft metal, thereby bonding the substrates together, and then removing the spacer.

〔作用〕[Effect]

前記した手段を採った場合、貼り合わせる基板の表面が
傾斜していても、基板間に圧力を加えた場合、スペーサ
の作用に依り、各バンプに加わる圧力は略均−となり、
特定のバンプにのみ強圧が印加されて潰れたり、或いは
、バンプに圧力が印加されない等の事故はなくなる。
When the above-mentioned method is adopted, even if the surfaces of the substrates to be bonded are inclined, when pressure is applied between the substrates, the pressure applied to each bump will be approximately equal due to the effect of the spacer.
Accidents such as strong pressure being applied only to a specific bump and causing it to collapse, or pressure not being applied to a bump, etc., are eliminated.

〔実施例〕〔Example〕

第1図乃至第6図は本発明一実施例を解説する為の工程
要所に於ける半導体装置の要部切断側面図であり、以下
、これ等の図を参照しつつ説明する。
1 to 6 are cross-sectional side views of essential parts of a semiconductor device at key points in the process for explaining one embodiment of the present invention, and the following description will be made with reference to these figures.

第1図参照 (a)  先ず、図示のような通常の電荷注入半導体装
置を用意する。これは、この種の半導体装置を製造する
際に従来から多用されている技法で実現されるものであ
るから、その製造工程の説明は省略する。
Refer to FIG. 1(a) First, a normal charge injection semiconductor device as shown in the figure is prepared. Since this is achieved by a technique that has been widely used in the past when manufacturing this type of semiconductor device, a description of the manufacturing process will be omitted.

図に於いて、20Aはパッド部分、20Bは電荷注入部
分、21はp型シリコン基板、22は二酸化シリコンか
らなる絶縁膜、23は電荷が注入されるnゝ型領領域2
4はアルミニウム(A1)からなる電極、25はアルミ
ニウムからなる配線、26は二酸化シリコンからなるバ
ッシベーション膜、27はアルミニウムからなる電極、
28はアルミニウムからなる電極をそれぞれ示している
。尚、図示されていないが、基板21には、前記構成の
外、n+型領領域23注入された電荷を転送して検出す
る例えばインクライン型COD等、電荷を処理する部分
が付加されているものであり、これ等を電荷注入処理部
分を有する基板と定義する。
In the figure, 20A is a pad portion, 20B is a charge injection portion, 21 is a p-type silicon substrate, 22 is an insulating film made of silicon dioxide, and 23 is an n-type region 2 into which charges are injected.
4 is an electrode made of aluminum (A1), 25 is a wiring made of aluminum, 26 is a passivation film made of silicon dioxide, 27 is an electrode made of aluminum,
Reference numeral 28 indicates electrodes made of aluminum. Although not shown in the drawings, in addition to the above-mentioned structure, the substrate 21 is provided with a charge processing part, such as an incline type COD, which transfers and detects the charge injected into the n+ type region 23. These are defined as substrates having a charge injection treated portion.

第2図参照 (bl  全面にポジ型フォト・レジスト膜29Aを厚
さ約2〔μm〕程度に、また、ネガ型フォト・レジスト
膜29Bを厚さ約8〔μm〕程度に形成する。
Refer to FIG. 2 (bl) A positive photoresist film 29A is formed on the entire surface to a thickness of about 2 [μm], and a negative photoresist film 29B is formed to a thickness of about 8 [μm].

本発明を実施するには、厚さ約10〔μm〕程度のフォ
ト・レジスト膜からなるスペーサを必要とするが、その
ように厚いフォト・レジスト膜を一度に形成することは
不可能に近いほど困難である。
To carry out the present invention, a spacer made of a photoresist film with a thickness of about 10 [μm] is required, but it is almost impossible to form such a thick photoresist film at once. Have difficulty.

従って、フォト・レジスト膜を積層することが必要とな
るが、一般に、ポジ型フォト・レジストは例えばアセト
ンを用いることに依り簡単に溶解して除去することが可
能である為、それを用いることは好ましいが、フォト・
レジスト膜を積層して厚さを稼ぐ場合、ネガ型フォト・
レジスト膜を併用するとパターニングする場合に有効で
ある。
Therefore, it is necessary to stack a photoresist film, but in general, it is not possible to use a positive photoresist because it can be easily dissolved and removed using, for example, acetone. Preferably, photo
When increasing the thickness by laminating resist films, negative photo
It is effective for patterning when a resist film is used in combination.

(C)  ネガ型フォト・レジスト膜29Bをパターニ
ングする為、記号DRIで指示しである部分、即ち、ネ
ガ型フォト・レジストIt!29Bに於ける所定幅の周
辺領域を露光する。
(C) In order to pattern the negative photoresist film 29B, the portion indicated by the symbol DRI, that is, the negative photoresist It! A peripheral area of a predetermined width at 29B is exposed.

第3図参照 (d+  現像を行うとネガ型フォト・レジスト膜29
Bがパターニングされる。
Refer to Figure 3 (d+ After development, the negative photoresist film 29
B is patterned.

(Ill  全面にポジ型フォト・レジスト膜29Cを
厚さ約1 〔μm〕程度に形成する。
(Ill) A positive photoresist film 29C is formed on the entire surface to a thickness of about 1 [μm].

(fl  ポジ型フォト・レジスト膜29G及びポジ型
フォト・レジスト膜29Aをパターニングする為、記号
DR27指示しである部分を露光する。
(fl In order to pattern the positive photoresist film 29G and the positive photoresist film 29A, a portion indicated by the symbol DR27 is exposed to light.

第4図参照 ((イ)現像を行うとポジ型フォト・レジスト膜29C
及び29Aがパターニングされてスペーサが完成する。
See Figure 4 ((a) After development, a positive photoresist film 29C
and 29A are patterned to complete the spacer.

前記したように、ボン型フォト・レジスト膜29A及び
29Cとネガ型フォト・レジスト膜29Bとをサンドイ
ンチ構造状に積層すると充分に厚いスペーサが得られ、
しかも、パターニングする場合には、比較的薄いフォト
・レジスト膜を順にパターニングすれば良いから、厚い
フォト・レジスト膜をパターニングする場合のようにパ
ターンが崩れるなどの戊はない。
As described above, by laminating the Bon type photoresist films 29A and 29C and the negative type photoresist film 29B in a sandwich structure, a sufficiently thick spacer can be obtained.
Furthermore, when patterning, relatively thin photoresist films can be patterned one after another, so there is no possibility of the pattern being disrupted, which is the case when patterning a thick photoresist film.

第5図参照 (hl  図示のような通常の光電変換半導体装置を用
意する。これは、前記電荷注入半導体装置と同様、この
種の半導体装置を製造する際に従来から多用されている
技法で実現されるものであるから、その製造工程の説明
は省略する。
See Figure 5 (hl) A normal photoelectric conversion semiconductor device as shown in the figure is prepared.This is realized by a technique that is conventionally widely used when manufacturing this type of semiconductor device, similar to the charge injection semiconductor device described above. Therefore, a description of the manufacturing process will be omitted.

図に於いて、31はp型InSb基板、32は二酸化シ
リコンからなる絶縁膜、33はp型InSb基板31と
の間に光電変換を行うpn接合を生成する為のn+型領
領域34はInからなるバンプをそれぞれ示している。
In the figure, 31 is a p-type InSb substrate, 32 is an insulating film made of silicon dioxide, and 33 is an n+ type region 34 for creating a pn junction for photoelectric conversion between the p-type InSb substrate 31 and the p-type InSb substrate 31. Each bump is shown in the figure.

尚、この構成を備えてなる基板を光電変換部分を有する
基板と定義する。
Note that a substrate having this configuration is defined as a substrate having a photoelectric conversion portion.

(11前記電荷注入処理部分を有する基板と前記光電変
換部分を有する基板とを図示のように対向させ、矢印に
見られるように押圧力を加えて電極27とバンプ34と
を結合させる。
(11) The substrate having the charge injection treated portion and the substrate having the photoelectric conversion portion are faced to each other as shown in the figure, and a pressing force is applied as shown by the arrow to bond the electrode 27 and the bump 34.

この場合、例えば基板21は固定台上に配置し、基板3
1の裏面に平板状の押圧子を当接して押圧力を加えるが
、その押圧子の裏面には、例えばスプリングが配設され
ていて、基板21或いは31の表面に傾斜が存在しても
、その傾斜はスプリングで吸収され、基板31の裏面を
略均等に押圧できるようになっている。
In this case, for example, the substrate 21 is placed on a fixed table, and the substrate 3
A flat presser is brought into contact with the back surface of the substrate 21 or 31 to apply a pressing force. For example, a spring is disposed on the back surface of the presser, and even if there is an inclination on the surface of the substrate 21 or 31, The inclination is absorbed by the spring, and the back surface of the substrate 31 can be pressed almost evenly.

即ち、基板21或いは31の表面に傾斜が在る場合に於
いて、押圧子で基板31の裏面を押圧すると、最初、基
板21或いは31の厚くなっている部分に存在するバン
プ34が電極27と当接し、バンプ34が若干圧潰され
た状態で基板31がスペーサ表面に当接する。
That is, when the surface of the substrate 21 or 31 has an inclination, when the back surface of the substrate 31 is pressed with a presser, the bumps 34 existing on the thicker portion of the substrate 21 or 31 will first be connected to the electrodes 27. The substrate 31 comes into contact with the spacer surface in a state where the bumps 34 are slightly crushed.

更に、押圧力を加えると、基板31がスペーサ表面に当
接した部分では最早押圧子が進行することはできず、前
記押圧力は前記スプリングを変形させる働きをするが、
基板21或いは31の薄くなっている部分では、押圧子
の力が基板31を有効に押圧するので、今度は、その部
分に存在するバンプ34が電極27と当接して結合する
ことになり、その場合に於けるバンプ34の若干の圧潰
は、その近傍にあるスペーサの表面に基板31が当接し
た際に停止される。
Furthermore, when a pressing force is applied, the presser can no longer advance in the portion where the substrate 31 contacts the spacer surface, and the pressing force acts to deform the spring;
At the thinner portion of the substrate 21 or 31, the force of the presser effectively presses the substrate 31, so the bumps 34 present at that portion come into contact with and bond with the electrode 27, and the In this case, the slight crushing of the bump 34 is stopped when the substrate 31 comes into contact with the surface of the spacer in the vicinity.

このようにして電極27及びバンプ34の結合が全面に
亙り行われ、基板21及び基板31の貼り合わせが完了
する。
In this way, the electrodes 27 and the bumps 34 are bonded over the entire surface, and the bonding of the substrates 21 and 31 is completed.

第6図参照 0)  フォト・レジスト膜29A乃至29Cからなる
スペーサを除去することに依り半導体装置を完成させる
(See FIG. 6 0) The semiconductor device is completed by removing the spacers made of photoresist films 29A to 29C.

この場合、最下層並びに最上層としては溶解・除去が容
易であるポジ型フォト・レジスト膜29A及び29Cで
構成されている為、その除去に特殊な溶解液を必要とす
るネガ型フォト・レジスト膜29Bを積層してあっても
、例えば、アセトン中に浸漬して最下層及び最上層を溶
解することに依り、スペーサ全体を簡単に除去すること
ができる。
In this case, since the bottom layer and the top layer are composed of positive photoresist films 29A and 29C that are easy to dissolve and remove, a negative photoresist film that requires a special solution to remove them. Even if 29B is stacked, the entire spacer can be easily removed by, for example, dipping it in acetone to dissolve the bottom and top layers.

前記実施例では、スペーサをポジ型フォト・レジスト膜
29A1ネガ型フオト・レジスト膜29B、ポジ型フォ
ト・レジスト膜29Gを用いて構成したが、これは最下
層と最上層がポジ型フォト・レジスト膜でありさえすれ
ば、その間はネガ型フォト・レジスト膜とポジ型フォト
・レジスト膜の多層に構成しても良い。尚、それ等フォ
ト・レジスト膜の厚み、即ちスペーサの厚みはバンプ3
4との兼ね合いで決定されることは云うまでもない。
In the above embodiment, the spacer was constructed using the positive photoresist film 29A, the negative photoresist film 29B, and the positive photoresist film 29G. As long as this is true, the gap between them may be composed of multiple layers of a negative type photoresist film and a positive type photoresist film. In addition, the thickness of the photoresist film, that is, the thickness of the spacer is the same as bump 3.
Needless to say, the decision will be made in consideration of 4.

また、前記実施例に於けるバンプ34は光電変換部分を
有する基板側にのみ形成したが、これは電荷注入処理部
分を有する基板側に形成しても良いし、或いは、両方の
基板に形成しても良い。
Furthermore, although the bumps 34 in the above embodiments were formed only on the substrate side having the photoelectric conversion portion, they may be formed on the substrate side having the charge injection processing portion, or they may be formed on both substrates. It's okay.

更に、前記実施例では、光電変換部分を有する基板とし
て、pn接合を有するInSb基板を用いたが、他に、
サファイア板に接着された極薄いInSb基板、或いは
、カドミウム(Cd)  ・テルル(Te)板の上にエ
ピタキシャル成長して作られた水SFa (Hg)Cd
−Te基板などを用いることができる。
Furthermore, in the above embodiment, an InSb substrate having a pn junction was used as the substrate having the photoelectric conversion portion, but in addition,
Water SFa (Hg)Cd made by epitaxial growth on an extremely thin InSb substrate bonded to a sapphire plate or a cadmium (Cd)/tellurium (Te) plate.
-Te substrate or the like can be used.

〔発明の効果〕〔Effect of the invention〕

本発明に於ける半導体装置の製造方法では、光電変換部
分を有する基板と翼誉光電変換部分で発生した電荷を注
入し処理する機能を持つ電荷注入処理部分を有する基板
とを結谷させるに際し、少なくとも一方の基板に於ける
周辺に最下層及び最上層がポジ型レジスト膜で且つそれ
等の間に少なくとも一層のネガ型レジスト膜が介挿され
たスペーサを形成し、次いで、前記基板の表面にある軟
質金属からなるバンプに圧力を加えることに依り基板ど
うしを貼り合わせ、次いで、前記スペーサを除去する工
程が含まれている。
In the method for manufacturing a semiconductor device according to the present invention, when bonding a substrate having a photoelectric conversion portion and a substrate having a charge injection processing portion having a function of injecting and processing charges generated in the photoelectric conversion portion, A spacer is formed around at least one of the substrates, the bottom layer and the top layer are positive resist films, and at least one negative resist film is interposed between them, and then a spacer is formed on the surface of the substrate. The process includes the steps of bonding the substrates together by applying pressure to a bump made of a certain soft metal, and then removing the spacer.

このようにすると、基板の厚みが一様でない場合であっ
ても、基板間に圧力を加えた場合、スペーサの作用に依
り、各バンプに加わる圧力は略均等になり、特定のバン
プにのみ強圧が印加されることに依り潰れて隣接バンブ
に接触したり、或いは、バンプに印加される押圧力が不
充分で結合不良になる等の事故はなくなり、製造歩留り
は著しく向上する。しかも、フォト・レジスト膜を積層
して構成したスペーサは最下層と最上層が容易に溶解す
るポジ型フォト・レジ・スト膜になっているから、例え
ば、アセトン中に浸漬することに依り簡単に除去するこ
とができるので、零発りnの実施は極めて容易である。
In this way, even if the thickness of the substrate is not uniform, when pressure is applied between the substrates, the pressure applied to each bump will be approximately equal due to the effect of the spacer, and strong pressure will only be applied to specific bumps. Accidents such as the bumps collapsing due to the application of bumps and coming into contact with adjacent bumps, or insufficient pressing force being applied to the bumps resulting in poor bonding, etc., are eliminated, and the manufacturing yield is significantly improved. Moreover, since the spacer is constructed by laminating photoresist films, the bottom layer and the top layer are positive photoresist films that easily dissolve. Since it can be removed, the implementation of n starting from zero is extremely easy.

【図面の簡単な説明】[Brief explanation of drawings]

第1図乃至第6図は本発明一実施例を説明する為の工程
要所に於ける半導体装置の要部切断側面図、第7図は従
来例を説明する為の半導体装置の要部切断側面図、第8
図は基板を貼り合わせた場合の問題点を説明する為の半
導体装置の要部側面図をそれぞれ表している。 図に於いて、20Aはパッド部分、20Bは電荷注入部
分、21はp型シリコン基板、22は二酸化シリコンか
らなる絶縁膜、23はn 4s型領域、24はアルミニ
ウムからなる電極、25はアルミニウムからなる配線、
26は二酸化シリコンから9A及び29Cはポジ型フォ
ト・レジスト膜、29Bはネガ型フォト・レジスト膜、
31はp型InSb基板、32は二酸化シリコンからな
る絶縁膜、33はn+型領領域34はバンプをそれぞれ
示している。 特許出願人   富士通株式会社 代理人弁理士  相 谷 昭 司 代理人弁理士  渡 邊 弘 − 第1図 第2工 笛3図 9C 20A          20B 第5図 W−ノ 0A20B 第7図 第8図
1 to 6 are cross-sectional side views of essential parts of a semiconductor device at key points in the process for explaining one embodiment of the present invention, and FIG. 7 is a cross-sectional side view of essential parts of a semiconductor device for explaining a conventional example. Side view, No. 8
Each figure shows a side view of a main part of a semiconductor device to explain problems when bonding substrates together. In the figure, 20A is a pad portion, 20B is a charge injection portion, 21 is a p-type silicon substrate, 22 is an insulating film made of silicon dioxide, 23 is an n4s type region, 24 is an electrode made of aluminum, and 25 is made of aluminum. wiring,
26 is silicon dioxide, 9A and 29C are positive photoresist films, 29B is a negative photoresist film,
31 is a p-type InSb substrate, 32 is an insulating film made of silicon dioxide, and 33 is an n+ type region 34 which is a bump. Patent Applicant Fujitsu Ltd. Representative Patent Attorney Akira Aitani Representative Patent Attorney Hiroshi Watanabe - Figure 1 Figure 2 Flute 3 Figure 9C 20A 20B Figure 5 W-0A20B Figure 7 Figure 8

Claims (1)

【特許請求の範囲】[Claims] 光電変換部分を有する基板と該光電変換部分で発生した
電荷を注入し処理する機能を持つ電荷注入処理部分を有
する基板とを結合させるに際し、少なくとも一方の基板
に於ける周辺に最下層及び最上層がポジ型レジスト膜で
且つそれ等の間に少なくとも一層のネガ型レジスト膜が
介挿されたスペーサを形成し、次いで、前記基板の表面
に在る軟質金属からなるバンプに圧力を加えることに依
り基板どうしを貼り合わせ、次いで、前記スペーサを除
去する工程が含まれてなることを特徴とする半導体装置
の製造方法。
When bonding a substrate having a photoelectric conversion portion and a substrate having a charge injection processing portion having a function of injecting and processing charges generated in the photoelectric conversion portion, a bottom layer and a top layer are formed around the periphery of at least one of the substrates. is a positive resist film and at least one negative resist film is interposed between the spacers, and then by applying pressure to bumps made of soft metal on the surface of the substrate. A method for manufacturing a semiconductor device, comprising the steps of bonding substrates together and then removing the spacer.
JP59180359A 1984-08-31 1984-08-31 Manufacture of semiconductor device Pending JPS6159771A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP59180359A JPS6159771A (en) 1984-08-31 1984-08-31 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59180359A JPS6159771A (en) 1984-08-31 1984-08-31 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPS6159771A true JPS6159771A (en) 1986-03-27

Family

ID=16081864

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59180359A Pending JPS6159771A (en) 1984-08-31 1984-08-31 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS6159771A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH11287862A (en) * 1998-02-09 1999-10-19 Sharp Corp Two-dimensional image detector and its manufacture

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH11287862A (en) * 1998-02-09 1999-10-19 Sharp Corp Two-dimensional image detector and its manufacture

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