JPS6159555A - Method for controlling data transfer of multiple hierarchical storage device - Google Patents

Abstract

PURPOSE:To reduce the overhead by transmitting an address of data required for middle order and high order hierarchical storage devices and a processor in a low order hierarchical storage device and transferring previously data necessary for each device according to the priority of the high order device. CONSTITUTION:A word address part W of an address register 6 is given to a data transmission control part 12. The control part 12 includes a counter means of an adder 122 and register 121 like an address control part 10, control the transmission sequence of a word address of from word data stored in a write data register 11 according to a specified rule by action timing of an action control part 7 and gives the selected signal to a data selection part 13. The selection part 13 gives selected word data of a data transfer register 14 and transfers them to a middle order hierarchical level 2 storage device WS3. Thereafter, the required data is transfered into a processor IP1 through a level 1 storage device BS2 of a high order hierarchical storage device.

Description

[Detailed Description of the Invention] [Field of Application of the Invention] The present invention relates to a storage device for an information processing system, and in particular, in a multi-tier storage device, data transfer from a lower tier storage device connected with a relatively small data transfer width is possible. The present invention relates to a data transfer control method suitable for reducing read overhead.

[Background of the invention]

Conventionally, as a method to improve the speed difference between a processing device and a main memory in an information processing system, a small-capacity, high-speed buffer storage (upper tier storage) is provided on the processing device side, and the buffer storage and main memory are A multi-tier storage device is known in which a medium-speed, medium-capacity work storage (medium-tier storage device) is provided between the two devices.

In this case, the main storage device is positioned as a lower hierarchy storage device. In such a multi-tier storage device, if a copy of the data requested by the processing device is not registered in either the upper or middle tier storage device.

The problem is the overhead of reading data from a lower tier storage device and transferring it to an upper tier storage device via a middle tier storage device.

As a method for reducing the overhead when reading data from a lower layer storage device of a multilayer storage device, as shown in Japanese Patent Publication No. 57-57782, for example, a middle layer storage device is provided with data register means, Selects the data to be transferred to the upper hierarchy storage device from among the data read out in parallel from the lower hierarchy storage device, sets it in the data register means, and transfers the data set in the data register means to the upper hierarchy storage device. Are known. However, according to this method, it is necessary to make the data transfer width for parallel reading between the lower and middle tier storage devices equal to or greater than the unit data transfer amount of the middle and upper tier storage devices. Therefore.

When the unit data transfer amount between the middle and upper tier storage devices is large, the amount of data transferred between the lower and middle tier storage devices becomes large, which eliminates the disadvantage that the number of data transfer lines increases.

Furthermore, there is a drawback that the number of storage units that operate in parallel within the lower tier storage device increases, making it difficult to increase the storage capacity.

[Purpose of the invention]

It is an object of the present invention to make the data transfer width between the lower and middle tier storage devices smaller than the unit data transfer amount between the middle and upper tier storage devices, and to reduce read overhead from the lower tier storage devices. The object of the present invention is to provide a multi-tiered storage device.

[Summary of the invention]

A feature of the present invention is that in addition to the address of data required by the middle-level storage device, the address of data required by the upper-level storage device and processing device is transmitted to the lower-level storage device, and The reason is that data required by each device is sent out in advance with priority, reducing overhead.

[Embodiments of the invention]

Hereinafter, one embodiment of the present invention will be described in detail with reference to the drawings.

FIG. 1 shows an embodiment of a multi-tiered storage device according to the present invention, and in particular shows in detail an example of the internal configuration of a lower-tiered storage device that forms the center of the invention.6 FIG.
Processing device (hereinafter referred to as IP) 1
Level 2 storage device (hereinafter referred to as BS) which is an upper layer storage device connected to 2. It is composed of a level 2 storage device (hereinafter referred to as WS) 3 which is a medium tier storage device connected to BS2 and a level 3 storage device @ (hereinafter referred to as MS) 4 which is a lower tier storage device connected to WS3.

MSll is a startup register 5 that receives a startup signal from WS3.
．． an address register 6 that receives an address signal accompanying the activation signal; an operation control section 7 that controls the operation of the MS 4 according to requests from the activation register 5; Storage unit 8 for storing data.
An address control unit 10 that controls the order of accessing parts of the storage unit 8 based on the information in the address register 6 and generates address signals, and a read register 11 that stores data read from the storage unit 8. address register 6
Data transmission control unit 12 controls the order in which data in the read register 11 is selected based on the information from the operation control unit 7 and generates a 1 selection signal. This selection signal selects the data in the read register 11. Data selection section 1
3. Consists of data transfer register 1/l that transfers selected data to WS3.

FIG. 2 shows the correspondence of data that is transmitted between each storage device in the configuration shown in FIG. 1. The unit data transfer amount transferred from MSll to WS3 is 1 line, the unit data transfer amount transferred from WS3 to BS2 is 1 block, and from BS2 to IPI
The amount of low-order data transferred to is defined as 1 word (for example, 8 bytes).

The relationship between the amounts of data at each lower level is 1 line>1 block>1 word, and in this embodiment, the relationship is 16:4:1.

Now, IPI needs the data of word W2.

If the data is not present in BS2 or even WS3, a data read command is issued to MS'l.

Upon receiving the data read command, MSll reads line LO containing word W2 and transfers it to ws3. Below, W
S3 transfers block [31 containing word W21 to 32, and BS2 transfers word W2 to IPI.

Here, if the data line from MS/l to WS3, that is, the data transfer width is equal to or larger than the data amount of one block, MS4 is connected to block B containing at least word W2.
The WS3, which has received the block B1 by reading and transferring the block B1 in advance, can reduce the read overhead by transferring the block B1 to the BS2 with the word W2 required by the IPI in advance. In this case, the address information given to MS4 is the IPI or the line address and block address containing the required word w2.

However, according to this method, the larger the definition of the amount of data in one block, the larger the data transfer width between MS4 and WS3, the larger the number of data lines, and the larger the number of storage units that perform read operations in parallel. Put it away.

The former will cause problems in implementation, and the latter will cause problems in units of storage capacity expansion.

In the present invention, the address information given to the MS4 is a line address, a block address, and a word address, and the addresses of words 1 to W2 required by the TPI are also instructed to the MS4. In response to this, the MS4 controls the block B1 containing the word W2 required by the IPI, and the word W2 within the same block B1 to be read out and transferred in advance. Therefore, the data transfer width of MS/1 and WS3 only needs to be at least one word wide. In the embodiment of FIG. 1, the width is l words.

Figure 3 shows how the data in Figure 2 is transferred from MS4 to WS according to the present invention.
3 shows the order of transfer. That is, the data transfer width DW (
1 word width), the word W2 required by the IPI and the block B1 required by the BS2 are transferred in advance in the upward direction T of the transfer order. Moreover, since there is a high probability that the next word that IPI will need with respect to the word W2 that IPI currently needs is generally a word at a consecutive address, within block Bl.

After word W2, word W3 is transferred, wrapping around in the direction of increasing word address. Similarly, in the line LO including block B1, block B2 is transferred after block B1. Furthermore, in block B2, word WO+4 whose address is as close as possible to the word address in block Bl
be transferred first.

The control operation in this embodiment shown in FIG. 1 will be explained below.

First, in the case of this embodiment, since the data transfer width between MS4 and WS3 is 1 word, basically the memory section 8 to be operated in parallel only needs to be 1 word wide, and it can be operated multiple times. That's fine. but.

Generally, depending on the performance of the storage unit 8, there will be gaps in data transfer between each operation. As a method of minimizing this free space, it is desirable to use the memory elements of the memory section 8 in operations such as page mode. Further, in the case of this embodiment, the storage section 8 is operated in parallel with a width of 4 words (1 block width), and is controlled to transfer one word at a time so that no empty data transfer occurs.

Now, the data required by IPI is BS2 and even WS.
3, the read request from IPI is sent to BS2.
．． WS3. Then, it is transmitted to the MS 4, and the activation request is stored in the activation register 5 and the address is stored in the address register 6. The address register 6 is formed by a line address section, a block address section B, and a word address section W.

Based on the upper bits of the line address part, the access selection section 9 selects the storage element in the storage section 8 that includes the line using the selection signal SO or S1. The lower bits of the line address part are given to the storage element as address AO in order to select the line. Further, eight parts of the block address are given to the address control section 10. The address control unit 10 includes a register 101 and a counter means of an adder 102,
Based on the operation timing of the operation control unit 7, the order in which the memory elements are operated in parallel multiple times (block address order) is controlled according to the rules described in 5 above, and the address A1 is assigned to the memory element.
I can get it.

On the other hand, due to the read request stored in the 9 activation register 5,
The operation control unit 7 generates timing for operating the storage unit 8 and the like, and provides timing No. 43 T to the storage element 801.

Thus, the storage unit 8 operates.

The read data (1 block width: 11 words) is stored in the read data register 11.

On the other hand, the word address section W of the address register section 6 is sent to the data transmission control section 12. The data transmission control section 12 includes a counter means of a register 121 and an adder 122 like the address control section 1o, and according to the operation timing of the operation control section 7, the data (4 words) stored in the read data register 11 according to the above-mentioned rules is ) and supplies the selection signal to the data selection section 13. The data selection unit 13 provides the selected data (1 word) to the data transfer register 14 and transfers it to the WS3. Thereafter, the requested data is transferred to the IPI via a data transfer path as shown in FIG.

According to this embodiment, while reducing read overbed, the data transfer width between MS4 and WS3 can be reduced between WS3 and BS2.
This has the effect of making it smaller than the low-level data transfer amount during the period.

In addition, in MS4, the data width for parallel operation is
This has the effect of making it smaller than the unit data transfer amount between WS3 and WS3.

In the embodiment shown in FIG. 1, one block of the storage section 8 is operated in parallel, but a plurality of blocks may be operated in parallel.
In that case, the block address part B is divided and a part is given to the address control part 10 and the rest to the data transfer control part 12,
Similar control can be easily realized.

In addition, as another embodiment, the data width to be read in parallel in the MS4 is one line, the number of parallel operations is one, and the block address part B and word address part W of the address register 6 are given to the data sending control part 12, The data transmission control unit 12 may control the block transfer order and the word transfer order in the same manner as in the above-described embodiment.

According to this embodiment, although it does not have the effect of reducing the data width that is operated in parallel in the MS4, it has the effect of reducing the number of interface lines and also reduces the operating time of the storage unit 8, so that other operation requests to the MS4 can be reduced. can be processed at high speed.

〔Effect of the invention〕

According to the present invention, in a multi-tier storage device, the data transfer line between the lower and middle tier storage devices can be made smaller than the unit data transfer amount between the middle and upper tier storage devices, and the read overhead can be reduced. can get. Furthermore, an effect can be obtained in which the storage capacity expansion cost of the lower tier storage device can be reduced.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an embodiment of a multi-tiered storage device according to the present invention, FIG. 2 is a conceptual diagram of data transfer in a three-tiered storage device, and FIG. 3 is a diagram showing an example of the order of data transfer according to the present invention. be. ■...Processing unit (IP), 2...Level 1 storage device (BS), 3...Level 2 storage device (WS)
), 4... Level 3 storage device (MS), 5...
Start register, 6...Address register, 7
...Operation control section, 8.Storage section, 9.Access selection section, 10.Address control section, 11.
...Read register, 12...Data sending control section, 13...Data selection section, 14...Data transfer register.

Claims (1)

[Claims] (1) Consists of at least level 1, 2, and 3 storage devices, with the level 3 storage device having the largest capacity and slowest speed, and the level 1 storage device having the smallest capacity and fastest speed, and one copy of the level 3 storage device. In a multi-tiered storage device in which a level 2 storage device has a copy of a copy of the level 2 storage device and a level 1 storage device has a copy of the level 2 storage device, data is read from level 3 and transmitted via the level 2 and 1 storage devices. When transferring data to a processing device, in addition to the address of the data required by the level 2 storage device, the address of the data required by the level 1 storage device and the processing device is transmitted to the level 3 storage device. Data transfer in a multi-tiered storage device, characterized in that data to be transferred to a level 1 storage device via a level 1 storage device and data to be transferred from a level 1 storage device to a processing device are sent in advance. control method.