JPS6158279A - Electrostatic induction type semiconductor photodetector - Google Patents

Electrostatic induction type semiconductor photodetector

Info

Publication number
JPS6158279A
JPS6158279A JP59179982A JP17998284A JPS6158279A JP S6158279 A JPS6158279 A JP S6158279A JP 59179982 A JP59179982 A JP 59179982A JP 17998284 A JP17998284 A JP 17998284A JP S6158279 A JPS6158279 A JP S6158279A
Authority
JP
Japan
Prior art keywords
region
gate
resistance layer
high resistance
layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP59179982A
Other languages
Japanese (ja)
Other versions
JPH0682859B2 (en
Inventor
Junichi Nishizawa
潤一 西澤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Semiconductor Research Foundation
Original Assignee
Semiconductor Research Foundation
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Filing date
Publication date
Application filed by Semiconductor Research Foundation filed Critical Semiconductor Research Foundation
Priority to JP59179982A priority Critical patent/JPH0682859B2/en
Publication of JPS6158279A publication Critical patent/JPS6158279A/en
Publication of JPH0682859B2 publication Critical patent/JPH0682859B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/08Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof in which radiation controls flow of current through the device, e.g. photoresistors
    • H01L31/10Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof in which radiation controls flow of current through the device, e.g. photoresistors characterised by potential barriers, e.g. phototransistors
    • H01L31/101Devices sensitive to infrared, visible or ultraviolet radiation
    • H01L31/112Devices sensitive to infrared, visible or ultraviolet radiation characterised by field-effect operation, e.g. junction field-effect phototransistor
    • H01L31/1127Devices with PN heterojunction gate
    • H01L31/1129Devices with PN heterojunction gate the device being a field-effect phototransistor

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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Electromagnetism (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Junction Field-Effect Transistors (AREA)
  • Light Receiving Elements (AREA)

Abstract

PURPOSE:To perform a detection of light by a method wherein the high-resistance regions between the gates and the drain are made narrower their forbidden band widths than that of the drain region, the sensitivity of the avalanche photo diode to the light of a long wavelength is increased, the optical amplification degree at the SIT part is increased, and furthermore, a function equivalent to the operation of the SCR, which is generated due to the forbidden band gap difference between the high-resistance regions and the drain, is let the photodetector have. CONSTITUTION:An n<+> type layer 21 and an n<-> type layer 24 are both an InGaAs layer, but the forbidden band widths thereof are wider than that of the InP layer of an n<-> the layer 22. p<+> type InP layers 25 are used as the gates of the photo SIT and an n<+> type InP layer 28 is used as the source of the SIT. The whole surface is covered with an insulative optical reflection preventing film 26, and Au-Zn-Ni electrodes 27 and Au-Ge-Ni electrodes 29 and 20 are attached. Each dimension and concentration of the layers 24 and 22 are selected and the layers 24 and 22 are made to deplete with voltage between the electrodes 27 and 29 and voltage between the electrodes 27 and 29 and the electrode 20 and the respective height of the potential barriers, which are generated in the layers 24 and 22 held between the gates 25, is made to change by the effect of the SIT. Moreover, when the dimension, voltage and impurity concentration are selected in such a way that an avalanche electric field is applied to the layer 22, the light of a long wavelength is received by the avalanche photo diode at a high speed and a high sensitivity, and furthermore, signal is amplified at the SIT part.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は静電誘導トランジスタを原理とする高速・高感
度な光検出器に関し、特に長波長感度が向上することか
ら、長波長光通信用高速・高感度な光検出器として利用
されるものである(従来技術) 従来型光検出器として特に本発明に近いものとして、静
電誘導ホトトランジスタがある。
[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a high-speed and highly sensitive photodetector based on an electrostatic induction transistor, and is particularly suitable for long-wavelength optical communication because the long-wavelength sensitivity is improved. Used as a High-Speed and High-Sensitivity Photodetector (Prior Art) As a conventional photodetector that is particularly close to the present invention, there is an electrostatic induction phototransistor.

例えば特願昭56−192417号「半導体光電変換装
置」)静電誘導ホトトランジスタは、ゲートのまわりに
分布するp −1−nダイオードを光検出部とする。n
チャンネルを例にとると光によって発生した電子正孔対
のうち正孔はp中ゲート領域に蓄積されるため、ゲート
の電位変化を引き起し、これによってチャンネル中の電
位障壁高さが変調されるため、ソース・ドレイン間を流
れる増幅電流がこのゲート電位変化で変調されるという
ものである。その光増幅度は非常に高く、しかも入射光
強度が微弱であれば微弱であるほど高いという、従来型
バイポーラホトトランジスタとは全く逆の特性がが得ら
れる。その最大光増幅度G mg、tは近似的にで現さ
れる。ここでnj  i、in” ソース領域の不純物
密度、p、cTはp“ ゲート領域の不純物密度、D6
は電子の拡散定数、DF7は正孔の拡散定数、W9は電
位障壁の実効的な厚さ、L7yは正孔の拡散距離、qは
単位電荷層、Kはボルツマン定数、Tは絶対温度、■。
For example, an electrostatic induction phototransistor (Japanese Patent Application No. 56-192417 ``Semiconductor Photoelectric Conversion Device'') uses p -1-n diodes distributed around the gate as a photodetector. n
Taking a channel as an example, holes among the electron-hole pairs generated by light are accumulated in the gate region during p-mode, causing a change in the gate potential, which modulates the potential barrier height in the channel. Therefore, the amplified current flowing between the source and drain is modulated by this gate potential change. The optical amplification factor is extremely high, and the weaker the incident light intensity, the higher the optical amplification, which is the complete opposite of that of conventional bipolar phototransistors. The maximum optical amplification degree G mg,t is approximately expressed as. where nj i,in'' is the impurity density in the source region, p, cT is p'' is the impurity density in the gate region, D6
is the electron diffusion constant, DF7 is the hole diffusion constant, W9 is the effective thickness of the potential barrier, L7y is the hole diffusion distance, q is the unit charge layer, K is Boltzmann's constant, T is the absolute temperature, ■ .

1crffはゲート・ソース間p1nダイオードの拡散
電位、V bic4”Jはソースからみた電位障壁高さ
ピークの高さである。
1crff is the diffusion potential of the p1n diode between the gate and source, and Vbic4''J is the peak height of the potential barrier as seen from the source.

その一般的な構造の一例を第2図に示す。n+暴根板6
0上形成されたn−もしくはp−の高抵抗11161中
に拡散されたp中領域62がゲート62間であり、n?
領域67はソースもしくはドレイン領域を示す。n中基
板60はドレインもしくはソース領域である。64及び
65はそれぞれゲート電極、ソースもしくはドレイン電
極を示す。63は絶縁物である。入射光hνによって侵
入した光は主としてn−高抵抗層61中において電子・
正孔対を発生させる。この正孔がp+ゲート領域62に
蓄積されることから主電極65及び66間に増幅信号が
得られる。
An example of its general structure is shown in FIG. n + wild root board 6
The p medium region 62 diffused into the n- or p- high resistance 11161 formed on the 0 is between the gates 62, and the n?
Region 67 represents the source or drain region. The n-type substrate 60 is a drain or source region. 64 and 65 represent a gate electrode, source or drain electrode, respectively. 63 is an insulator. The light penetrating by the incident light hν mainly generates electrons in the n-high resistance layer 61.
Generates hole pairs. Since these holes are accumulated in the p+ gate region 62, an amplified signal is obtained between the main electrodes 65 and 66.

n−高抵抗層中には電位障壁が形□成されるべく、D”
ゲート62間の寸法、不純物密度及びn−111161
の寸法、不純物密度は選ばれている。従来型構造におい
ては高抵抗111[i域n−61の半導体の禁制帯幅と
p+ゲート領11162及びn++板60を形成する半
導体の禁制帯幅は全て同じである。すなわち、はぼ全て
の領域は同一半導体で形成されることが多い。一部、ペ
テロ接合をゲート領域もしくはソース領域に設ける静電
誘導トランジスタの例がある。この場合、ゲート領域6
2の半導体をチャンネル領域の半導体に比べ禁制帯幅の
広いもので形成すると、ゲート62及びチャンネルn−
61の接合界面にはヘテロ接合が生ずる。ゲートのみ禁
制帯幅の広い半導体で形成するだけで、他の領域は同一
半導体とすると、そのヘテロ接合界面における電位差分
だけ積算された形で電流増幅率は上昇する。すなわち、
ヘテロ界面における電位差分が(1)式の指数項の中身
に入ってくるわけである。更にソース領域に禁制帯幅の
広い半導体を用いても電流増幅率は上昇する。第2図に
おいてn“基板60の部分がp中領域で形成されると静
電誘導型ホトサイリスタとなる。
In order to form a potential barrier in the n-high resistance layer, D”
Dimensions between gates 62, impurity density and n-111161
dimensions and impurity density are selected. In the conventional structure, the forbidden band width of the semiconductor in the high resistance 111[i region n-61 and the forbidden band width of the semiconductor forming the p+ gate region 11162 and the n++ plate 60 are all the same. That is, almost all regions are often formed of the same semiconductor. There are some examples of static induction transistors in which a Peter junction is provided in a gate region or a source region. In this case, gate region 6
If the semiconductor No. 2 is formed of a material having a wider forbidden band width than the semiconductor in the channel region, the gate 62 and the channel n-
A heterojunction occurs at the junction interface 61. If only the gate is formed of a semiconductor with a wide forbidden band width, and the other regions are made of the same semiconductor, the current amplification factor increases by integrating the potential difference at the heterojunction interface. That is,
The potential difference at the hetero interface is included in the exponential term in equation (1). Furthermore, even if a semiconductor with a wide forbidden band width is used in the source region, the current amplification factor increases. In FIG. 2, if the n'' substrate 60 is formed in the p medium region, it becomes an electrostatic induction type photothyristor.

〔発明が解決しようどする問題点〕[Problems that the invention attempts to solve]

しかるに本発明者は、更に高速・高感度な静N誘導型光
検出器を見出した。
However, the present inventors have discovered a static N-induced photodetector that is even faster and more sensitive.

〔発明が解決しようとする手段〕[Means to be solved by the invention]

ゲート・ドレイン間の高抵抗m領域にゲート領域及びド
レイン領域よりも禁制帯幅の狭い半導体を用いることに
よって長波長感度が増大し、静電誘導トランジスタ部分
の光増幅度を増し、かつ高抵抗層領域とドレイン間のバ
ンドギャップ差によるサイリスク動作と等価な載面を持
つ光検出器となる。更にこの禁制帯幅の狭い半導体部分
には、従来の同一禁制帯幅で・形成される場合に比べ、
より強電界を同一の厚さ、同一の電圧で発生することが
できるため、アバランシミ界がかかるように寸法、電圧
、不純物密度等を選べば、長波長光をAPDで高速・高
感度に受光しかつ静電4尋トランジスタ部分で更に信号
増幅が行なわれることになる。又アバランシ電界となる
ほど電界強度を高くしなくても本発明の84成のものは
充分高感度・1:)速である。
By using a semiconductor whose forbidden band width is narrower than that of the gate and drain regions in the high resistance m region between the gate and drain, the long wavelength sensitivity is increased, the optical amplification of the static induction transistor portion is increased, and the high resistance layer This results in a photodetector with a mounting surface equivalent to the Sirisk operation due to the bandgap difference between the region and the drain. Furthermore, compared to the conventional case where the semiconductor part with the narrow forbidden band width is formed with the same forbidden band width,
A stronger electric field can be generated with the same thickness and voltage, so if the dimensions, voltage, impurity density, etc. are selected so that an avalanche field is applied, long wavelength light can be received by the APD at high speed and with high sensitivity. Furthermore, signal amplification is performed in the electrostatic four-layer transistor section. Further, even if the electric field strength is not made so high as to cause an avalanche electric field, the 84-component device of the present invention has sufficiently high sensitivity and 1:) speed.

(作用) 上述の如〈従来型静電誘導ホトトランジスタのゲート・
トレイン間の高抵抗層部分を禁制帯幅の狭い半導体で形
成するとゲート・ドレイン間には強電界が発生しやすく
なる。アバランシ電界となるとキ17リアの衝突電離に
よって増倍されたキャリアが強電界中を走行する。nチ
ャンネル静′Fixs トランジスタの場合を例にとる
と、増倍された正孔はp+ゲート領域にM積され、また
増倍された電子は高抵抗層とアノード領域とのヘテロ接
合界面に一部蓄積される。pヤゲート領域に蓄積された
正孔はp+ゲート領域を正に帯電させるため、静W1誘
導トランジスタのゲートが順方向バイアスされることに
なり、チャンネル中の電位P3壁が下がる。これにつれ
て、n+ソース領域から高抵抗チャンネル領域への電子
の注入がおこり、アバランシ電・界で増倍された光信号
としての正孔が、更に多くの数の電子を増幅してソース
・ドレイン間に光信号出力が得られるわけである。
(Function) As mentioned above, the gate of the conventional static induction phototransistor
If the high resistance layer portion between the trains is formed of a semiconductor with a narrow forbidden band width, a strong electric field is likely to be generated between the gate and drain. In the case of an avalanche electric field, carriers multiplied by collision ionization of the Q17 rear travel in a strong electric field. Taking the case of an n-channel static fixes transistor as an example, the multiplied holes are accumulated in the p+ gate region, and some of the multiplied electrons are deposited at the heterojunction interface between the high resistance layer and the anode region. Accumulated. The holes accumulated in the p+ gate region positively charge the p+ gate region, thus forward biasing the gate of the static W1 induction transistor and lowering the potential P3 wall in the channel. Along with this, electrons are injected from the n+ source region to the high-resistance channel region, and the holes, which serve as optical signals multiplied by the avalanche electric field, amplify even more electrons and form a gap between the source and drain. Therefore, an optical signal output can be obtained.

(実施例) 第1図は本発明の実施例を示す。(Example) FIG. 1 shows an embodiment of the invention.

領域21はドレインもしくはアノード領域を示し、n+
領領域しくはn中領域として形成された主電極領域であ
り、n中領域であれば静電誘導ホトトランジスタとして
動作し、pf領領域あれば静電誘導ホトサイリスタとし
て動作する。材料としては例えばn+InPもしくはp
“InPを用いる。¥4域20はドレインもしくはアノ
ード電極であり電極材料としてはn + 1nPに対し
てはAu −Qe−Niまたpヤ 【nPに対してはA
LI −7n−Ni等の合金を用いる。領域22は本発
明の特徴を表わす禁制帯幅の小さい半導体で形成された
高抵抗層である。
Region 21 represents the drain or anode region, and is n+
The main electrode region is formed as a region or an n-medium region, and if it is an n-medium region, it operates as a static induction phototransistor, and if it is a pf region, it operates as a static induction photothyristor. For example, the material is n+InP or p
"InP is used. The ¥4 area 20 is the drain or anode electrode, and the electrode material is Au-Qe-Ni or pya for n+1nP.
An alloy such as LI-7n-Ni is used. Region 22 is a high resistance layer formed of a semiconductor with a small forbidden band width, which is a feature of the present invention.

例えば1nQaAsを用いる。、領域24は同じく高抵
抗層であるが、領L1i22とは別の、領域22よりも
禁制帯幅の広い半導体層である。例えばn= [n p
を用いる。n中領域25は静電誘導ホトトランジスタも
しくは静電4尋ホトサイリスタのゲートとして作用し、
例えばp+1nPで形成されている。n中領域28は静
電誘導ホトトランジスタのソース領域もしくは静電誘導
ホトサイリスタのカソードmbXとして作用し、例えば
n″″InPで形成されている。領域26は絶縁性光学
的反射防止膜である。領域27はゲート電極であり、例
えばp”tnpに対してはAu −Zn−Ni等で形成
する。又領域29はn中領域28の電極であり、例えば
n中InPに対してはALI −Qe−Ni等で形成す
る。光11νはp+ゲート領域表面から入射する。高抵
抗層領域24及び22はp+ゲート領域25とn”領域
28或いはp+ゲート領域25と高不純物密度領域21
間に形成されるp −1−nダイオードのi層部分に相
当している。高抵抗層領域24及び22はゲート電極2
7及び一方の主電極29、他方の主電極20間に印加さ
れる電圧によってほぼ空乏化するように寸法、不純物密
度を選ぶ。更にp′+ゲート25に挾まれた高抵抗層部
分24及び22の一部分にはn+領域28からみて電位
障壁が形成され、その高さはゲートff電極27の電圧
とn 電極29及び電極20間の電圧による静電誘導効
果によって変化されるようにp÷ゲートWA域25間の
寸法及び不純物!F/J!、高抵抗WI22.24の厚
さは選ばれる。高抵抗W!J領域22として他の領域2
4.25.21.28よりも禁制帯幅の狭い半導体を用
いることで、表面から入射する光の波長のうち長波長領
域の感度が増大する。更に強電界が生じやすくなるため
、p”(25)n−(24)n−(22)n+もしくは
p十(21)間の22の領域にアバランシ電界が発生す
るように寸法、不純物密度等が選ばれればアバランシホ
トダイオードがゲートのまわりに分布した静電誘3#型
光検出器が形成されることになる。p+ゲート25と高
不純物密U領11!21間に形成されたアバランシダイ
オードによって高速・高感度に受光された光信号が更に
増幅された信号が主電極29及び20間から取り出され
る。電子正孔対は殆んど空乏化された高抵抗層ffa域
22及び24中で発生し、そのうち正孔はp+ゲート領
域25に18!Iされ、ゲート25の静1!誘導効果に
よって口”領[28の近傍に生じている電位障壁高さが
変化することになる。高抵抗領域24の代りにp型の半
導体を用いてもよい。p型領域が完全に空乏化されるな
らば静電誘導ホトトランジスタと同等の動作となるが、
一部パイポーラベース層の中性領域が残っている場合に
は、バイポーラ型ホトトランジスタもしくはホトサイリ
スタとなる。或いは高抵抗温域1m!24の全部もしく
は領域22近くの一部が高抵抗温域*22と同じく禁i
ll帯幅の狭い半導体(例えばn−In Qa As 
)で形成されていてもよい。高不純物密度領域21がゲ
ート領域25と同一導電型の領域(第1図の例でp+)
の場合には、第1図の実施例は、静電誘導型ホトサイリ
スタとして動作する。この場合領域21と禁制帯幅の狭
い領域22とのヘテロ界面は光によって発生した電子正
孔のうら電子が蓄積される領域となる。この電子の蓄積
によって増幅されて更に多くの正孔がp中領域21から
領域22へ注入されることになる。各部を形成する半導
体の例としてIn P−In GaAsの例を示したが
、これに限るものではなく、Ga As −Ga At
 As 、 Ga As −In Ga As P等の
他の2元系、3元系、4元系の化合物半導体の組み合わ
せでもよい。本発明の実施例においては平面ゲート構造
について示したが、ゲートの形状は埋め込みゲート、切
り込みゲート、MOS(Mis)ゲート、ヘテロゲート
、ショットキーゲートであってもよいことは勿論である
For example, 1nQaAs is used. The region 24 is also a high resistance layer, but is a semiconductor layer different from the region L1i22 and having a wider forbidden band width than the region 22. For example, n = [n p
Use. The n-middle region 25 acts as a gate of an electrostatic induction phototransistor or an electrostatic four-layer photothyristor,
For example, it is formed of p+1nP. The n middle region 28 functions as a source region of an electrostatic induction phototransistor or a cathode mbX of an electrostatic induction photothyristor, and is formed of, for example, n''''InP. Region 26 is an insulating optical anti-reflection coating. The region 27 is a gate electrode, and is formed of Au-Zn-Ni etc. for p"tnp, for example. The region 29 is an electrode of the n-middle region 28, and is formed of ALI-Qe for, for example, n-middle InP. -Ni, etc. The light 11ν enters from the surface of the p+ gate region.The high resistance layer regions 24 and 22 are composed of the p+ gate region 25 and the n'' region 28 or the p+ gate region 25 and the high impurity density region 21.
This corresponds to the i-layer portion of the p-1-n diode formed between the two. High resistance layer regions 24 and 22 are gate electrodes 2
The dimensions and impurity density are selected so that depletion occurs due to the voltage applied between the main electrode 7, one main electrode 29, and the other main electrode 20. Furthermore, a potential barrier is formed in a portion of the high resistance layer portions 24 and 22 sandwiched between the p′+ gate 25 when viewed from the n+ region 28, and its height is equal to the voltage between the gate ff electrode 27 and the n electrode 29 and the electrode 20. Dimensions between p÷ gate WA area 25 and impurities as changed by electrostatic induction effect due to voltage of ! F/J! , the thickness of high resistance WI22.24 is chosen. High resistance W! Other area 2 as J area 22
By using a semiconductor whose forbidden band width is narrower than that of 4.25.21.28, the sensitivity in the long wavelength region of the wavelengths of light incident from the surface increases. Furthermore, since a strong electric field is likely to occur, the dimensions, impurity density, etc. should be adjusted so that an avalanche electric field is generated in the region 22 between p'' (25) n- (24) n- (22) n+ or p10 (21). If selected, an electrostatic dielectric 3# type photodetector in which avalanche photodiodes are distributed around the gate will be formed.Avalanche diodes are formed between the p+ gate 25 and the highly impurity-dense U region 11!21. A signal obtained by further amplifying the optical signal received at high speed and high sensitivity is extracted from between the main electrodes 29 and 20.Electron-hole pairs are mostly depleted in the high resistance layer ffa regions 22 and 24. The holes are generated, and among them, the holes are transferred to the p+ gate region 25, and the potential barrier height generated in the vicinity of the gate region [28] changes due to the static 1! induction effect of the gate 25. A p-type semiconductor may be used instead of the high resistance region 24. If the p-type region is completely depleted, the operation will be equivalent to that of a static induction phototransistor, but
If some neutral region of the bipolar base layer remains, it becomes a bipolar phototransistor or a photothyristor. Or high resistance temperature range 1m! All of 24 or part of area 22 is prohibited as in high resistance temperature area*22.
Semiconductors with narrow bandwidth (e.g. n-In Qa As
) may be formed. High impurity density region 21 is a region of the same conductivity type as gate region 25 (p+ in the example of FIG. 1)
In this case, the embodiment of FIG. 1 operates as a static induction photothyristor. In this case, the hetero interface between the region 21 and the narrow forbidden band region 22 becomes a region where electrons behind electrons and holes generated by light are accumulated. This accumulation of electrons causes more holes to be amplified and injected from the p-type region 21 to the region 22. Although InP-InGaAs is shown as an example of a semiconductor forming each part, the semiconductor is not limited to this, and GaAs-GaAt
Combinations of other binary, ternary, and quaternary compound semiconductors such as As, GaAs-InGaAsP, etc. may also be used. In the embodiments of the present invention, a planar gate structure is shown, but it goes without saying that the shape of the gate may be a buried gate, a cut gate, a MOS (Mis) gate, a hetero gate, or a Schottky gate.

〔発明の効果〕〔Effect of the invention〕

本発明による静電誘導型光検出器では、主としてゲート
・ドレインもしくはゲート・アノード間に禁制帯幅の狭
い半導体を用いることを特徴としており、この領域の禁
制帯幅が狭いことから光検出波長としては長波長感度が
増大する。更にこの領域の電界強度を高くすることが容
易となるため、例えばアバランシ電界強度となれば、こ
のゲート・ドレインもしくはゲート・アノード間のアバ
ランシダイオードによって高速・高感度に受光可能とな
り、従来の静?l!誘導型光検出器よりら更に高速・高
感度となる。
The electrostatic induction photodetector according to the present invention is characterized in that a semiconductor with a narrow forbidden band width is mainly used between the gate and drain or between the gate and anode. increases long wavelength sensitivity. Furthermore, since it is easy to increase the electric field strength in this region, for example, if it becomes an avalanche electric field strength, it becomes possible to receive light at high speed and with high sensitivity using the avalanche diode between the gate and drain or between the gate and anode. ? l! Faster and more sensitive than inductive photodetectors.

本発明は、従来の!J造方法例えばMOCVD法、光C
VD法、光エピタキシャル法、分子層エピタキシャル法
を用いて製造することが容易であり、かつ高速・′a高
感度長波長光通信用光検出器となることから工業的価値
の高いものである。
The present invention is different from conventional! J manufacturing method such as MOCVD method, optical C
It is easy to manufacture using the VD method, photoepitaxial method, or molecular layer epitaxial method, and is of high industrial value because it can be used as a photodetector for high-speed, high-sensitivity, and long-wavelength optical communications.

【図面の簡単な説明】[Brief explanation of drawings]

° 第1図は本発明の実施例を示し、第2図は従・来の
静電誘導型光検出器の断面41り造例である。 20・・・ドレインもしくはアノードとなる主電極、2
1・・・n+もしくはp十の高不純物密度領域、22・
・・他の領域より禁制帯幅の狭くなされた高抵抗層、2
4・・・高抵抗層、25・・・ゲート拡散領域、28・
・・ソースもしくはカソード領域、29・・・ソースも
しくはカソード電極、26・・・絶縁性光学的反射防止
膜、27・・・ゲート電極。
1 shows an embodiment of the present invention, and FIG. 2 shows a cross section 41 of a conventional electrostatic induction photodetector. 20... Main electrode serving as a drain or anode, 2
1...n+ or p10 high impurity density region, 22.
...High resistance layer with narrower forbidden band width than other regions, 2
4... High resistance layer, 25... Gate diffusion region, 28...
. . . Source or cathode region, 29 . . . Source or cathode electrode, 26 . . . Insulating optical antireflection film, 27 . . . Gate electrode.

Claims (1)

【特許請求の範囲】[Claims] (1)半導体基板が、ともに第1及び第2の高抵抗層か
らなる第一及び第二のヘテロ接合で構成され、前記第一
の高抵抗層中に形成された第一の導電型の高不純物密度
ゲート拡散領域と、前記ゲート拡散領域に挟まれて前記
第一の高抵抗層中に形成された第二の導電型で前記ゲー
ト拡散領域とは反対導電型の高不純物密度領域からなる
第一の主電極領域と、前記ゲート及び第一の主電極領域
の形成された第一の主表面とは反対側の第二の高抵抗層
と接合面を形成する第一もしくは第二の導電型の高不純
物密度領域からなる第二の主電極領域と、第一及び第二
の主電極領域上に形成された第一及び第二の電極領域と
、前記ゲート拡散領域を含む前記第一の高抵抗層上に形
成された絶縁性・光学的反射防止膜と、前記ゲート拡散
領域上に形成された第三のゲート電極とを有し、第二の
高抵抗層を形成する半導体のみが他の領域の半導体の禁
制帯幅より小さい禁制帯幅を有する半導体で形成され、
第二の主電極領域と前記ゲート領域に加わる電圧によっ
て容易にアバランシ電界が発生すべくなされ、かつ前記
第一の高抵抗層中もしくは第一及び第二の高抵抗層中に
、前記ゲート拡散領域と第一の主電極領域間の電圧及び
前記ゲート拡散領域と第二の主電極領域間の電圧によつ
て電位障壁が形成され前記第一及び第二の高抵抗層領域
はほとんど空乏化されており、前記ゲート拡散領域及び
前記第二の主電極領域の電位によって前記電位障壁の高
さが変化するような寸法に各部の寸法が選ばれ、前記電
位障壁高さによって第一及び第二の主電極間を流れる多
数キャリアが制御されることを特徴とする静電誘導型光
検出器。
(1) A semiconductor substrate is composed of first and second heterojunctions each consisting of a first and a second high resistance layer, and a first conductivity type heterojunction formed in the first high resistance layer. an impurity density gate diffusion region; and a high impurity density region of a second conductivity type opposite to that of the gate diffusion region, which is sandwiched between the gate diffusion region and formed in the first high resistance layer. A first or second conductivity type that forms a bonding surface with one main electrode region and a second high-resistance layer opposite to the first main surface on which the gate and the first main electrode region are formed. a second main electrode region consisting of a high impurity density region, first and second electrode regions formed on the first and second main electrode regions, and the first height region including the gate diffusion region. It has an insulating/optical antireflection film formed on the resistance layer and a third gate electrode formed on the gate diffusion region, and only the semiconductor forming the second high resistance layer is separated from the others. formed of a semiconductor having a forbidden band width smaller than the forbidden band width of the semiconductor in the region;
The gate diffusion region is configured such that an avalanche electric field can be easily generated by a voltage applied to the second main electrode region and the gate region, and the gate diffusion region is arranged in the first high resistance layer or in the first and second high resistance layers. A potential barrier is formed by the voltage between the gate diffusion region and the first main electrode region and the voltage between the gate diffusion region and the second main electrode region, and the first and second high resistance layer regions are almost depleted. The dimensions of each part are selected such that the height of the potential barrier changes depending on the potential of the gate diffusion region and the second main electrode region. An electrostatic induction photodetector characterized by controlling majority carriers flowing between electrodes.
JP59179982A 1984-08-28 1984-08-28 Static induction type semiconductor photodetector Expired - Fee Related JPH0682859B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP59179982A JPH0682859B2 (en) 1984-08-28 1984-08-28 Static induction type semiconductor photodetector

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59179982A JPH0682859B2 (en) 1984-08-28 1984-08-28 Static induction type semiconductor photodetector

Publications (2)

Publication Number Publication Date
JPS6158279A true JPS6158279A (en) 1986-03-25
JPH0682859B2 JPH0682859B2 (en) 1994-10-19

Family

ID=16075383

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59179982A Expired - Fee Related JPH0682859B2 (en) 1984-08-28 1984-08-28 Static induction type semiconductor photodetector

Country Status (1)

Country Link
JP (1) JPH0682859B2 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1994023455A1 (en) * 1993-03-31 1994-10-13 Siemens Components, Inc. High-voltage, vertical-trench semiconductor device
KR100348700B1 (en) * 2000-09-16 2002-08-13 서울대학교 공과대학 교육연구재단 Optical Device and Manufacturing Method of the Same

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1994023455A1 (en) * 1993-03-31 1994-10-13 Siemens Components, Inc. High-voltage, vertical-trench semiconductor device
US5445974A (en) * 1993-03-31 1995-08-29 Siemens Components, Inc. Method of fabricating a high-voltage, vertical-trench semiconductor device
US5793063A (en) * 1993-03-31 1998-08-11 Siemens Microelectronics, Inc. High voltage, vertical-trench semiconductor device
KR100348700B1 (en) * 2000-09-16 2002-08-13 서울대학교 공과대학 교육연구재단 Optical Device and Manufacturing Method of the Same

Also Published As

Publication number Publication date
JPH0682859B2 (en) 1994-10-19

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