JPH0682859B2 - Static induction type semiconductor photodetector - Google Patents

Static induction type semiconductor photodetector

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Publication number
JPH0682859B2
JPH0682859B2 JP59179982A JP17998284A JPH0682859B2 JP H0682859 B2 JPH0682859 B2 JP H0682859B2 JP 59179982 A JP59179982 A JP 59179982A JP 17998284 A JP17998284 A JP 17998284A JP H0682859 B2 JPH0682859 B2 JP H0682859B2
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JP
Japan
Prior art keywords
region
gate
high resistance
resistance layer
main electrode
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP59179982A
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Japanese (ja)
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JPS6158279A (en
Inventor
潤一 西澤
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Individual
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Individual
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Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/08Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof in which radiation controls flow of current through the device, e.g. photoresistors
    • H01L31/10Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof in which radiation controls flow of current through the device, e.g. photoresistors characterised by potential barriers, e.g. phototransistors
    • H01L31/101Devices sensitive to infrared, visible or ultraviolet radiation
    • H01L31/112Devices sensitive to infrared, visible or ultraviolet radiation characterised by field-effect operation, e.g. junction field-effect phototransistor
    • H01L31/1127Devices with PN heterojunction gate
    • H01L31/1129Devices with PN heterojunction gate the device being a field-effect phototransistor

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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Electromagnetism (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Junction Field-Effect Transistors (AREA)
  • Light Receiving Elements (AREA)

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は静電誘導トランジスタを原理とする高速・高感
度な光検出器に関し、特に長波長感度が向上することか
ら、長波長光通信用高速・高感度な光検出器として利用
されるものである。
Description: TECHNICAL FIELD The present invention relates to a photodetector having a high speed and high sensitivity based on the principle of an electrostatic induction transistor, and particularly for long wavelength optical communication because the long wavelength sensitivity is improved. It is used as a high-speed, high-sensitivity photodetector.

〔従来技術〕[Prior art]

従来型光検出器として特に本発明に近いものとして、静
電誘導ホトトランジスタがある。
As a conventional photodetector, an electrostatic induction phototransistor is particularly close to the present invention.

例えば審判昭62−18752号「半導体光電変換装置」)静
電誘導ホトトランジスタは、ゲートのまわりに分布する
p−i−nダイオードを光検出部とする。nチャンネル
を例にとると光によって発生した電子正孔対のうち正孔
はp+ゲート領域に蓄積されるため、ゲートの電位変化を
引き起し、これによってチャンネル中の電位障壁高さが
変調されるため、ソース・ドレイン間を流れる増幅電流
がこのゲート電位変化で変調されるというものである。
その光増幅度は非常に高く、しかも入射光強度が微弱で
あれば微弱であるほど高いという、従来型バイポーラホ
トトランジスタとは全く逆の特性がが得られる。その最
大光増幅度Gmaxは近似的に で現される。ここでnはn+ソース領域の不純物密度、
はp+ゲート領域の不純物密度、Dは電子の拡散定
数、Dは正孔の拡散定数、Wは電位障壁の実効的な
厚さ、Lは正孔の拡散距離、qは単位電荷量、Kはボ
ルツマン定数、Tは絶対温度、VbiGSはゲート・ソース
間pinダイオードの拡散電位、VbiG はソースからみ
た電位障壁高さピークの高さである。その一般的な構造
の一例を第2図に示す。n+基板60上に形成されたn-もし
くはp-の高抵抗層61中に拡散されたp+領域62がゲート領
域であり、n+領域67はソース領域を示す。n+基板60はド
レイン領域である。64及び65はそれぞれゲート領域、ソ
ース電極を示す。63は絶縁物である。入射光hνによっ
て侵入した光は主としてn-高抵抗層61中において電子・
正孔対を発生させる。この正孔がp+ゲート領域62に蓄積
されることから主電極65及び66間に増幅信号が得られ
る。n-高抵抗層中には電位障壁が形成されるべく、p+
ート62間の寸法、不純物密度及びn-層61の寸法、不純物
密度は選ばれている。従来型構造においては高抵抗層領
域n-61の半導体の禁制帯幅とp+ゲート領域62及びn+基板
60を形成する半導体の禁制帯幅は全て同じである。すな
わち、ほぼ全ての領域は同一半導体で形成されることが
多い。一部、ヘテロ接合をゲート領域もしくはソース領
域に設ける静電誘導トランジスタの例がある。この場
合、ゲート領域62の半導体をチャンネル領域の半導体に
比べ禁制帯幅の広いもので形成すると、ゲート62及びチ
ャンネルn-61の接合界面にはヘテロ接合が生ずる。ゲー
トのみ禁制帯幅の広い半導体で形成するだけで、他の領
域は同一半導体とすると、そのヘテロ接合界面における
電位差分だけ積算された形で電流増幅率は上昇する。す
なわち、ヘテロ界面における電位差分が(1)式の指数
項の中身に入ってくるわけである。更にソース領域に禁
制帯幅の広い半導体を用いても電流増幅率は上昇する。
第2図においてn+基板60の部分がp+領域で形成されると
静電誘導型ホトサイリスタとなる。n+領域67をドレイン
領域、n+基板60をソース領域として用いても静電誘導ト
ランジスタとして動作をする。
For example, Jpn. Pat. Appln. KOKAI Publication No. 62-18752 "Semiconductor photoelectric conversion device") In the static induction phototransistor, a pin diode distributed around the gate is used as a photodetector. Taking the n-channel as an example, holes among the electron-hole pairs generated by light are accumulated in the p + gate region, which causes a change in the gate potential, which causes the potential barrier height in the channel to be modulated. Therefore, the amplified current flowing between the source and drain is modulated by this gate potential change.
The optical amplification degree is very high, and the weaker the incident light intensity is, the higher the weaker the incident light intensity is, which is the opposite characteristic of the conventional bipolar phototransistor. The maximum optical amplification G max is approximately Is represented by. Where n S is the impurity density of the n + source region,
P G impurity density of the p + gate region, D m is the electron diffusion constant, D p is the hole diffusion constant, W G is the effective thickness of the potential barrier, L P is the hole diffusion length, q Is the unit charge amount, K is the Boltzmann constant, T is the absolute temperature, V biGS is the diffusion potential of the gate diode between the source and the source, and V biG * S is the height of the potential barrier height peak viewed from the source. An example of the general structure is shown in FIG. The p + region 62 diffused in the n or p high resistance layer 61 formed on the n + substrate 60 is a gate region, and the n + region 67 is a source region. The n + substrate 60 is the drain region. Reference numerals 64 and 65 denote a gate region and a source electrode, respectively. 63 is an insulator. The light penetrating by the incident light hν is mainly the electrons in the n high resistance layer 61.
Generates hole pairs. Since the holes are accumulated in the p + gate region 62, an amplified signal is obtained between the main electrodes 65 and 66. The dimensions between the p + gates 62, the impurity density, and the dimensions of the n layer 61 and the impurity density are selected so that a potential barrier is formed in the n high resistance layer. In the conventional structure, the forbidden band width of the semiconductor in the high resistance layer region n - 61 and the p + gate region 62 and the n + substrate
The band gaps of the semiconductors forming 60 are all the same. That is, almost all regions are often formed of the same semiconductor. There are some examples of static induction transistors in which a heterojunction is provided in the gate region or the source region. In this case, when formed in a wider bandgap than the semiconductor gate region 62 in the semiconductor of the channel region, the gate 62 and channel n - heterojunction occurs in the bonding interface 61. If only the gate is formed of a semiconductor having a wide band gap and the other regions are made of the same semiconductor, the current amplification factor increases in a form integrated by the potential difference at the heterojunction interface. That is, the potential difference at the hetero interface comes into the content of the exponential term of the equation (1). Further, the current amplification factor increases even if a semiconductor having a wide band gap is used for the source region.
In FIG. 2, when the part of the n + substrate 60 is formed by the p + region, it becomes an electrostatic induction type photothyristor. Even if the n + region 67 is used as the drain region and the n + substrate 60 is used as the source region, it operates as a static induction transistor.

〔発明が解決しようとする問題点〕[Problems to be solved by the invention]

しかるに本発明者は、更に高速・高感度な静電誘導型光
検出器を見出した。
However, the present inventor has found an electrostatic induction type photodetector with higher speed and higher sensitivity.

〔発明が解決しようとする手段〕[Means to be Solved by the Invention]

ゲート・ドレイン間の高抵抗層領域にゲート領域及びド
レイン領域よりも禁制帯幅の狭い半導体を用いることに
よって長波長感度が増大し、静電誘導トランジスタ部分
の光増幅度を増した光検出器となる。更にこの禁制帯幅
の狭い半導体部分には、従来の同一禁制帯幅で形成され
る場合に比べ、より強電界を同一の厚さ、同一の電圧で
発生することができるため、アバランシ電界がかかるよ
うに寸法、電圧、不純物密度等を選べば、長波長光をAP
Dで高速・高感度に受光しかつ静電誘導トランジスタ部
分で更に信号増幅が行なわれることになる。又アバラン
シ電界となるほど電界強度を高くしなくても本発明の構
成のものは充分高感度・高速である。
By using a semiconductor with a narrower bandgap than the gate and drain regions in the high-resistance layer region between the gate and drain, long-wavelength sensitivity is increased, and a photodetector with increased optical amplification of the static induction transistor Become. Further, since a stronger electric field can be generated with the same thickness and the same voltage in the semiconductor portion having the narrower forbidden band width than in the case where the conventional forbidden band width is formed, an avalanche electric field is applied. As long as you choose dimensions, voltage, impurity density, etc.
Light is received at high speed and with high sensitivity at D, and signal amplification is further performed at the electrostatic induction transistor section. Further, the structure of the present invention has sufficiently high sensitivity and high speed even if the electric field strength is not so high as to give an avalanche electric field.

〔作用〕[Action]

上述の如く従来型静電誘導ホトトランジスタのゲート・
ドレイン間の高抵抗層部分を禁制帯幅の狭い半導体で形
成するとゲート・ドレイン間には強電界が発生しやすく
なる。アバランシ電界となるとキャリアの衝突電離によ
って増倍されたキャリアが強電界中を走行する。nチャ
ンネル静電誘導トランジスタの場合を例にとると、増倍
された正孔はp+ゲート領域に蓄積され、また増倍された
電子は高抵抗層とアノード領域とのヘテロ接合界面に一
部蓄積される。p+ゲート領域に蓄積された正孔はp+ゲー
ト領域を正に帯電させるため、静電誘導トランジスタの
ゲートが順方向バイアスされることになり、チャンネル
中の電位障壁が下がる。これにつれて、n+ソース領域か
ら高抵抗チャンネル領域への電子の注入がおこり、アバ
ランシ電界で増倍された光信号としての正孔が、更に多
くの数の電子を増幅してソース・ドレイン間に信号出力
が得られるわけである。
As mentioned above, the gate of the conventional static induction phototransistor
If the high resistance layer portion between the drains is formed of a semiconductor having a narrow band gap, a strong electric field is easily generated between the gate and the drain. When an avalanche electric field is reached, carriers multiplied by collisional ionization of carriers travel in a strong electric field. Taking the case of an n-channel static induction transistor as an example, the multiplied holes are accumulated in the p + gate region, and the multiplied electrons are partly at the heterojunction interface between the high resistance layer and the anode region. Accumulated. holes stored in p + gate region in order to positively charge the p + gate region, will be the gate of the static induction transistor is forward biased, the potential barrier in the channel is reduced. Along with this, electrons are injected from the n + source region to the high resistance channel region, and holes as an optical signal multiplied by the avalanche electric field amplify a larger number of electrons to cause a gap between the source and drain. The signal output is obtained.

〔実施例〕〔Example〕

第1図は本発明の実施例を示す。 FIG. 1 shows an embodiment of the present invention.

領域21はドレインもしくはアノード領域を示し、n+領域
もしくはp+領域として形成された主電極領域であり、n+
領域であれば静電誘導ホトトランジスタとして動作し、
p+領域であれば静電誘導ホトサイリスタとして動作す
る。材料としては例えばn+InPもしくはp+InPを用いる。
領域20はドレインもしくはアノード電極であり電極材料
としてはn+InPに対してはAu−Ge−Niまたp+InPに対して
はAu−Zn−Ni等の合金を用いる。領域22は本発明の特徴
を表わす禁制帯幅の小さい半導体で形成された高抵抗層
である。例えばInGaAsを用いる。領域24は同じく高抵抗
層であるが、領域22とは別の、領域22よりも禁制帯幅の
広い半導体層である。例えばn-InPを用いる。p+領域25
は静電誘導ホトトランジスタもしくは静電誘導ホトサイ
リスタのゲートとして作用し、例えばp+InPで形成され
ている。n+領域28は静電誘導ホトトランジスタのソース
領域もしくは静電誘導ホトサイリスタのカソード領域と
して作用し、例えばn+InPで形成されている。領域26は
絶縁性光学的反射防止膜である。領域27はゲート電極で
あり、例えばp+InPに対してはAu−Zn−Ni等で形成す
る。又領域29はn+領域28の電極であり、例えばn+InPに
対してはAu−Ge−Ni等で形成する。光hνはp+ゲート領
域表面から入射する。高抵抗層領域24及び22はp+ゲート
領域25とn+領域28或いはp+ゲート領域25と高不純物密度
領域21間に形成されるp−i−nダイオードのi層部分
に相当している。高抵抗層領域24及び22はゲート電極27
及び一方の主電極29、他方の主電極20間に印加される電
圧によってほぼ空乏化するように寸法、不純物密度を選
ぶ。更にp+ゲート25に挾まれた高抵抗層部分24及び22の
一部分にはn+領域28からみて電位障壁が形成され、その
高さはゲート電極27の電圧とn+電極29及び電極20間の電
圧による静電誘導効果によって変化されるようにp+ゲー
ト領域25間の寸法及び不純物密度、高抵抗層22、24の厚
さは選ばれる。高抵抗層領域22として他の領域24、25、
21、28よりも禁制帯幅の狭い半導体を用いることで、表
面から入射する光の波長のうち長波長領域の感度が増大
する。更に強電界が生じやすくなるため、p+(25)n
-(24)n-(22)n+もしくはp+(21)間の22の領域にア
バランシ電界が発生するように寸法、不純物密度等が選
ばれればアバランシホトダイオードがゲートのまわりに
分布した静電誘導型光検出器が形成されることになる。
p+ゲート25と高不純物密度領域21間に形成されたアバラ
ンシダイオードによって高速・高感度に受光された光信
号が更に増幅された信号として主電極29及び20間から取
り出される。電子正孔対は殆んど空乏化された高抵抗層
領域22及び24中で発生し、そのうち正孔はp+ゲート領域
25に蓄積され、ゲート25の静電誘導効果によってn+領域
28の近傍に生じている電位障壁高さが変化することにな
る。高抵抗領域24の代りにp型の半導体を用いてもよ
い。p型領域が完全に空乏化されるならば静電誘導ホト
トランジスタと同等の動作となるが、p型領域に中性領
域が残っている場合には、バイポーラ型ホトトランジス
タとなる。基板21がp+型の時はホトサイリスタとなる。
或いは高抵抗層領域24の全部もしくは領域22近くの一部
が高抵抗層領域22と同じく禁制帯幅の狭い半導体(例え
ばn-InGaAs)で形成されていてもよい。高不純物密度領
域21がゲート領域25と同一導電型の領域(第1図の例で
p+)の場合には、第1図の実施例は、静電誘導ホトサイ
リスタとして動作する。この場合領域21と禁制帯幅の狭
い領域22とのヘテロ界面は光によって発生した電子正孔
のうち電子が蓄積される領域となる。この電子の蓄積に
よって増幅されて更に多くの正孔がp+領域21から領域22
へ注入されることになる。各部を形成する半導体の例と
してInP−InGaAsの例を示したが、これに限るものでは
なく、GaAs−GaAlAs、GaAs−InGaAsP等の他の2元系、
3元系、4元系の化合物半導体の組み合わせでもよい。
本発明の実施例においては平面ゲート構造について示し
たが、ゲートの形状は埋め込みゲート、切り込みゲー
ト、MOS(MIS)ゲート、ヘテロゲート、ショットキーゲ
ートであってもよいことは勿論である。
Region 21 indicates a drain or anode region, which is a main electrode region formed as an n + region or p + region, and n +
If it is a region, it operates as a static induction phototransistor,
If it is in the p + region, it operates as an electrostatic induction photothyristor. For example, n + InP or p + InP is used as the material.
The region 20 is a drain or anode electrode, and the electrode material is an alloy such as Au-Ge-Ni for n + InP and Au-Zn-Ni for p + InP. The region 22 is a high resistance layer formed of a semiconductor having a small forbidden band width, which is a feature of the present invention. For example, InGaAs is used. The region 24 is also a high resistance layer, but is a semiconductor layer different from the region 22 and having a wider forbidden band than the region 22. For example, n - InP is used. p + region 25
Acts as a gate of an electrostatic induction phototransistor or an electrostatic induction photothyristor, and is formed of, for example, p + InP. The n + region 28 acts as the source region of the static induction phototransistor or the cathode region of the static induction photothyristor, and is formed of, for example, n + InP. Region 26 is an insulating optical antireflection coating. The region 27 is a gate electrode, and is formed of, for example, Au-Zn-Ni for p + InP. The region 29 is an electrode of the n + region 28, and is formed of Au-Ge-Ni for n + InP, for example. The light hν enters from the surface of the p + gate region. The high resistance layer regions 24 and 22 correspond to the i layer portion of the p-i-n diode formed between the p + gate region 25 and the n + region 28 or between the p + gate region 25 and the high impurity density region 21. . The high resistance layer regions 24 and 22 are gate electrodes 27.
The dimensions and the impurity density are selected so that the voltage is almost depleted by the voltage applied between the one main electrode 29 and the other main electrode 20. Further, a potential barrier is formed in a part of the high resistance layer portions 24 and 22 sandwiched by the p + gate 25 as viewed from the n + region 28, and its height is between the voltage of the gate electrode 27 and the n + electrode 29 and the electrode 20. The size and impurity density between the p + gate regions 25 and the thickness of the high resistance layers 22 and 24 are selected so as to be changed by the electrostatic induction effect due to the voltage of. Other regions 24, 25 as the high resistance layer region 22,
By using a semiconductor having a narrower band gap than 21 and 28, the sensitivity in the long wavelength region of the wavelength of light incident from the surface is increased. Since a strong electric field is more likely to occur, p + (25) n
- (24) n - (22 ) n + or p + (21) dimensioned to avalanche electric field is generated in the region of 22 between the static an impurity density and the like are distributed around avalanche photodiode of the gate if selected An inductive photodetector will be formed.
An optical signal received at high speed and with high sensitivity by the avalanche diode formed between the p + gate 25 and the high impurity density region 21 is extracted from between the main electrodes 29 and 20 as a further amplified signal. Electron-hole pairs are generated in the almost depleted high resistance layer regions 22 and 24, of which holes are p + gate regions.
N + region accumulated in gate 25 by the electrostatic induction effect of gate 25
The height of the potential barrier generated near 28 changes. A p-type semiconductor may be used instead of the high resistance region 24. If the p-type region is completely depleted, the operation is equivalent to that of the static induction phototransistor, but if the p-type region has a neutral region remaining, it becomes a bipolar phototransistor. When the substrate 21 is p + type, it becomes a photothyristor.
Alternatively, the entire high resistance layer region 24 or a part near the region 22 may be formed of a semiconductor (for example, n InGaAs) having a narrow bandgap like the high resistance layer region 22. The high impurity density region 21 has the same conductivity type as the gate region 25 (in the example of FIG. 1,
In the case of p + ), the embodiment of FIG. 1 operates as an electrostatic induction photothyristor. In this case, the hetero interface between the region 21 and the region 22 having a narrow forbidden band is a region where electrons among electron holes generated by light are accumulated. More holes are amplified by this accumulation of electrons and more holes are transferred from p + region 21 to region 22.
Will be injected into. Although InP-InGaAs is shown as an example of the semiconductor forming each part, the present invention is not limited to this, and other binary systems such as GaAs-GaAlAs and GaAs-InGaAsP,
A combination of ternary and quaternary compound semiconductors may be used.
Although the planar gate structure is shown in the embodiment of the present invention, the gate may have a buried gate, a cut gate, a MOS (MIS) gate, a hetero gate, or a Schottky gate.

〔発明の効果〕〔The invention's effect〕

本発明による静電誘導型光検出器では、主としてゲート
・ドレインもしくはゲート・アノード間に禁制帯幅の狭
い半導体を用いることを特徴としており、この領域の禁
制帯幅が狭いことから光検出波長としては長波長感度が
増大する。更にこの領域の電界強度を高くすることが容
易となるため、例えばアバランシ電界強度となれば、こ
のゲート・ドレインもしくはゲート・アノード間のアバ
ランシダイオードによって高速・高感度に受光可能とな
り、従来の静電誘導型光検出器よりも更に高速・高感度
となる。
The electrostatic induction photodetector according to the present invention is mainly characterized by using a semiconductor having a narrow forbidden band between the gate and the drain or the gate and the anode. Has increased long wavelength sensitivity. Furthermore, since it becomes easy to increase the electric field strength in this region, if the avalanche electric field strength is reached, light can be received at high speed and high sensitivity by the avalanche diode between the gate and drain or the gate and anode. Higher speed and higher sensitivity than the electric induction type photodetector.

本発明は、従来の製造方法例えばMOCVD法、光CVD法、光
エピタキシャル法、分子層エピタキシャル法を用いて製
造することが容易であり、かつ高速・高感度な長波長光
通信用光検出器となることから工業的価値の高いもので
ある。
The present invention provides a photodetector for long-wavelength optical communication that is easy to manufacture using a conventional manufacturing method such as a MOCVD method, an optical CVD method, an optical epitaxial method, and a molecular layer epitaxial method, and has high speed and high sensitivity. Therefore, it has high industrial value.

【図面の簡単な説明】[Brief description of drawings]

第1図は本発明の実施例を示し、第2図は従来の静電誘
導型光検出器の断面構造例である。 20……ドレインもしくはアノードとなる主電極、21……
n+もしくはp+の高不純物密度領域、22……他の領域より
禁制帯幅の狭くなされた高抵抗層、24……高抵抗層、25
……ゲート拡散領域、28……ソースもしくはカソード領
域、29……ソースもしくはカソード電極、26……絶縁性
光学的反射防止膜、27……ゲート電極。
FIG. 1 shows an embodiment of the present invention, and FIG. 2 shows an example of a sectional structure of a conventional static induction photodetector. 20 …… Main electrode that serves as drain or anode, 21 ……
n + or p + high impurity density region, 22 …… high resistance layer with a narrower band gap than other regions, 24 …… high resistance layer, 25
...... Gate diffusion region, 28 …… Source or cathode region, 29 …… Source or cathode electrode, 26 …… Insulating optical antireflection film, 27 …… Gate electrode.

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】半導体基板上に、該基板より禁制帯幅の小
さい第二の高抵抗層と第一の高抵抗層を順に有し、かつ
各領域間にそれぞれヘテロ接合を具備して構成され、前
記第一の高抵抗層中に形成された第一の導電型の高不純
物密度ゲート拡散領域と、前記ゲート拡散領域に挾まれ
て前記第一の高抵抗層中に形成された第二の導電型で前
記ゲート拡散領域とは反対導電型の高不純物密度領域か
らなる第一の主電極領域と、前記ゲート及び第一の主電
極領域の形成された第一の主表面とは反対側の第二の高
抵抗層と接合面を形成する第一もしくは第二の導電型の
高不純物密度領域からなる第二の主電極領域と、第一及
び第二の主電極領域上に形成された第一及び第二の電極
と、前記ゲート拡散領域を含む前記第一の高抵抗層上に
形成された絶縁性・光学的反射防止膜と、前記ゲート拡
散領域上に形成されたゲート電極とを有し、第二の高抵
抗層を形成する半導体のみが他の領域の半導体の禁制帯
幅より小さい禁制帯幅を有する半導体で形成され、各部
の寸法が第二の主電極領域と前記ゲート領域に加わる電
圧によって容易にアバランシ電界が発生すべくなされ、
かつ前記第一の高抵抗層中もしくは第一及び第二の高抵
抗層中に、前記ゲート拡散領域と第一の主電極領域間の
電圧及び前記ゲート拡散領域と第二の主電極領域間の電
圧によって電位障壁が形成されて前記第一及び第二の高
抵抗層領域はほとんど空乏化され、前記ゲート拡散領域
及び前記第二の主電極領域の電位によって前記電位障壁
の高さが変化するような寸法に選ばれ、前記電位障壁高
さによって第一及び第二の主電極間を流れる多数キャリ
アが制御されることを特徴とする静電誘導型光検出器。
1. A semiconductor substrate having a second high resistance layer and a first high resistance layer having a band gap smaller than that of the substrate in this order, and a heterojunction provided between each region. A first conductivity type high impurity density gate diffusion region formed in the first high resistance layer, and a second diffusion layer formed in the first high resistance layer sandwiched by the gate diffusion region. A first main electrode region formed of a high impurity density region of a conductivity type opposite to the gate diffusion region and a first main surface on which the gate and the first main electrode region are formed are provided on the opposite side. A second main electrode region formed of a first or second conductivity type high impurity density region forming a junction surface with the second high resistance layer, and a second main electrode region formed on the first and second main electrode regions. An insulating property formed on the first high resistance layer including the first and second electrodes and the gate diffusion region; An optical antireflection film and a gate electrode formed on the gate diffusion region, and only the semiconductor forming the second high resistance layer has a forbidden band width smaller than the forbidden band width of the semiconductor in other regions. Formed by a semiconductor which has a size of each part so that an avalanche electric field is easily generated by a voltage applied to the second main electrode region and the gate region,
And in the first high resistance layer or in the first and second high resistance layers, the voltage between the gate diffusion region and the first main electrode region and the voltage between the gate diffusion region and the second main electrode region. A potential barrier is formed by the voltage so that the first and second high resistance layer regions are almost depleted, and the height of the potential barrier is changed by the potentials of the gate diffusion region and the second main electrode region. The electrostatic induction photodetector is characterized in that the majority carriers flowing between the first and second main electrodes are controlled by the height of the potential barrier.
JP59179982A 1984-08-28 1984-08-28 Static induction type semiconductor photodetector Expired - Fee Related JPH0682859B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP59179982A JPH0682859B2 (en) 1984-08-28 1984-08-28 Static induction type semiconductor photodetector

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59179982A JPH0682859B2 (en) 1984-08-28 1984-08-28 Static induction type semiconductor photodetector

Publications (2)

Publication Number Publication Date
JPS6158279A JPS6158279A (en) 1986-03-25
JPH0682859B2 true JPH0682859B2 (en) 1994-10-19

Family

ID=16075383

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59179982A Expired - Fee Related JPH0682859B2 (en) 1984-08-28 1984-08-28 Static induction type semiconductor photodetector

Country Status (1)

Country Link
JP (1) JPH0682859B2 (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5445974A (en) * 1993-03-31 1995-08-29 Siemens Components, Inc. Method of fabricating a high-voltage, vertical-trench semiconductor device
KR100348700B1 (en) * 2000-09-16 2002-08-13 서울대학교 공과대학 교육연구재단 Optical Device and Manufacturing Method of the Same

Also Published As

Publication number Publication date
JPS6158279A (en) 1986-03-25

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