JPS6157753U - - Google Patents
Info
- Publication number
- JPS6157753U JPS6157753U JP14249984U JP14249984U JPS6157753U JP S6157753 U JPS6157753 U JP S6157753U JP 14249984 U JP14249984 U JP 14249984U JP 14249984 U JP14249984 U JP 14249984U JP S6157753 U JPS6157753 U JP S6157753U
- Authority
- JP
- Japan
- Prior art keywords
- horizontal
- frequency
- circuit
- voltage conversion
- conversion circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000006243 chemical reaction Methods 0.000 claims 3
- 230000035945 sensitivity Effects 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 5
- 239000003990 capacitor Substances 0.000 description 1
- 238000001514 detection method Methods 0.000 description 1
- 230000010355 oscillation Effects 0.000 description 1
Landscapes
- Synchronizing For Television (AREA)
- Details Of Television Scanning (AREA)
Description
第１図は本考案マルチ走査型テレビジヨン受像
機の要部の一実施例を示すブロツク図、第２図は
第１図の説明に供する略線図、第３図はマルチ走
査型テレビジヨン受像機の例を示すブロツク図、
第４図は第３図の水平偏向系を抜き出して示す構
成図、第５図及び第６図は夫々第３図の垂直偏向
系を抜き出して示す構成図である。
１，２０Ｓ及び２１Ｓは夫々入力端子、１０は
ＡＦＣ回路、１２は水平発振回路、３１はＦＶＣ
、３４はＶＣＯ、４５は検出回路、４８はＬＰＦ
、８２はコンデンサ、８６はバツフアアンプ、８
７はトランジスタ、８８，８９，９０及び９２は
夫々抵抗器、９１及び９３は夫々第１及び第２の
スイツチ回路、９４は比較回路である。
Fig. 1 is a block diagram showing an embodiment of the essential parts of the multi-scanning television receiver of the present invention, Fig. 2 is a schematic diagram for explaining Fig. 1, and Fig. 3 is a multi-scanning television receiver. A block diagram showing an example of the machine,
4 is a block diagram showing the horizontal deflection system extracted from FIG. 3, and FIGS. 5 and 6 are block diagrams showing the vertical deflection system extracted from FIG. 3, respectively. 1, 20S and 21S are input terminals, 10 is an AFC circuit, 12 is a horizontal oscillation circuit, and 31 is an FVC
, 34 is a VCO, 45 is a detection circuit, 48 is an LPF
, 82 is a capacitor, 86 is a buffer amplifier, 8
7 is a transistor, 88, 89, 90 and 92 are resistors, 91 and 93 are first and second switch circuits, respectively, and 94 is a comparison circuit.
Claims (1)
路に加え、該周波数−電圧変換回路の出力電圧を
水平偏向回路に加え、該水平偏向回路の水平周波
数を切り換えて異なる水平周波数の入力信号を受
像するマルチ走査型テレビジヨン受像機において
、上記水平同期信号が印加されるＡＦＣ回路に上
記周波数−電圧変換回路の上記出力電圧を印加し
、上記ＡＦＣ回路の感度を上記入力信号の上記水
平周波数によらず一定化するようにしたことを特
徴とするマルチ走査型テレビジヨン受像機。 A horizontal synchronization signal of the input signal is applied to a frequency-voltage conversion circuit, an output voltage of the frequency-voltage conversion circuit is applied to a horizontal deflection circuit, and the horizontal frequency of the horizontal deflection circuit is switched to receive input signals of different horizontal frequencies. In a multi-scan television receiver, the output voltage of the frequency-voltage conversion circuit is applied to the AFC circuit to which the horizontal synchronizing signal is applied, and the sensitivity of the AFC circuit is adjusted independently of the horizontal frequency of the input signal. A multi-scanning television receiver characterized in that it is made constant.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14249984U JPS6157753U (en) | 1984-09-20 | 1984-09-20 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14249984U JPS6157753U (en) | 1984-09-20 | 1984-09-20 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6157753U true JPS6157753U (en) | 1986-04-18 |
Family
ID=30700823
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP14249984U Pending JPS6157753U (en) | 1984-09-20 | 1984-09-20 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6157753U (en) |
-
1984
- 1984-09-20 JP JP14249984U patent/JPS6157753U/ja active Pending
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