JPS6156873B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an insulated gate field effect transistor that has small stray capacitance and is capable of high frequency operation, and a method for manufacturing the same.

In order to increase the frequency and speed of insulated gate field effect transistors, stray capacitance, such as gate
Capacitance between source Cgs, capacitance between gate and drain
It is necessary to minimize Cgd, etc. Therefore,
Si field-effect transistors employ self-alignment techniques using diffusion or ion implantation. In this self-alignment method, for example, after forming a gate oxide film and a gate electrode, diffusion or ion implantation is performed using the gate oxide film and gate electrode as a mask.
Creating source/drain. To create such a structure, it is necessary that the electrical properties of the interface between the Si and the oxide film do not deteriorate at high temperatures during the heat treatment after diffusion or ion implantation. Furthermore, since thermosetting SiO ₂ is used for the gate oxide film, the above-mentioned self-alignment method is possible.

By the way, since compound semiconductors such as GaAs and InP do not have a single component, thermal decomposition becomes a problem, and high-temperature treatment causes deterioration of their surface crystals. For this reason, although good interface properties are maintained even after diffusion heat treatment, no insulating film has been found that prevents the crystal surface from deteriorating. has a different structure and manufacturing method. To explain this using an inverted n-channel InP-insulated gate field effect transistor, as shown in FIG. 1, an n-type diffusion layer 2 is first formed on the entire surface of a p-type or semi-insulating InP substrate 1. This may be accomplished by n-type epitaxial growth or ion implantation, but the simplest method uses thermal diffusion. In FIG. 1, a sulfur diffusion layer is used as the n-type diffusion layer 2. Next, after forming a source electrode 3a and a drain electrode 3b, a resistor 6 is formed as a mask on the n-type diffusion layer 2 as shown in FIG. Part 7)
The surface of the p-type or semi-insulating substrate 1 is exposed as shown in FIG. 1c. Thereafter, the resist 6 is removed, and a gate insulating film 4 and a gate electrode 5 are formed as shown in FIG. 1a.

The gate-drain capacitance Cgd and gate-source capacitance Cgs, which are stray capacitances of the insulated gate field effect transistor configured in this way, are determined by the overlapped portions 8a and 8b of the gate electrode 5 with the source region or drain region. proportional to size. Therefore, in order to increase the speed of this field effect transistor, it is necessary to reduce this overlap, but this requires highly accurate photoetching technology, especially mask alignment, and this accuracy determines the high frequency characteristics. There was a problem that I was exposed.

In order to eliminate the drawbacks of the above-mentioned conventional example, the present invention provides a gate-drain capacitance Cgd, which is a stray capacitance,
The present invention provides a field effect transistor with reduced gate-source capacitance Cgs and a method for manufacturing the same. Hereinafter, embodiments will be described in detail with reference to the drawings.

FIG. 2 shows an embodiment of the present invention, and the same reference numerals as in FIG. 1 indicate the same parts.
The difference is that another insulating film 9 is provided in the overlapping portions 8a and 8b of the drains to reduce stray capacitance. This insulating film 9 may be made of the same material as the gate insulating film 4 or a different material, but it is more advantageous to have a dielectric constant smaller than that of the gate insulating film 4. For example, if the dielectric constant of the gate insulating film 4 is ε _g , the dielectric constant of the newly provided insulating film 9 is ε _a , and the thicknesses of each film are d _g and d _a , then the stray capacitance of the overlapping portion, for example, C _gd is , when there is no insulating film 9, C _gd =ε _g /d _g , and when there is an insulating film 9, C' _gd = 1/(d _g /ε _g +d _a /ε _a ). For example, the gate insulating film 4 is made of Al ₂ O ₃ (ε~8)
The thickness is 1000 Å, and the insulating film 9 is
If it is made of SiO ₂ (ε~4) and its thickness is 2000 Å, then C′ _gd /C _gd 〓1/5. That is, even if the overlapping area is the same, the stray capacitance will be 1/5. From another perspective, even if the overlap length is 1 μm, it becomes equivalent to an overlap length of 0.2 μm due to the insulating film 9, and even a photo-etch technique with an accuracy of 1 μm is the same as a photo-etch with an accuracy of 0.2 μm.

Next, the manufacturing method of this example will be explained. First, as shown in FIG. 2b, in order to etch the gate portion 7, the insulating film 9 is etched using the resist 10 as a mask, and then the n-type diffusion layer 2 is etched, and the InP substrate 1 is etched. . Next, as shown in FIG. 2c, the resist 10 is removed, and a gate insulating film 4 and a gate electrode 5 are formed as shown in FIG. 2a.

In this embodiment configured as described above, the entire portion of the InP substrate other than the etched portion is covered with the insulating film 9, that is, the insulating film 9 is located entirely in the overlapping portion of the source or drain portion of the gate electrode. Therefore, the stray capacitance in the overlapping portion shown in FIG. 2a can be reduced. At this time, the insulating film 9
Since it can be regarded as a mask for etching the InP substrate 1, this structure and its manufacturing method can be called a self-alignment method using an etching mask.

FIG. 3 shows another embodiment of the present invention, and the same reference numerals as in FIG. 2 indicate the same parts. In this embodiment, the InP substrate of the gate section 7 is etched deeply. When etching or increasing underetching, the slope of the wall of the etched InP substrate is gentle, and this portion 1
The stray capacitance of 1a and 11b is the total stray capacitance (part 8
a, 8b) cannot be ignored. Even in such a case, the total stray capacitance can be reduced by providing the insulating film 9 as shown in FIG. 3b. To explain the manufacturing method of this example,
First, when etching the InP substrate, the portion of the insulating film 9 that is etched as shown by the dotted line 12 is left as is, and the gate insulating film 4 is formed by leaving the part of the insulating film 9 that remains as a ridge as is, in the same manner as in the previous embodiment. It is possible to introduce the effect of self-alignment.

It goes without saying that the present invention is applicable not only to InP and GaAs but also to insulated gate field effect transistors using other compound semiconductors as substrates. Further, as for the insulating film 9 to be newly introduced, it is advantageous that the dielectric constant is as small as possible and the insulating property is as high as possible. Further, there is no restriction on the material of the gate insulating film, as long as it is not damaged at high temperatures when forming the gate insulating film.

As explained above, according to the present invention, by providing another insulating film in the overlapping part with the source part or drain part of the gate, it is possible to reduce the stray capacitance in the overlapping part, and this insulating film is applied to the gate part. By using it as a mask for etching, it brings about a so-called self-alignment effect, so even when the accuracy of photoetching, especially the accuracy of mask alignment, is the same, it is possible to effectively reduce the overlapping area, which reduces the electric field effect. Reduces stray capacitance in transistors, providing advantages in high-speed, high-frequency operation.

[Brief explanation of the drawing]

FIG. 1a is a cross-sectional view of a conventional insulated gate field effect transistor, FIGS. 1b and c are cross-sectional views of FIG. 1a during manufacture, and FIG. 2a is a cross-sectional view of an embodiment of the present invention. , FIGS. 2b and 2c are sectional views of FIG. 2a during manufacture, FIG. 3a is a sectional view of another embodiment of the present invention, and FIG. 3b is a sectional view of FIG. 3a during manufacture. FIG. DESCRIPTION OF SYMBOLS 1...p-type or semi-insulating InP substrate, 2...n-type diffusion layer, 3...source a, drain b electrode, 4...
...Gate insulating film, 5...Gate electrode, 9...Insulating film for reducing stray capacitance, 10...Photoresist.

Claims (1)

[Claims] 1. A p-type or semi-insulating substrate, an n-type diffusion layer formed on this substrate, a first insulating film formed on the n-type diffusion layer excluding the gate portion, This first
a gate portion formed using an insulating film as a mask; a second insulating film formed on the insulating film;
and a gate electrode formed on an insulating film of
A field effect transistor characterized in that the first insulating film is used as an insulating film for reducing gate-source capacitance and gate-drain capacitance. 2. Form an n-type diffusion layer on a p-type or semi-insulating substrate, form a first insulating film on the n-type diffusion layer, and etch the gate portion using the first insulating film as a mask. A method for manufacturing a field effect transistor, comprising forming a second insulating film on the first insulating film and the gate portion, and further forming a gate electrode on the second insulating film.