JPS6156685B2 - - Google Patents

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Publication number
JPS6156685B2
JPS6156685B2 JP52064178A JP6417877A JPS6156685B2 JP S6156685 B2 JPS6156685 B2 JP S6156685B2 JP 52064178 A JP52064178 A JP 52064178A JP 6417877 A JP6417877 A JP 6417877A JP S6156685 B2 JPS6156685 B2 JP S6156685B2
Authority
JP
Japan
Prior art keywords
circuit
collector
base
transistor
pnp transistor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP52064178A
Other languages
Japanese (ja)
Other versions
JPS53147943A (en
Inventor
Yukio Myazaki
Mitsugi Takeda
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP6417877A priority Critical patent/JPS53147943A/en
Publication of JPS53147943A publication Critical patent/JPS53147943A/en
Publication of JPS6156685B2 publication Critical patent/JPS6156685B2/ja
Granted legal-status Critical Current

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Description

【発明の詳細な説明】 この発明は、最適な電流検知装置を備えた地絡
検出装置に関するものである。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a ground fault detection device equipped with an optimal current detection device.

従来、地絡検出装置(漏電遮断器)は、機械的
要素により構成されていたが、その特性の悪さに
より数年前より電子化が進められている。電子化
により地絡電流を電圧に変換する零相変流器
(Zero Current Transformer)が小形化し、コス
ト的なメリツトも大きくなつた。第1図に従来の
地絡検出装置の電子回路の概略構成を示す。
Conventionally, ground fault detection devices (earth leakage circuit breakers) have been composed of mechanical elements, but due to their poor characteristics, electronic devices have been promoted for several years. Computerization has made the zero-phase current transformer, which converts ground fault current into voltage, smaller and has greater cost advantages. FIG. 1 shows a schematic configuration of an electronic circuit of a conventional ground fault detection device.

第1図において、1は電路、2は遮断器、3は
零相変流器、4は差動増幅器、5は時延回路、6
はシユミツト回路、7は電源電圧安定化用のツエ
ナーダイオード、8はサイリスタ、9は遮断コイ
ル、10は差動増幅器4、時延回路5、シユミツ
ト回路6にかかる電源E6の電位を決める電圧ド
ロツプ用の抵抗器、11は平滑用コンデンサ、1
2は整流ダイオード、13は交流電源である。零
相変流器3の出力E1,E2は差動増幅器4の反
転、非反転入力に与えられ、差動増幅器4の出力
E3は時延回路5の入力に与えられ、時延回路5
の出力E4はシユミツト回路6の入力に与えら
れ、シユミツト回路6の出力E5がサイリスタ8
を駆動し、遮断器2を働かせる構成となつてい
る。零相変流器3は電路1にアンバランスが生じ
た時に、その二次側に電圧を発生する一種のトラ
ンスである。この構成における遮断動作を以下に
説明する。
In FIG. 1, 1 is an electric circuit, 2 is a circuit breaker, 3 is a zero-phase current transformer, 4 is a differential amplifier, 5 is a time delay circuit, and 6
is a Schmitts circuit, 7 is a Zener diode for stabilizing the power supply voltage, 8 is a thyristor, 9 is a cutoff coil, 10 is a voltage drop that determines the potential of the power supply E6 applied to the differential amplifier 4, time delay circuit 5, and Schmitts circuit 6 . 11 is a smoothing capacitor, 1
2 is a rectifier diode, and 13 is an AC power source. The outputs E 1 and E 2 of the zero-phase current transformer 3 are given to the inverting and non-inverting inputs of the differential amplifier 4, and the outputs of the differential amplifier 4 are
E 3 is given to the input of the time delay circuit 5, and the time delay circuit 5
The output E 4 of is given to the input of the Schmitt circuit 6, and the output E 5 of the Schmitt circuit 6 is applied to the thyristor 8.
The structure is such that the circuit breaker 2 is activated by driving the circuit breaker 2. The zero-phase current transformer 3 is a type of transformer that generates a voltage on its secondary side when an imbalance occurs in the electric line 1. The shutoff operation in this configuration will be explained below.

地絡が起こると、零相変流器3の出力E1,E2
に電圧が発生し、その出力E1,E2は差動増幅器
4で増幅され、その出力E3は時延回路5で遅延
され、時延回路5の出力E4がシユミツト回路6
で波形整形され、その出力E5でサイリスタ8を
駆動し、遮断コイル9に電流が流れ電路1を遮断
する。
When a ground fault occurs, the outputs E 1 and E 2 of zero-phase current transformer 3
A voltage is generated at , the outputs E 1 and E 2 are amplified by the differential amplifier 4, the output E 3 is delayed by the delay circuit 5, and the output E 4 of the delay circuit 5 is sent to the Schmitts circuit 6.
The waveform is shaped by the output E5 , which drives the thyristor 8, and current flows through the cutoff coil 9 to cut off the electric path 1.

ところがこの方式では、非常に使用し難い問題
点がある。それは、サイリスタ8が不動作時と、
動作させる時とで、ほゞサイリスタ8のゲート電
流分だけ電源電流、すなわち電源E6から電源E7
に向つて流れる電流に差があること、つまりサイ
リスタ8が動作時、ゲート電流が流れることに応
じて抵抗10での電圧降下が不動作時より大きい
ことで、サイリスタ8を完全に動作させるには、
ゲート電流が流れた時にも、電源E6を正常な電
位に保つておく必要がある。そのために、第1の
ものにあつては、サイリスタ8の不動作時にサイ
リスタ8のゲート電流分をツエナーダイオード7
に常に流しておき、サイリスタ8の動作時ゲート
電流が流れても電源E6の電位が正常な電位に保
つようにしてあるものである。そうでないと、シ
ユミツト回路6が動作時、抵抗器10での電圧降
下により電源E6の電圧が下がり、シユミツト回
路6には所望の電源電圧が印加されなくなるの
で、その出力E5の電圧が下がり、サイリスタ8
をオンできなくなる。従つて電圧ドロツプ用の抵
抗器10には、ほぼゲート電流分だけ多くの電流
を流す必要があり、交流電圧100Vおよび200Vな
どから電圧を降下させるには、非常に大きな電力
に耐え得る抵抗器10が必要で、その形状も大き
く、地絡検出装置の小形化が実現できなかつた。
また100V、200V兼用の地絡検出装置(漏電遮断
器)を作る上にも抵抗器10の抵抗値は100V用
に依存し、しかも多くの電流を流すようになつて
いるため、200V用で使用した場合には、抵抗器
10での消費電力が大きくなるため、100V専用
に比し、さらに大きな電力に耐え得るものが必要
となり、形状も大きくなるという問題があつた。
However, this method has a problem that makes it extremely difficult to use. That is when thyristor 8 is not operating,
When operating, the power supply current is approximately equal to the gate current of thyristor 8, that is, from power supply E 6 to power supply E 7
In other words, when the thyristor 8 is in operation, the voltage drop across the resistor 10 is larger as the gate current flows than when the thyristor 8 is not in operation. ,
Even when the gate current flows, it is necessary to keep the power supply E 6 at a normal potential. Therefore, in the first case, when the thyristor 8 is not operating, the gate current of the thyristor 8 is transferred to the Zener diode 7.
is kept flowing at all times, so that even if the gate current flows during operation of the thyristor 8, the potential of the power source E6 is maintained at a normal potential. Otherwise, when the Schmitts circuit 6 is operating, the voltage of the power supply E 6 will drop due to the voltage drop across the resistor 10, and the desired power supply voltage will no longer be applied to the Schmitts circuit 6, so the voltage of its output E 5 will drop. , thyristor 8
cannot be turned on. Therefore, it is necessary to allow a current as large as the gate current to flow through the voltage drop resistor 10, and in order to drop the voltage from an AC voltage of 100V or 200V, a resistor 10 that can withstand extremely large power is required. The size of the ground fault detection device is large, making it impossible to downsize the ground fault detection device.
In addition, when making a ground fault detection device (earth leakage breaker) that can be used for both 100V and 200V, the resistance value of resistor 10 depends on the 100V application, and since it allows a large amount of current to flow, it is used for the 200V application. In this case, the power consumption of the resistor 10 becomes large, so a resistor 10 that can withstand even higher power than a 100V-only resistor is required, and the shape becomes larger.

この発明は、上述の点にかんがみなされたもの
で、シユミツト回路を例えばNPNトランジスタ
と、PNPトランジスタで構成されるラツチ回路の
動作をする波形整形回路としたところにあり、サ
イリスタ8の動作を確実にし、電子回路での消費
電力を最小限に減らし、小形化を図るとともに、
100V、200V兼用の電子回路にも適用可能化を図
つたところにある。その一例を第2図に示す。
This invention has been made in consideration of the above points, and consists in using a Schmitt circuit as a waveform shaping circuit that operates as a latch circuit composed of, for example, an NPN transistor and a PNP transistor, thereby ensuring the operation of the thyristor 8. In addition to minimizing power consumption and miniaturization of electronic circuits,
The aim is to make it applicable to both 100V and 200V electronic circuits. An example is shown in FIG.

第2図において、E4が入力で、61,62が
NPNトランジスタ、63,64はPNPトランジ
スタ、65,66,67は抵抗器、E5は出力、
E6,E7は電源で、電源E7が最も低電位である。
第2図においてNPNトランジスタ61,62、
PNPトランジスタ63でサイリスタを構成し、
PNPトランジスタ64で増幅して出力E5に高電
位を発生する。すなわち、入力E4にNPNトラン
ジスタ61のベース、エミツタオン電圧スレシヨ
ルト値以上の電位がかゝるとNPNトランジスタ
61がオン状態になり、PNPトランジスタ63の
ベース電流を引張り、PNPトランジスタ63でそ
の電流がhFE倍され、NPNトランジスタ62の
ベース電流となり、その電流がhFE倍されてPNP
トランジスタ63のベース電流となる。すなわ
ち、NPNトランジスタ62とPNPトランジスタ
63で正帰還がかゝり、サイリスタと同様な動作
をする。
In Figure 2, E 4 is the input, and 61 and 62 are
NPN transistor, 63, 64 are PNP transistors, 65, 66, 67 are resistors, E 5 is output,
E 6 and E 7 are power supplies, and power supply E 7 has the lowest potential.
In FIG. 2, NPN transistors 61, 62,
Configure a thyristor with PNP transistor 63,
It is amplified by the PNP transistor 64 to generate a high potential at the output E5 . That is, when a potential equal to or higher than the base-emitter on-voltage threshold value of the NPN transistor 61 is applied to the input E4 , the NPN transistor 61 turns on, pulling the base current of the PNP transistor 63, and the current becomes h in the PNP transistor 63. The current is multiplied by FE and becomes the base current of the NPN transistor 62, and the current is multiplied by h FE and becomes the base current of the NPN transistor 62.
This becomes the base current of the transistor 63. That is, positive feedback occurs between the NPN transistor 62 and the PNP transistor 63, and the operation is similar to that of a thyristor.

なお、第2図の回路において、NPNトランジ
スタ61や62のベース・エミツタにダイオード
を並列に接続したりPNPトランジスタ63のエミ
ツタ・ベースに並列にダイオードを接続したりす
ることにより、トランジスタ61,62,63で
構成されるサイリスタのループゲインを適当にコ
ントロールすることができる。そのような配慮を
施すことにより、サージ、ノイズに強いサイリス
タを構成することができる。
In the circuit shown in FIG. 2, the transistors 61, 62, The loop gain of the thyristor 63 can be appropriately controlled. By taking such considerations, it is possible to construct a thyristor that is resistant to surges and noise.

第1図のシユミツト回路6の代りに第2図に示
した波形整形回路6′を応用した地絡検出装置の
一実施例を第3図に示す。
FIG. 3 shows an embodiment of a ground fault detection device in which the waveform shaping circuit 6' shown in FIG. 2 is used instead of the Schmitt circuit 6 shown in FIG. 1.

第3図の実施例は第1図に比べ、ツエナーダイ
オード7がないことと、シユミツト回路6が第2
図に示す波形整形回路6′となつている点で異な
つている。さて、地絡が起つていない時、波形整
形回路6′には電流が流れず、その時、差動増幅
器4、時延回路5を駆動できる電源E6の電圧に
なるように抵抗器10の抵抗値を選ぶ。地絡が起
ると、零相変流器3の出力E1,E2に電位が発生
し、その出力E1,E2は差動増幅器4で増幅さ
れ、その出力E3が時延回路5で遅延され、時延
回路5の出力がある所定の電位(第3図の場合V
BE)に達すると波形整形回路6′が動作し、その
出力インピーダンスが低いため(第2図の抵抗器
66の抵抗値を低くしておく)、電源E6の電圧は
下がり、差動増幅器4、時延回路5に流れていた
電流が減り、それだけの電流がほゞサイリスタ8
のゲート電流となる。
The embodiment of FIG. 3 differs from the embodiment of FIG. 1 in that there is no Zener diode 7 and that the Schmitt circuit 6 is
The difference is that the waveform shaping circuit 6' shown in the figure is used. Now, when no ground fault has occurred, no current flows through the waveform shaping circuit 6', and at that time, the voltage of the resistor 10 is adjusted so that the voltage of the power source E6 is high enough to drive the differential amplifier 4 and the delay circuit 5. Choose a resistance value. When a ground fault occurs, a potential is generated at the outputs E 1 and E 2 of the zero-phase current transformer 3, and the outputs E 1 and E 2 are amplified by the differential amplifier 4, and the output E 3 is sent to the time delay circuit. 5, and the output of the time delay circuit 5 is at a predetermined potential (V in the case of FIG.
BE ), the waveform shaping circuit 6' operates, and since its output impedance is low (the resistance value of the resistor 66 in FIG. 2 is kept low), the voltage of the power supply E 6 decreases, and the differential amplifier 4 , the current flowing through the time delay circuit 5 decreases, and that much current flows through the thyristor 8.
The gate current will be .

なお、波形整形回路6′は電源E6が約2VBE
Vsat(Vsatは飽和電圧で約1.6V)になるまで、
出力に電位を発生させるため、サイリスタ8のゲ
ート電流を流し続けることができる。
In addition, the power supply E 6 of the waveform shaping circuit 6' is approximately 2V BE +
Until Vsat (Vsat is the saturation voltage of about 1.6V),
In order to generate a potential at the output, the gate current of the thyristor 8 can continue to flow.

したがつて、この装置にあつては、地絡発生
時、つまりサイリスタ8の制御時に、差動増巾回
路4、時延回路5に流れていた電流の減少分がほ
ぼサイリスタ8のゲート電流となるため、サイリ
スタ8の不動作時に第1図に示すもののように、
電源電流をほぼゲート電流分余分に流しておく必
要がなくなり、装置における消費電力を最小限に
減らすこと、特に抵抗10での消費電力を減らす
ことができ、装置の小型化が図れるとともに、抵
抗10での消費電力が減らせるため、100V、
200V兼用としても適用可能となるものである。
しかも、波形整形回路6′が電源E6が約2VBE
Dsatになるまで出力に電位を発生させ、例え増
巾器4の入力信号がなくなつてもサイリスタ8の
ゲート電流を流し続けているので、電流E6が交
流電源13の半波整流でも、半波整流のどの時点
で地絡が発生しようともサイリスタ8を確実に動
作でき(サイリスタが導通状態を保持するには、
アノード−カソード間にホールド電流を流す必要
があり、アノード−カソード間に所定電位印加さ
れていることを必要とし、所定電位以下のときの
みゲートにトリガパルスが加わつても、サイリス
タは導通しない。)、部品点数を減らせるととも
に、また、電源E6が交流電源13の全波整流で
も、電源E6が所定電位以下の時に地絡が発生し
ても、少なくとも所定電位以上になるまではサイ
リスタ8のゲート電流が流れているので、サイリ
スタ8を確実に動作できるものである。この発明
は、以上に述べたとおり波形整形回路として、ス
レシヨルド値をこえて導通した時に前記増幅器の
入力信号がなくなつても導通状態を保持し続け、
さらに前記波形整形回路の供給電圧が下がつても
導通状態を保持し続けるラツチ回路を用いたの
で、波形整形回路の導通時に増幅器および時延回
路の電流を減少し、この減少した分をサイリスタ
のゲート電流として供給することができる。その
ため、地絡検出装置の電子回路で消費する電力を
最小限に減らし、良好な特性を持ち、確実にサイ
リスタを動作できる地絡検出装置を提供すること
ができる。そして、その消費電力の減少により、
100V、200V兼用(交流電源電圧範囲としては、
80〜242V)の地絡検出装置の電子回路部が簡単
に構成され、その形状も小らくなり、製造者側に
とつても需要者側にとつてもそのメリツトは非常
に大なるものである。らなみに、第3図の構成に
おける地絡検出装置で、その電子回路部の消費電
流が、300μAの集積回路を完成することができ
た。この場合、100V、200V兼用の地絡検出装置
が実現でき、電圧ドロツプ用の抵抗器の消費電力
が、従来に比べ極端に小さくなつた。
Therefore, in this device, when a ground fault occurs, that is, when controlling the thyristor 8, the decrease in the current flowing through the differential amplifier circuit 4 and the time delay circuit 5 is almost equal to the gate current of the thyristor 8. Therefore, when the thyristor 8 is not operating, as shown in FIG.
It is no longer necessary to keep the power supply current approximately equal to the gate current flowing, and the power consumption in the device can be reduced to a minimum, especially the power consumption in the resistor 10. 100V,
It can also be used for 200V.
Moreover, the waveform shaping circuit 6' has a power supply E 6 of approximately 2V BE +
A potential is generated at the output until it reaches Dsat, and even if the input signal to the amplifier 4 disappears, the gate current of the thyristor 8 continues to flow, so even if the current E 6 is half-wave rectified by the AC power supply 13, Thyristor 8 can be operated reliably even if a ground fault occurs at any point during wave rectification (in order for the thyristor to maintain a conductive state,
It is necessary to flow a hold current between the anode and the cathode, and it is necessary to apply a predetermined potential between the anode and the cathode, and even if a trigger pulse is applied to the gate only when the potential is below the predetermined potential, the thyristor will not conduct. ), the number of parts can be reduced, and even if the power source E 6 is a full-wave rectifier of the AC power source 13, even if a ground fault occurs when the power source E 6 is below a predetermined potential, the thyristor can be used at least until the potential exceeds the predetermined potential. Since the gate current of 8 is flowing, the thyristor 8 can be operated reliably. As described above, the present invention, as a waveform shaping circuit, continues to maintain a conductive state even when the input signal of the amplifier disappears when it becomes conductive beyond a threshold value,
Furthermore, since we used a latch circuit that continues to maintain conduction even when the supply voltage of the waveform shaping circuit decreases, the current in the amplifier and delay circuit is reduced when the waveform shaping circuit is conductive, and this decreased current is transferred to the thyristor. Can be supplied as gate current. Therefore, it is possible to provide a ground fault detection device that reduces the power consumed by the electronic circuit of the ground fault detection device to a minimum, has good characteristics, and can operate the thyristor reliably. And, due to the reduction in power consumption,
Can be used for both 100V and 200V (AC power supply voltage range:
The electronic circuit section of the ground fault detection device (80 to 242V) can be easily configured and its size can be reduced, which is a huge benefit for both the manufacturer and the consumer. . Incidentally, with the ground fault detection device having the configuration shown in FIG. 3, we were able to complete an integrated circuit whose electronic circuit section consumed a current of 300 μA. In this case, a ground fault detection device that can be used for both 100V and 200V has been realized, and the power consumption of the voltage drop resistor has been significantly reduced compared to conventional methods.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は従来の地絡検出装置を示す回路図、第
2図はこの発明に用いる波形整形回路の一例を示
す回路図、第3図は第2図の波形整形回路を用い
たこの発明の一実施例を示す回路図である。 図中、1は電路、2は遮断器、3は零相変流
器、4は差動増幅器、5は時延回路、6′は波形
整形回路、8はサイリスタ、9は遮断コイル、1
0は抵抗器、11は平滑用コンデンサ、12は整
流ダイオード、13は交流電源である。なお、図
中の同一符号は同一または相当部分を示す。
Fig. 1 is a circuit diagram showing a conventional ground fault detection device, Fig. 2 is a circuit diagram showing an example of a waveform shaping circuit used in the present invention, and Fig. 3 is a circuit diagram showing an example of a waveform shaping circuit used in the present invention. FIG. 2 is a circuit diagram showing an example. In the figure, 1 is an electric circuit, 2 is a circuit breaker, 3 is a zero-phase current transformer, 4 is a differential amplifier, 5 is a time delay circuit, 6' is a waveform shaping circuit, 8 is a thyristor, 9 is a cutoff coil, 1
0 is a resistor, 11 is a smoothing capacitor, 12 is a rectifier diode, and 13 is an AC power source. Note that the same reference numerals in the figures indicate the same or corresponding parts.

Claims (1)

【特許請求の範囲】 1 被検出電流に応じた信号を増幅する増幅器、
その出力を遅延させる時延回路、その出力を受け
る波形整形回路、およびその出力によりサイリス
タのゲートに電流を流して前記サイリスタをオン
として遮断器を動作させる地絡検出装置におい
て、前記波形整形回路の導通時に前記増幅器およ
び時延回路の電流を減少し、この減少した分を前
記サイリスタのゲート電流として供給するために
前記波形整形回路としてスレシヨルド値をこえて
導通した時に前記増幅器の入力信号がなくなつて
も導通状態を保持し続け、さらに前記波形整形回
路の供給電圧が下がつても導通状態を保持し続け
るラツチ回路を用いたことを特徴とする地絡検出
装置。 2 波形整形回路は第1のNPNトランジスタの
ベースを入力としそのコレクタを第1のPNPトラ
ンジスタのベースに接続しそのコレクタを第2の
NPNトランジスタのベースに接続し、第2の
NPNトランジスタのコレクタは前記第1のNPN
トランジスタのコレクタに、そのエミツタは前記
第1のNPNトランジスタのエミツタと共通接続
とし、前記第1のPNPトランジスタのエミツタを
第2のPNPトランジスタのベースに接続し、この
第2のPNPトランジスタのコレクタを出力側とし
た特許請求の範囲第1項記載の地絡検出装置。 3 波形整形回路は第1のNPNトランジスタの
ベースを入力としそのコレクタを第1のPNPトラ
ンジスタのベースに接続し、そのコレクタを第1
のNPNトランジスタのベースに接続し、前記第
1のPNPトランジスタのエミツタを第2のPNPト
ランジスタのベースに接続し、この第2のPNPト
ランジスタのコレクタを出力側とした特許請求の
範囲第1項記載の地絡検出装置。
[Claims] 1. An amplifier that amplifies a signal according to the current to be detected;
A time delay circuit that delays the output, a waveform shaping circuit that receives the output, and a ground fault detection device that causes a current to flow through the gate of a thyristor by the output to turn on the thyristor and operate a circuit breaker. The waveform shaping circuit reduces the current of the amplifier and the time delay circuit when conductive, and supplies this reduced amount as the gate current of the thyristor, so that when conductive exceeds a threshold value, the input signal of the amplifier disappears. A ground fault detection device characterized by using a latch circuit which continues to maintain a conductive state even when the voltage supplied to the waveform shaping circuit decreases. 2 The waveform shaping circuit takes the base of the first NPN transistor as its input, connects its collector to the base of the first PNP transistor, and connects its collector to the base of the second PNP transistor.
Connect to the base of the NPN transistor and connect the second
The collector of the NPN transistor is the first NPN
a collector of the transistor, the emitter of which is commonly connected to the emitter of the first NPN transistor; the emitter of the first PNP transistor is connected to the base of a second PNP transistor; the collector of the second PNP transistor is connected to the collector of the transistor; The earth fault detection device according to claim 1, which is on the output side. 3 The waveform shaping circuit receives the base of the first NPN transistor as input, connects its collector to the base of the first PNP transistor, and connects its collector to the base of the first PNP transistor.
The emitter of the first PNP transistor is connected to the base of a second PNP transistor, and the collector of the second PNP transistor is the output side. Ground fault detection device.
JP6417877A 1977-05-31 1977-05-31 Ground fault detector Granted JPS53147943A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6417877A JPS53147943A (en) 1977-05-31 1977-05-31 Ground fault detector

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6417877A JPS53147943A (en) 1977-05-31 1977-05-31 Ground fault detector

Publications (2)

Publication Number Publication Date
JPS53147943A JPS53147943A (en) 1978-12-23
JPS6156685B2 true JPS6156685B2 (en) 1986-12-03

Family

ID=13250539

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6417877A Granted JPS53147943A (en) 1977-05-31 1977-05-31 Ground fault detector

Country Status (1)

Country Link
JP (1) JPS53147943A (en)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5015686B2 (en) * 2007-07-24 2012-08-29 パナソニック株式会社 Charge monitoring device
JP5015685B2 (en) * 2007-07-24 2012-08-29 パナソニック株式会社 Charge monitoring device
EP2184827B1 (en) * 2007-07-24 2015-12-09 Panasonic Intellectual Property Management Co., Ltd. Charge monitoring device

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4825142A (en) * 1971-08-05 1973-04-02

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4825142A (en) * 1971-08-05 1973-04-02

Also Published As

Publication number Publication date
JPS53147943A (en) 1978-12-23

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