JPS6155732A - Microprocessor - Google Patents

Abstract

PURPOSE:To increase remarkably processing speed by connecting plural logical operation circuits to a common bus and allowing other logical operation circuit to apply data input and output to a bus while one logical operation circuit is in operation to attain processing like pipeline processing. CONSTITUTION:An address A and a data D are supplied alternately to common buses 14, 16, a logical operation circuit 10 fetches the address and a logical operation circuit 20 fetches the data. The time for fetch processing is a 1/2 period when the data D is given to the buses 14, 16 when viewed from the circuit 10 and a period when the address A is given to the 14, 16 when viewed from the circuit 20. After the processing, a data is outputted through a common bus 12, and the circuit 10 fetches an address from the buses 14, 16 and the circuit 20 fetches a data from the buses 14, 16 during this time, and the next processing is started. A control circuit 24 gives the address A and the data D on the buses 14, 16 alternately, allows the circuits 10, 20 to fetch them and output the result. The data required for the operation is extracted from a register file 22 and the result of operation is fed to the buses or the register file.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a microprocessor having a plurality of logic operation circuits connected to a common bus.

[Conventional technology]

Conventional microprocessors typically have only a single logic circuit, or if they have multiple logic circuits, they typically use different buses or segmented buses, so they have a common I can't find anything that connects multiple logic operation circuits to a bus.If you connect multiple logic operation circuits to a common bus, there is a problem such as 1h data overlapping when these logic operation circuits operate simultaneously. .

(Problems to be Solved by the Invention) However, data processing speed cannot be increased with one logic operation circuit, and data processing speed cannot be increased with a single logic operation circuit, and with a system in which multiple logic operation circuits are provided using different buses or segmented buses, the data processing speed cannot be increased. Although the speed increases, the chip area is consumed due to the increase in the number of buses or segment switching circuits, making the chip larger.

By the way, the bus is used for the processing performed by the logical operation circuit, that is, the processing of receiving data or addresses from the bus, calculating them, and outputting the results to the bus. This is an output process, and the bus is not used while the calculation is being performed, and the bus is empty. By allowing other logic operation circuits to use the bus during this vacant period, a plurality of logic operation circuits can operate simultaneously while using the same bus. The present invention focuses on this point, and attempts to reliably enable a plurality of logic operation circuits to operate simultaneously using the same bus.

[Means for solving problems]

The present invention provides a microprocessor in which a data bus, an address bus, and a logic operation circuit are configured on a semiconductor chip, in which a plurality of logic operation circuits are connected to a common bus connected to the data bus and the address bus, and the common bus is connected to a common bus. It is characterized in that it is time-divisionally used so that while one logic operation circuit is performing an operation, the other logic circuit inputs and outputs data using the common bus. Next, the configuration and operation will be explained with reference to embodiments.

〔Example〕

FIG. 1 shows an embodiment of the present invention, where 10.20 is 2+l1
il logic operation circuit, 12, 14.16 is a bus common to these logic operation circuits, 26 is a data bus connected to the common bus, 28 is the same address bus, 22 is a register file (register group) and the common bus 12 .14.16. A control circuit 24 controls the logical operation circuits 10, 20, and the like. The two logic operation circuits 10.20 connect to the register file 22 using three common buses 12.14.16.
You can access any register in it. These logical operation circuits, buses, etc. are constructed on a semiconductor chip.

The operation of the logical operation circuit is to first receive data or addresses from the bus, then perform arithmetic processing, and output the operation results to the bus. In order to operate two logic operation circuits at the same time, each logic operation circuit requires a dedicated bus, but by staggering the operations of the two logic operation circuits, it is possible to If the other logic operation circuit uses the bus, the two logic operation circuits can operate simultaneously without providing a dedicated bus. When viewed from the bus, the two logical operation circuits access the bus alternately, and the bus can operate as if it were a dedicated bus for each logical operation circuit, albeit in a time-sharing manner. A basic timing chart of this circuit is shown in FIG.

In FIG. 2, A indicates an address, D indicates data, I indicates address or data capture, T indicates arithmetic processing, and 0 indicates output of arithmetic results. Addresses A and data D are alternately placed on the common bus 14, 16, and the logic operation circuit 10 takes in the address and the logic operation circuit 20 takes in the data. The period during which data is captured and processed (T) is the period when the data D is on the bus 14.16 from the perspective of the logic operation circuit 10, and the period when the address A is on the bus 14.16 from the perspective of the logic operation circuit 20. be. After processing, it outputs (0), but this output bus is 12, and at this time, the logic operation circuit 10 outputs bus 14.16.
The logical operation circuit 20 receives an address from the bus 14.
．． 16, and the next process begins.

It is the control circuit 24 that alternately places addresses A and data D on the buses 14 and 16, causes the logic operation circuits 10 and 20 to take them in, perform calculations, and output the results. Data necessary for the operation is taken out from the buses 26, 28 or the register file 22, and the results of the operation are sent to these buses or the register file.

The result of the operation may become the input for the next operation, and the logic operation circuit 10 may perform the data operation, and the logic operation circuit 20 may perform the address operation. FIG. 3 shows a time chart in this case. Of course, the logic operation circuits 10 and 20 can also both perform address operations or data operations.

〔Effect of the invention〕

As is clear from the above explanation, according to the present invention, a plurality of logic operation circuits are operated simultaneously using a common bus,
Since pipeline processing can be performed, the processing speed is 1.5 to 2.0 times faster than that of a microprocessor having only a single logic operation circuit, making it extremely effective.

[Brief explanation of the drawing]

FIG. 1 is a process diagram showing an embodiment of the present invention, and FIGS. 2 and 3 are time charts for explaining the operation. In the drawing, 26 is a data bus, 28 is an address bus, 12
．． 14.16 is a common bus, and 10.20 is a logic operation circuit.

Claims (2)

[Claims] (1) A data bus, an address bus, and a logic operation circuit are configured on a semiconductor chip, and a plurality of logic operation circuits are connected to a common bus connected to the data bus and address bus, and the common bus is used in a time-sharing manner. A microprocessor characterized in that, while one logic operation circuit is performing an operation, the other logic circuit inputs and outputs data using the common bus. (2) One of the multiple logic operation circuits is for address operation,
2. The microprocessor according to claim 1, wherein the other is for data calculation.