JPS6155718A - Stabilized electric power supply device - Google Patents
Stabilized electric power supply deviceInfo
- Publication number
- JPS6155718A JPS6155718A JP17746484A JP17746484A JPS6155718A JP S6155718 A JPS6155718 A JP S6155718A JP 17746484 A JP17746484 A JP 17746484A JP 17746484 A JP17746484 A JP 17746484A JP S6155718 A JPS6155718 A JP S6155718A
- Authority
- JP
- Japan
- Prior art keywords
- output
- voltage
- input
- cut
- transistor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
- G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
- G05F1/10—Regulating voltage or current
- G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
- G05F1/56—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices
- G05F1/565—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices sensing a condition of the system or its load in addition to means responsive to deviations in the output of the system, e.g. current, voltage, power factor
- G05F1/569—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices sensing a condition of the system or its load in addition to means responsive to deviations in the output of the system, e.g. current, voltage, power factor for protection
- G05F1/571—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices sensing a condition of the system or its load in addition to means responsive to deviations in the output of the system, e.g. current, voltage, power factor for protection with overvoltage detector
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Electromagnetism (AREA)
- General Physics & Mathematics (AREA)
- Radar, Positioning & Navigation (AREA)
- Automation & Control Theory (AREA)
- Control Of Electrical Variables (AREA)
- Continuous-Control Power Sources That Use Transistors (AREA)
Abstract
Description
【発明の詳細な説明】
（産業上の利用分野）
木兄８Ａは、安定化電源装置に関し、特に入力電圧の遮
断直後における出力電圧の急激な低下を防止した電源装
置に関する。DETAILED DESCRIPTION OF THE INVENTION (Industrial Application Field) Kinoi 8A relates to a stabilized power supply device, and particularly to a power supply device that prevents a sudden drop in output voltage immediately after input voltage is cut off.
（従来の技術）
第２図は、従来形の安定化電源装置の１例としてのシリ
ーズノやスレギュレータを示す。同図の電源装置は、入
力端子と出力端子間に接続された出力制御用トランジス
タＱ１、出力電圧Ｖ。ＵＴと基準電圧ｖｌＥＦを比較し
てトランジスタＱ工のベース電流を制御する誤差増幅話
人□、トランジスタＱ１のエミッタベース間に接続され
た抵抗ＲＢＢ％そしてそれぞれ入力端子とグランド間お
よび出力端子とグランド間に接続された入力容量Ｃ１お
よび出力容量Ｃ３を具備する。(Prior Art) FIG. 2 shows a series regulator and a series regulator as an example of a conventional stabilized power supply device. The power supply device in the figure has an output control transistor Q1 connected between an input terminal and an output terminal, and an output voltage V. Error amplification speaker □ which controls the base current of transistor Q by comparing UT and reference voltage vlEF, resistor RBB% connected between the emitter base of transistor Q1, and between the input terminal and ground and between the output terminal and ground, respectively. The input capacitor C1 and the output capacitor C3 are connected to the input capacitor C1 and the output capacitor C3.
第２図の回路においては、出力電圧Ｖ。ＵＴが低下する
と誤差増幅器Ａ１によってトランジスタＱ１のベース電
圧が引き下げられる。これによシ、該トランジスタＱ、
のエミッタコレクタ間電圧が小さくなるように制御され
て出力電圧Ｖ。ＵＴの低下が防止され、したがって出力
電圧Ｖ。ＵＴが一定の値に保持される。なお、トランジ
スタＱ□のエミッタベース間に接続された抵抗ＲＢＢは
、負荷電流が小さい時にトランジスタＱ□のベース電流
よりＢが極めて小さくなシ誤差増幅器Ａ！の出力電流が
小さくなって該増幅器の動作が不安定になシあるいは制
御不能となることを防止するために挿入されている。In the circuit of FIG. 2, the output voltage V. When UT drops, error amplifier A1 pulls down the base voltage of transistor Q1. Accordingly, the transistor Q,
The output voltage V is controlled so that the emitter-collector voltage is small. A drop in UT and thus the output voltage V is prevented. UT is held at a constant value. Note that the resistor RBB connected between the emitter and base of the transistor Q□ is an error amplifier A! whose B is extremely smaller than the base current of the transistor Q□ when the load current is small. The amplifier is inserted in order to prevent the output current from becoming small and the operation of the amplifier to become unstable or uncontrollable.
ところで、上述の安定化電源装置においては、いったん
入力電圧ｖＸＮが印加されて安定化動作を行なっている
状態で該入力電圧ｖＸＮが急激に遮断された時にも、出
力電圧Ｖ。。７を一定時間保持する必要がある場合があ
る。例えば、安定化電源装置にマイクロコンビエータシ
ステムが接続されておシ、入力電圧ｖｘＮが遮断された
時に該マイクロコンピュータシステムをスタンバイモー
ドにするとかあるいは各部のリセットを行なうためには
、出力電圧が一定時間所定値以上に保持される必要があ
る。例えば、出力電圧Ｖ。ＩｊＴの定格値が５ｖであり
て入力電圧ｖｒｘが遮断された場合に出力電圧ｖｏＴＪ
Ｔが例えば４．５ｖ以上の状態が数１０ミ！Ｊセカンド
持続する必要がある場合等である。By the way, in the above-mentioned stabilized power supply device, even when the input voltage vXN is suddenly cut off while the input voltage vXN is being applied and the stabilizing operation is being performed, the output voltage V remains unchanged. . 7 may need to be held for a certain period of time. For example, if a microcombiator system is connected to a stabilized power supply, the output voltage must be kept constant in order to put the microcomputer system into standby mode or reset each part when the input voltage vxN is cut off. It is necessary to hold the time longer than a predetermined value. For example, the output voltage V. When the rated value of IjT is 5V and the input voltage vrx is cut off, the output voltage voTJ
For example, the state where T is 4.5V or more is several tens of times! This is the case when it is necessary to last for J seconds.
ところが、第２図の従来形の回路においては、入力電圧
ｖＸＮが出力電圧Ｖ。ＵＴより低ぐなるとトランジスタ
Ｑｌがコレクタとエミッタが逆転した形でトランジスタ
動作を行なういわゆる逆トランジスタ効果を生じ誤差増
幅器Ａ、および抵抗ＲＩｌ！ｌによって供給されるベー
ス電流■ＢＢＩＣよって出力容量Ｃ２の電荷が入力側に
放電される。そして、入力電圧ｖｘＮの遮ＩＦ／ｉが入
力回路を解放状態にして行なわれる場合は、出力容量Ｃ
２の電荷が入力容量Ｃｘに転送されるのみであシ急激な
出力電圧の低下は生じない。しかしながら、入力端子に
例えばランプ等が接続されている等入力側が低インピー
ダンスの状態で入力電圧ｖＸＮが遮断される場合は、出
力容量Ｃ２の電荷が急激に入力側に放電され出力電圧Ｖ
。Ｕ、が急速に低下するとかう不都合があった。However, in the conventional circuit shown in FIG. 2, the input voltage vXN is the output voltage V. When the voltage becomes lower than UT, a so-called reverse transistor effect occurs in which the transistor Ql operates as a transistor with its collector and emitter reversed, and the error amplifier A and the resistor RIl! The charge in the output capacitor C2 is discharged to the input side by the base current {circle around (2)} BBIC supplied by l. When the input voltage vxN is blocked by IF/i with the input circuit in the open state, the output capacitance C
Since only two charges are transferred to the input capacitor Cx, no sudden drop in output voltage occurs. However, if the input voltage vXN is cut off when the input side is in a low impedance state, such as when a lamp or the like is connected to the input terminal, the charge of the output capacitor C2 is rapidly discharged to the input side, causing the output voltage V
. There was an inconvenience that U rapidly decreased.
（発明が解決しようとする問題点）
本発明は、前述の従来形における問題点に鑑み、入力電
圧がいかなる状態で遮断された場合にも出力電圧の急激
な低下を生じないようにすることを目的とする。(Problems to be Solved by the Invention) In view of the problems in the conventional type described above, the present invention aims to prevent a sudden drop in the output voltage even when the input voltage is cut off under any condition. purpose.
（問題点を解決するための手段）
上述の問題点を解決するため、本発明によれば、入力端
子と出力端子との間にエミッタ−コレクタ間回路が接続
された出力制御用トランジスタ、出力電圧と基準電圧と
を比較しその比較結果に応じて出力制御用トランジスタ
のベース電流を調節する誤差増幅器、および入力電圧が
゛出力電圧よシも所定値以上低下した場合に出力制御用
トランジスタをカットオフする遮断回路を具備する。こ
とを特徴とする安定化電源装置が提供される。(Means for Solving the Problems) In order to solve the above-mentioned problems, according to the present invention, an output control transistor having an emitter-collector circuit connected between an input terminal and an output terminal, an output voltage and a reference voltage, and adjusts the base current of the output control transistor according to the comparison result, and cuts off the output control transistor when the input voltage and the output voltage decrease by more than a predetermined value. Equipped with a cut-off circuit. A stabilized power supply device is provided.
（作用）
本発明においては、上述のような手段を用いるととによ
シ、入力電圧が出力電圧よシも所定値以上低下した場合
に出力制御用トランジスタがカットオフされるから、入
力電圧の遮断が例え入力側回路が低インピーダンスの状
態で生じても、出力側回路の電荷が入力側回路に放電さ
れることが防止され、出力電圧の急激な低下が抑制され
る。(Function) In the present invention, when the above-mentioned means are used, the output control transistor is cut off when the input voltage is lower than the output voltage by more than a predetermined value. Even if the interruption occurs when the input side circuit is in a low impedance state, the charge in the output side circuit is prevented from being discharged to the input side circuit, and a sudden drop in the output voltage is suppressed.
（実施例） 以下、図面により本発明の詳細な説明する。(Example) Hereinafter, the present invention will be explained in detail with reference to the drawings.
第１図は、本発明の１実施例に係わる安定化電源装置を
示すｄ同図の電源装置は、第２図の電源装置における出
力制御用トランジスタＱｌ誤差増幅器Ａ１％入力容ｆｉ
ｔＣｔ、出力容量Ｃ，の他に、さらに、入力電圧ｖＩＮ
と出力電圧Ｖ。。アを比較する比較器Ａ２、トランジス
タＱｌのベースエミ、り間に接続されたトランジスタＱ
１、トランジスタＱａのベースエミ、り間に接続された
ダイオードＱｚ、等を具備する。トランジスタＱ、およ
びＱ２はカレントミラー回路を構成するものでありて比
較缶入２の出力によって制御される。ま九、ｖＴは入力
端子と比較器Ａ２の反転入力端子との間に所定の電位差
を与えるためのレベルシフト回路でちシ例えばダイオー
ド等によって構成される。FIG. 1 shows a stabilized power supply device according to an embodiment of the present invention. The power supply device in the same figure has an output control transistor Ql error amplifier A1% input capacitance fi in the power supply device of FIG.
In addition to tCt and output capacitance C, the input voltage vIN
and output voltage V. . A comparator A2 that compares A, the transistor Q connected between the base emitter and the
1, a diode Qz connected between the base and emitter of the transistor Qa, and the like. Transistors Q and Q2 constitute a current mirror circuit and are controlled by the output of comparison canister 2. (9) vT is a level shift circuit for providing a predetermined potential difference between the input terminal and the inverting input terminal of the comparator A2, and is constituted by, for example, a diode.
また、Ｖ□２は基準電圧源である。Further, V□2 is a reference voltage source.
第１図の回路においては、入力電圧ｖＸＮが出力電圧Ｖ
。。７よシ高−通常動作時は、比較器Ａ２の出力が低レ
ベルとなっており入力端子からダイオードＱ２を介して
比較器Ａ２の出力に所定の電流が流れる。この所定の電
流と同じ大きさまたは所定の比率を有する電流がトラン
ジスタＱ３のエミッタコレクタ間に流れ第２図における
抵抗ＲＩｔ！ｌと同様に誤差増幅器Ａ１の動作を安定化
している。そして、出力電圧Ｖ。。７が例えば低下する
と誤差増幅器Ａ１の出力電圧が低下しトランジスタＱ１
のベース電流を増加する。これにより、トランジスタＱ
！のエミッタコレクメル］電圧が低下し出力電圧■。。In the circuit of FIG. 1, the input voltage vXN is the output voltage V
. . 7 high - During normal operation, the output of the comparator A2 is at a low level, and a predetermined current flows from the input terminal to the output of the comparator A2 via the diode Q2. A current having the same magnitude as this predetermined current or a predetermined ratio flows between the emitter and collector of transistor Q3 and resistor RIt! in FIG. Similarly to 1, the operation of the error amplifier A1 is stabilized. And the output voltage V. . 7 decreases, the output voltage of the error amplifier A1 decreases, and the transistor Q1
increase the base current. This results in transistor Q
! The emitter collector] voltage decreases and the output voltage ■. .
７の低下が防止され、出力電圧Ｖ。ＵＴが安定化される
。7 is prevented from decreasing, and the output voltage V. UT is stabilized.
ところで、第１図の回路において、入力電圧ｖｘＮが低
下してｖ、Ｎ≦”０ＵＴ−ｖＴどなると比較話人２の出
力が高レベルとなυ、ダイオードＱ２の電流が遮断され
トランジスタＱｓがカットオフされる。また、誤差増幅
器Ａｔは、制御電圧ｖｃＺイ。By the way, in the circuit shown in Fig. 1, when the input voltage vxN decreases such that v,N≦"0UT-vT, the output of the comparison speaker 2 becomes high level υ, the current of the diode Q2 is cut off, and the transistor Qs is cut off. Also, the error amplifier At is turned off at the control voltage vcZi.
すなわち比較器ＡＩの出力が高レベル【なると出力電流
が遮断されるように構成されているから、この場合トラ
ンジスタＱ１のベース電流が遮断され該トランジスタＱ
１がカットオフされる。これによフ、出力容量Ｃ２に蓄
積された電荷が入力回路側に放電されることが防止され
出力電圧Ｖ。ＵＴの急激な低下が防止される。なお、こ
の時出力容量Ｃ２にＳ積゛された電荷は負荷回路に流れ
る電流と、誤差増幅器Ａ１および比較器Ａ！に流れる比
較的微少な回路電流とによって放電されるのみであるか
ら、マイクロコン♂、−タシステム等のシステム動作上
必要とされるオフ動作に必要な時間出力電圧Ｖ。Ｕ、ｒ
を所定値以上に確保することが可能となる。また、比較
器Ａ２の出力によって誤差増幅器Ａ１の出力電流を遮断
する方法としては、誤差増幅器Ａ、の電源回路に挿入し
たスイッチングトランジスタを比較器Ａ２の高レベルの
出力によシ遮断するようにしてもよい。In other words, since the configuration is such that the output current is cut off when the output of the comparator AI is at a high level, in this case, the base current of the transistor Q1 is cut off and the transistor Q
1 is cut off. This prevents the charge accumulated in the output capacitor C2 from being discharged to the input circuit side, thereby reducing the output voltage V. A sudden drop in UT is prevented. Note that the charge S accumulated in the output capacitor C2 at this time is the current flowing to the load circuit, the error amplifier A1, and the comparator A! Since the output voltage V is discharged only by a relatively small amount of circuit current flowing through the circuit, the time output voltage V is required for the OFF operation required for system operation of microcontrollers, computer systems, etc. U, r
It becomes possible to ensure that the value exceeds a predetermined value. Further, as a method of cutting off the output current of the error amplifier A1 by the output of the comparator A2, a switching transistor inserted in the power supply circuit of the error amplifier A is cut off by the high level output of the comparator A2. Good too.
（発明の効果）
このように、本発明によれば、入力電圧が急激に低下し
た場合圧出力制御用トランジスタがカットオフされるか
ら、入力回路が低インピーダンスの状態で入力電圧が遮
断されても出力回路の電荷が入力回路に放電されること
が防止され出力電圧の急激な低下が防止される。したが
って、マイクロコンビーータシステム等の電源遮断時に
おけるリセット動作等を的確に行なうことが可能となる
。(Effects of the Invention) As described above, according to the present invention, the pressure output control transistor is cut off when the input voltage suddenly decreases, so even if the input voltage is cut off while the input circuit is in a low impedance state, the voltage output control transistor is cut off. Charges in the output circuit are prevented from being discharged to the input circuit, and a sudden drop in the output voltage is prevented. Therefore, it is possible to accurately perform a reset operation and the like when the power of the microconbeater system or the like is cut off.
第１図は本発明の１実施例に係わる安定化電源装置を示
すブロック回路図、そして第２図は従来形の安定化電源
袋はを示すブロック回路図である。
Ｑｌ・・・出力制御用トランジスタ、Ａ１ ・・・誤差
増幅器、Ａ２・・・比較器、Ｃ２−・・ダイオード、Ｑ
ｓ ・・・トランジスタ、Ｃ１・・・入力容ｆｆｂ Ｃ
ｚ・・・出力容量、ｖＴ・・・レベルシフト回路、ｖ０
２・・・基準電圧源、ＲＢＢ・・・抵抗。FIG. 1 is a block circuit diagram showing a stabilized power supply device according to an embodiment of the present invention, and FIG. 2 is a block circuit diagram showing a conventional stabilized power supply bag. Ql...Output control transistor, A1...Error amplifier, A2...Comparator, C2-...Diode, Q
s...Transistor, C1...Input capacity ffb C
z...Output capacitance, vT...Level shift circuit, v0
2...Reference voltage source, RBB...Resistance.
Claims (1)
が接続された出力制御用トランジスタ、出力電圧と基準
電圧とを比較しその比較結果に応じて出力制御用トラン
ジスタのベース電流を調節する誤差増幅器、および入力
電圧が出力電圧よりも所定値以上低下した場合に出力制
御用トランジスタをカットオフする遮断回路を具備する
ことを特徴とする安定化電源装置。An output control transistor with an emitter-collector circuit connected between the input terminal and the output terminal, and an error amplifier that compares the output voltage with a reference voltage and adjusts the base current of the output control transistor according to the comparison result. A stabilized power supply device comprising: and a cutoff circuit that cuts off an output control transistor when the input voltage drops by a predetermined value or more than the output voltage.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17746484A JPS6155718A (en) | 1984-08-28 | 1984-08-28 | Stabilized electric power supply device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17746484A JPS6155718A (en) | 1984-08-28 | 1984-08-28 | Stabilized electric power supply device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6155718A true JPS6155718A (en) | 1986-03-20 |
Family
ID=16031385
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP17746484A Pending JPS6155718A (en) | 1984-08-28 | 1984-08-28 | Stabilized electric power supply device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6155718A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0299292A2 (en) * | 1987-07-16 | 1989-01-18 | Sgs-Thomson Microelectronics Gmbh | Longitudinal voltage regulator with reduced output reverse current |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS58169605A (en) * | 1982-03-31 | 1983-10-06 | Toshiba Corp | Dc voltage stabilizing circuit |
| JPS5854713B2 (en) * | 1978-06-30 | 1983-12-06 | 岩崎通信機株式会社 | Hands-free response method in button telephone equipment |
-
1984
- 1984-08-28 JP JP17746484A patent/JPS6155718A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5854713B2 (en) * | 1978-06-30 | 1983-12-06 | 岩崎通信機株式会社 | Hands-free response method in button telephone equipment |
| JPS58169605A (en) * | 1982-03-31 | 1983-10-06 | Toshiba Corp | Dc voltage stabilizing circuit |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0299292A2 (en) * | 1987-07-16 | 1989-01-18 | Sgs-Thomson Microelectronics Gmbh | Longitudinal voltage regulator with reduced output reverse current |
| EP0299292A3 (en) * | 1987-07-16 | 1989-05-10 | Sgs-Thomson Microelectronics Gmbh | Longitudinal voltage regulator with reduced output reverse current |
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