JP3507164B2 - Power supply circuit for electronic equipment - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a power supply circuit for electronic devices, and more particularly to a power supply circuit for supplying power to a load in a device by using a battery as a power supply.

[0002]

2. Description of the Related Art A general example of a conventional device is shown in FIG. In the figure, when the power switch S1 is pressed, the voltage V of the battery 1 is
_B is applied to the source side of the FET 2 and the terminal V _IN of the DC-DC converter 4, for example, and the battery voltage V _R2 divided by the resistors R1 and R2 is applied to the terminal V _TH . The voltage division ratio by the resistors R1 and R2 can be set arbitrarily.

[0003] DC-DC converter 4, if contained in a voltage range in which the battery voltage V _B input is determined, then the terminal LB to form a constant level of the rated power supply voltage Vcc
Send from o. Further, the divided voltage V _R2 applied to the terminal V _TH is compared with the reference voltage by an internal comparator (not shown), and depending on whether it is higher or lower than the reference voltage, for example, a constant voltage of H level or L level is output from the terminal LBo. Send out.

From the DC-DC converter 4 to the power supply voltage Vc
When c is sent, the CPU 5 performs a predetermined operation such as reading data into a memory (not shown). The reset circuit 6 monitors the power supply voltage Vcc while the CPU 5 is operating, and when it becomes lower than a predetermined reference level, for example, issues an H-level reset signal to the CPU 5 to bring it to the initialization state, and
Prevent the malfunction of U.

When a heavy load 3 such as an LCD backlight is turned on (ON), for example, the switch S2 is pressed to press C.
Give a lighting command to PU5. The CPU 5 reads whether the voltage applied to the input port IN from the terminal LBo of the DC-DC converter 4 is H level or L level.

In this case, if it is at the L level, it is determined that the battery voltage is lower than the lower limit value of the determined voltage range,
For example, a warning sound is emitted to notify the device operator,
The output port OUT is set to high impedance so that the base current does not flow to the transistor Q. As a result, the transistor Q is turned off, and therefore the FET 2 is turned off when the potential difference between the source and the gate is zero, the current path from the battery 1 to the heavy load 3 is cut off, and the backlight is not turned on.

When the voltage of the input port IN is at H level, the CPU 5 determines that the battery voltage is within the predetermined voltage range, sets the output port to low impedance and sends the base current to the transistor Q. As a result, the transistor Q is turned on and a collector current flows from the battery 1 through the resistor R3, causing a voltage drop in the resistor R3. Due to this voltage drop, the FET 2 is also turned on, a current path from the battery 1 to the heavy load 3 is formed, and current flows through the heavy load to turn on the backlight.

Now, with reference to FIG. 4 together, a description will be given of a decrease in battery voltage and the like. As shown in FIG. 4 (A), when the battery voltage V _B input to the DC-DC converter 4 is within a predetermined range, the DC-DC converter 4 outputs a constant rated power supply voltage, that is, the system power supply voltage Vcc. It For this rated voltage, the standard value Vccs,
The maximum allowable value Vccmax, the minimum allowable value Vccmin, etc. are defined in the element standards.

It is assumed that the battery voltage V _B during the operation of the device has begun to decrease gradually from the time point t1. Where DC
Output voltage Vcc happen allowable maximum value of the -DC converter 4 and an A was (Vccmax), the battery voltage _{V B} in lowering the voltage Vccmax + Vd obtained by adding the internal absorption voltage Vd of the DC-DC converter 4 to the allowable maximum value For example, when the voltage drops below t2, the output voltage Vcc will be the battery voltage V
CPU5 that decreases in parallel with _B and uses Vcc as the power supply voltage
The operation becomes unstable.

Therefore, a comparator (not shown) is provided in the DC-DC converter 4, for example, Vccmax and Vcc.
A voltage equal to 1 / n of the sum of d is set as the reference voltage Vref,
The voltage V _{R2 obtained} by dividing the battery voltage V _B into 1 / n is the above Vr.
Compare with ef. The comparison output drives the gate of a switching element FET (not shown),
The output on the open drain side of T is C as a battery LOW detection signal from the terminal LBo of the DC-DC converter 4.
It is designed to be sent to PU5.

Now, before time t2, V _R2 ≧ Vref
At that time, the output of the comparator (not shown) is almost zero level, and if the FET (not shown) is in the OFF state, the LBo terminal is pulled up to the level of the power supply voltage Vcc via the resistor R4, and the LBo terminal is pulled up. It is at the H level as shown in FIG.

When V _R2 <Vref is reached after the time t2, the output of the comparator (not shown) rises to near the power supply voltage of the DC-DC converter 4 and becomes H level, and the FET (not shown) is turned ON. As a result, the drain current flows from the power supply voltage Vcc to the FET (not shown) connected to the LBo terminal via the resistor R4, and the voltage at the LBo terminal is reduced due to the voltage drop generated at the resistor R4.
As shown in, the value goes down to near zero and becomes the L level. C
When PU5 reads that the battery LOW detection signal has become L level at the input port IN, it cuts off the base current to the transistor Q as described above, and the battery 1 to the heavy load 3
Turn off the current path to.

[0013] Next, when the output voltage Vcc of the DC-DC converter 4 is, for example, a minimum acceptable value (Vccmin), the coercive voltage Vcc to a constant value until time t3 the battery voltage _{V B} decreases to a value equal to the Vccmin + Vd Sagging, t3
After the time point, the voltage decreases in parallel with the decrease in the battery voltage V _B. In this case, even if it is operating with only a light load, CP
Regular operations such as U5 are no longer guaranteed.

Therefore, a comparator (not shown) is provided in the reset circuit 6 for monitoring the output voltage Vcc of the DC-DC converter 4, for example, the above-mentioned allowable minimum value Vccmin.
Of the reference voltage Vref equal to 1 / n of
The divided voltage of 1 / n of the voltage Vcc applied from the DC converter 4 is compared with the reference voltage Vref. The comparison output is, for example, t3 as shown in FIG.
Since the L level changes to the H level at this time, this signal is given to the CPU 5 to perform system reset (initialization).

[0015]

The above-mentioned conventional device has the advantage that the structure is relatively simple. By the way, DC
-Even if the battery LOW detection voltage sent from the terminal LBo of the DC converter 4 is at the H level, even if the battery is being depleted when the current path to the heavy load 3 is actually turned ON, it is applicable to that type as well. However, depending on the battery LOW detection level, the battery voltage may momentarily drop below the reset voltage level to the CPU 5.

In this case, if the CPU 5 cannot detect the voltage drop of the input port IN and operates the output port OUT to the high impedance in time, the system is reset by the reset signal from the reset circuit 6 and is taken into the memory. However, there is a risk of losing data.

The present invention has been made in consideration of the above circumstances, and an object of the present invention is to provide a power supply circuit capable of rapidly stopping current supply to a heavy load when the battery is exhausted.

[0018]

In order to solve the above problems, according to the present invention, for example, a means for detecting a decrease in battery voltage directly by an analog comparator and shutting off a current supply path to a heavy load by the detection output. Be prepared.

[0019]

According to the above means, the power supply path of the heavy load is turned off faster than the time required for the CPU to read the battery LOW at the input port and operate the output port to high impedance.

[0020]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Referring to FIG. 1 showing an embodiment of the present invention, the parts other than the circuit surrounded by a dotted line frame including a comparator 7 and a capacitor C have the same structure as the conventional device. .

Here, to the + input terminal of the comparator 7, for example, a voltage VB obtained by dividing the battery voltage VB by resistors R5 and R6.
_R6 is added, and the LBo output voltage of the DC-DC converter 4 is applied to its-input terminal. The output voltage of the comparator 7 is applied to the emitter side of the transistor Q, for example.

In this embodiment, the two resistors R
5 and R6 have the same resistance value, that is, R5 = R6, the voltage V _R6 applied to the + input terminal is the battery voltage V _B.
However, the voltage division ratio by the resistors R5 and R6 may be set arbitrarily. A capacitor C, for example, is provided between the signal path from the output terminal LBo of the DC-DC converter 4 to the input port IN of the CPU 5 and the ground.

Next, the operation of each part will be described with reference to FIG. Here, in FIG. 1, the same reference numerals are written in the portions where the signals denoted by the reference numerals in FIG. Note that the time axis in FIG. 2 is enlarged for easy viewing.

In FIG. 2, it is assumed that the battery voltage V _B () is operating with a light load before time t1 and hardly changes. Now press the switch S2 at time t1,
When a current is passed through the heavy load 3 such as a backlight of an LCD, the voltage V _{B of the} battery which has been consumed is rapidly decreased, and accordingly the + input terminal voltage V _R6 () of the comparator 7 is also decreased. Further, the divided voltage V _R2 () applied to the input terminal V _TH of the DC-DC converter 4 also decreases.

Here, the divided voltage V _R2 is, for example, t2.
At a time point, when the voltage falls below the reference voltage Vref () of the comparator (not shown) of the DC-DC converter 4, LBo
The FET (not shown) connected to the terminal is turned on by the output of the comparator as in the conventional example. As a result, the voltage of the capacitor C, which has been charged to a level equal to the power supply voltage Vcc, is discharged through the low ON resistance of the FET connected to the LBo terminal, and the voltage drops rapidly.

This decreasing sending voltage of the LBo terminal ()
Is applied to the minus input terminal of the comparator 7, and the divided voltage VR6 () of the battery is applied to the plus input terminal of the comparator 7.
Is being added as well.

Now, above-the LB added to the input terminal
When the output voltage (o) of o falls below the voltage V _R6 () applied to the + input terminal at the time t3, the output voltage () of the comparator 7 changes from almost zero level to the battery voltage V _B.
Rising toward (), this rising output voltage is applied to the emitter of transistor Q.

As a result, the transistor Q is in the reverse bias state, and if the transistor Q is turned off at time t4 when the voltage applied to the emitter reaches the voltage V, for example, the FET2 has a zero voltage difference between the source and the gate, that is, the same potential. And FET2 is also turned off. Therefore, the power supply path from the battery 1 to the heavy load 3 is cut off, and the current supply is stopped. That is, the backlight is turned off before the system reset signal is sent from the reset circuit 6.

When the current stops flowing to the heavy load 3, the battery voltage V _B () returns toward the level at the time of light load, for example, and two voltages obtained by dividing the battery voltage, that is, the + input of the comparator 7 Terminal voltage V _R6 () and D
The voltage V _R2 () applied to the terminal V _TH of the C-DC converter 4 also rises.

Here, the voltage V _R2 is applied to the reference voltage V _R2 by the comparator (not shown) of the DC-DC converter 4.
It is compared with ref () and, for example, at time t5, the reference voltage V
When it exceeds ref, the output voltage of the comparator (not shown) becomes almost zero level, and the switching FET (not shown) driven by this output is turned off.

Therefore, in the DC-DC converter 4, the current path from the LBo terminal to the ground side via the FET (not shown) is cut off. As a result, the capacitor C is charged from the power supply voltage Vcc via the pull-up resistor R4, and its charging voltage () rises relatively gently according to the time constant determined by the capacitance value of the capacitor C and the value of the resistor R4.

The battery voltage V _B () and the divided voltage V
For example, _R6 () and _VR2 () are restored to the levels before the time t1 at the time t6, for example.
Here, the rising LBo terminal voltage () is, for example, t
When the _divided voltage V _R6 () is exceeded at time point 7, the output voltage () of the comparator 7, which has risen to almost the battery voltage V _B (), decreases toward the zero level, and at time t8, the transistor Q moves forward. There is a risk of being biased and turned on again.

Therefore, in this embodiment, the battery LOW is delayed by delaying the time t7 until the CPU 5 reads from the software that the input port IN is at the LOW level and operates the output port OUT to high impedance.
The value of the capacitor C is set for the resistor R4 so that the period of time becomes longer. The capacitor C can be omitted if the CPU 5 connects the LBo output (), which decreases to the zero level direction at the time t2, to an interrupt (not shown) in the input port IN.

[0034]

As described above, according to the present invention, the battery voltage that decreases when the heavy load is turned on and the battery LOW detection voltage sent from the LBo terminal are added to the analog comparator 7, and the heavy load is generated by the comparison output. System reset can be avoided by rapidly shutting off the current supply path to the.

Further, since the battery LOW time can be maintained for a long time, the CPU can easily operate the output port at high impedance. Furthermore, the history of the battery voltage dropping until it falls below the battery LOW detection level momentarily
Can be left as data.

[Brief description of drawings]

FIG. 1 is a block diagram showing an electrical configuration of a power supply circuit to which the present invention is applied.

FIG. 2 is a level diagram for explaining operation timing of a power supply circuit to which the present invention is applied.

FIG. 3 is a block diagram showing an electrical configuration of a conventional device.

FIG. 4 is a level diagram for explaining operation timing of a conventional device.

[Explanation of symbols]

1 battery power 2 FET 3 double load 4 DC-DC converter 5 CPU 7 comparator C capacitor _{V B} cell power supply voltage Vcc system power supply voltage _{V R2} divided voltage _{V R6} division voltage

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Claims (2)

(57) [Claims] 1. When power is supplied from a battery power source to a heavy load through a semiconductor switching element and the voltage of the battery power source falls below a predetermined level, the switching element is turned off.
In a power supply circuit of an electronic device that is driven to F to stop power supply, a system power supply voltage of a certain level is formed from the battery power supply, and a battery low (LOW) signal is detected by detecting a voltage drop of the battery power supply. And a CPU that receives the battery low signal to control ON / OFF of the drive circuit of the switching element. The drive circuit is turned on / off by the base current given from the CPU. A transistor for simultaneously turning on and off the switching element and a comparator for comparing the magnitudes of the two signals by respectively inputting the battery low signal and the divided voltage of the battery power source. When the battery low signal falls below the divided voltage during the ON operation of the A power supply for electronic devices characterized in that an inverted output of H level generated from the battery generator is applied to the above transistor in a reverse bias state, and the same transistor is turned off so as to cut off the current from the battery power supply to the heavy load. Supply circuit. 2. A power supply for electronic devices according to claim 1, wherein a capacitor for maintaining the battery low state for a desired period is provided between the battery low signal path from the DC-DC converter to the CPU and the ground. Supply circuit.