JPS6155300B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a control method for preventing a so-called bus fight, which is a phenomenon in which both devices output simultaneously when information is transferred between devices using a bidirectional bus.

For example, in an LSI computer system, most of the functions such as a processing unit are included on a single chip, but due to the limited number of I/O pins, a bidirectional bus is used to exchange information with external circuits. It is done using Conventionally, as shown in Figure 1, LSI1
and an external circuit are connected by a bidirectional bus 2, and at both ends of the bus 2 there is a driver circuit made up of tristate gates 3 and 4, and a receiver circuit 5,
6 is connected, and a control signal E indicating which of gates 3 and 4 to enable is directly applied to gate 4 of the external circuit via control line 7 from LSI 1.

The control signal E must have the function of enabling only one of the gates 3 and 4 to prevent a bus fight and prevent destruction of the device.
However, in reality, it takes a certain amount of time for the signal to propagate from point a to point b, and bus fights may occur during that time. For example, when transitioning from a state where gate 4 is enabled to a state where gate 3 is enabled, both gates will be enabled during the above propagation time, and if the output values of the two gates are different at that time, the gate element will be It may be destroyed. In the past, no special measures were taken to deal with such cases, but as the degree of integration of LSIs increases,
As each element becomes smaller, the risk of breakage increases, and it has become desirable to reliably prevent bathphites.

The present invention aims to solve these conventional problems and will be explained below with reference to FIG. 2.

FIG. 2 is a block diagram of an embodiment of the present invention.
In the figure, the same symbols as in FIG. 1 indicate the same things, 8 and 9 are delay means with delay times T ₁ and T ₂ respectively, and 10 is an AND gate. In the present invention, the control signal E generated within the LSI 1 is first applied to an external circuit via a line 11. In the external circuit, the received signal E is applied to the tristate gate 4 via the first delay means 8, and is applied to the LSI 1 via the second delay means 9 and the line 12.
send it back to In the LSI 1, the returned signal and the signal generated by itself are ANDed by a gate 10, and the output is given to its own tristate gate 3. That is, tristate gate 3 is a
-d-f-g-b-c route and the tristate gate 4 is provided with control signal E on the ad-e route. T ₁ and T ₂ may be adjusted so that the propagation times on both routes are equal.

In Fig. 1, it is possible to insert a delay means corresponding to the propagation time between a and b before point a in the figure, but this external propagation time depends on the wiring length of the printed board and the other device. Since the delay time is not constant depending on the structure of the device, it is preferable to provide a delay means suitable for the circuit in the other party's circuit and control the own device based on the signal fed back from the delay means as in the present invention.

Further, in FIG. 2, the above T ₂ may be zero. For example, if there is some originally necessary circuit between d and e of the external circuit, and _T1 cannot be lower than a certain value, and that value is f-g-b-
If it is larger than the propagation time between c, the difference is
This will be canceled out at T ₂ , but otherwise, if T ₁ is set so that the d-e propagation time is equal to the f-g-b-c propagation time, T ₂ =0 may be sufficient.

As described above, in the present invention, the device that emits the control signal E controls the tristate gate of its own device on the condition of feedback from the other device, and the other device transmits the received control signal for a certain period of time T ₁ By controlling the tristate gate of its own device with a delay and returning the control signal with a delay of time _T2 , it is possible to prevent both tristate gates from being enabled at the same time.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a conventional example of a bidirectional bus control system, and FIG. 2 is a block diagram showing an embodiment of the present invention. In the figure, 1 is an LSI, 2 is a bidirectional bus, 3 and 4 are tristate gates, E is a control signal, 8 and 9 are delay means, and 10 is an AND gate.

Claims (1)

[Claims] 1 each having a tri-state gate output 2
In the control method of the bidirectional bus that connects devices,
The first device includes means for generating a tri-state gate control signal and the AND means; the second device includes first and second delay means; The second device sends the control signal, and in the second device, the received control signal is given to the tristate gate via the first delay means for control, and the received control signal is given to the tristate gate via the second delay means. and returns it to the first device, and in the first device, the AND output of the control signal and the control signal sent back from the second device is given to a tristate gate for control. A bidirectional bus control method.