JPS6154939U - - Google Patents

Info

Publication number
JPS6154939U
JPS6154939U JP14110884U JP14110884U JPS6154939U JP S6154939 U JPS6154939 U JP S6154939U JP 14110884 U JP14110884 U JP 14110884U JP 14110884 U JP14110884 U JP 14110884U JP S6154939 U JPS6154939 U JP S6154939U
Authority
JP
Japan
Prior art keywords
switch
circuit
output control
state determination
oscillation output
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP14110884U
Other languages
Japanese (ja)
Other versions
JPH0117054Y2 (en
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP1984141108U priority Critical patent/JPH0117054Y2/ja
Publication of JPS6154939U publication Critical patent/JPS6154939U/ja
Application granted granted Critical
Publication of JPH0117054Y2 publication Critical patent/JPH0117054Y2/ja
Expired legal-status Critical Current

Links

Landscapes

  • Switch Cases, Indication, And Locking (AREA)
  • Electronic Switches (AREA)

Description

【図面の簡単な説明】[Brief explanation of drawings]

第１図は本考案の一実施例を示す構成図、第２
図はその動作説明図、第３図および第４図は本考
案の他の実施例を示す構成図、第５図は従来の各
種スイツチのオン、オフ表示法の説明図である。 図中、ＳＷａ〜ＳＷｄは機能スイツチ、Ａ〜Ｄ
は各種回路、ＯＳＣ１，ＯＳＣ２は発振器、ＭＩ
Ｘはミキサ、ＳＰはスピーカ、ＦＦ，ＣＰＵはス
イツチ状態判別機能を有するフリツプフロツプお
よびプロセツサ、Ｔ１，Ｔ２およびＡＳ１，ＡＳ
２は発振出力制御機能を有するトランジスタおよ
びアナログスイツチである。 Figure 1 is a configuration diagram showing one embodiment of the present invention;
3 and 4 are block diagrams showing other embodiments of the present invention, and FIG. 5 is a diagram illustrating the conventional on/off display method for various switches. In the figure, SWa to SWd are function switches, A to D
are various circuits, OSC 1 and OSC 2 are oscillators, MI
X is a mixer, SP is a speaker, FF, CPU is a flip-flop and processor with a switch state determination function, T 1 , T 2 and AS 1 , AS
2 is a transistor and an analog switch having an oscillation output control function.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 所定の機能を有する回路をオンおよびオフさせ
るスイツチの操作時に、オンとオフとで異なる可
聴音を一時的に発生するための発振器、スイツチ
状態判別回路および発振出力制御回路を備えてな
ることを特徴とするスイツチのオン、オフ報知装
置。 It is characterized by being equipped with an oscillator, a switch state determination circuit, and an oscillation output control circuit for temporarily generating different audible sounds depending on on and off when operating a switch that turns on and off a circuit having a predetermined function. Switch on/off notification device.
JP1984141108U 1984-09-18 1984-09-18 Expired JPH0117054Y2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1984141108U JPH0117054Y2 (en) 1984-09-18 1984-09-18

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1984141108U JPH0117054Y2 (en) 1984-09-18 1984-09-18

Publications (2)

Publication Number Publication Date
JPS6154939U true JPS6154939U (en) 1986-04-12
JPH0117054Y2 JPH0117054Y2 (en) 1989-05-18

Family

ID=30699453

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1984141108U Expired JPH0117054Y2 (en) 1984-09-18 1984-09-18

Country Status (1)

Country Link
JP (1) JPH0117054Y2 (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS54137140U (en) * 1978-03-17 1979-09-22

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS54137140U (en) * 1978-03-17 1979-09-22

Also Published As

Publication number Publication date
JPH0117054Y2 (en) 1989-05-18

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