JPS6154298B2 - - Google Patents

Description

[Detailed description of the invention] The present invention relates to a device for broadcast communication.

2. Description of the Related Art There have conventionally been devices for broadcast communication in which signals such as facsimile signals and data signals are simultaneously broadcast from one transmitting device to a plurality of receiving devices.
FIG. 1 shows a conventional example of such a device for facsimile transmission. A coded facsimile signal is sent from a transmitter 11 of the facsimile transmitter to a modulator 12 . Modulation section 1
2 converts this signal to 9600bps (bits per second) or
Modulate for 4800bps code transmission. The modulated signal is delivered to a plurality of line interfaces 14A, 14B... by the branch amplifier 13, and is sent to the receiving device 16A, 16 from each line interface 14A, 14B... through each line 15A, 15B...
The same signal is simultaneously transmitted to B...

On the other hand, response signals are transmitted from the receiving devices 16A, 16B, . . . to the respective line interfaces 14A, 14B, . . . through the respective lines 15A, 15B, .
This response signal is transmitted to the response signal demodulators 17A, 17B...
The received signal is demodulated and sent to the response detection units 18A, 18b, . . . . The response detection units 18A, 18B, . . . decode the type of response signal and send the results to the response editing unit 19. The response editing section 19 edits the results sent from each receiving device and sends them to the transmission control section 10.
Transmission control section 10 performs necessary control on transmitting section 11 and modulating section 12 in response to this.

In such a conventional device, each line 15A, 1
It was necessary to send signals to 5B... at the same code transmission rate all at once. In other words, on the transmission line
If there were two types, 9600bps and 4800bps, it would be necessary to send signals at a slow transmission rate of 4800bps to each line.

Furthermore, in such a device, even if a code error occurs in the transmission of signals sent to each line, it is difficult to correct it. In other words, even with conventional equipment,
By adding a check bit such as a CRC code to the signal to be transmitted, each receiving device could detect whether there were any errors in the signal transmission, and if there were fewer errors, it would be possible to correct them. However, in systems where this cannot fully correct the error, the system must rely on the error retransmission correction method, but if each receiver tries to retransmit the signal after the signal with the code error, the signal with the code error will be retransmitted. Since the location is not constant for each line, the transmitting device should have buffer memory equivalent to one screen for each line, or
It was necessary to provide a separate transmitting section for each line, which caused an economical problem.

The present invention has been made in view of the above-mentioned circumstances, and allows the transmitting device to transmit signals in accordance with the code transmission speed of each line, and also allows the transmitting device to It is an object of the present invention to provide a device for broadcast communication that can easily correct code errors by re-sending signals from the base station.

In the present invention, the transmitter is provided with one buffer memory for storing signals equivalent to, for example, one screen, and as many transmission control units as the number of lines provided corresponding to each line. The signal to be transmitted is then stored in the buffer memory, and the signal is delivered in a time-sharing manner to each transmission control unit that controls transmission, thereby enabling transmission according to the code transmission speed of each line. .

Furthermore, each receiving device is equipped with a function of detecting code errors in the transmitted signal and sending out a retransmission request signal requesting retransmission of the signal containing the code error. When a signal retransmission is requested from the receiving device, the buffer memory transfers the requested signal from each corresponding receiving device to each line control unit in the transmitting device in a time-sharing manner. Thus, the above objectives have been achieved.

The present invention will be explained in detail with reference to Examples below.

FIG. 2 represents the apparatus of the invention.
In the present invention, a buffer memory (hereinafter simply referred to as memory) 21 stores image signals for one or more screens in the transmitter.
and a memory control unit 22 that controls this memory 21.
It has A transmission control unit 23 controls transmission, and a modulation unit 2 modulates the image signal for code transmission.
4. Interface section 2 for connection with the line
5 for each line.

In response to a request from the transmission control section 23, the memory 21 divides the image signal into blocks and sends them to each transmission control section 23 in a time-division manner. Details of this time-division signal transfer will be described later.

Each transmission control section 23 that has received the signal sequentially sends out the signal of each block obtained from the memory 21 to the modulation section 24 according to, for example, an HDLC (high level data ring) frame configuration.

Figure 3a shows the frame structure of this HDLC.Flag sequence F, which consists of 8 bits, is followed by address field A, which also consists of 8 bits, and then address field A, which also consists of 8 bits. A control field C follows.

When the frame is the "information transfer frame" shown in FIG. N(S) is attached. The 5th bit is the poll/final bit P/F, and the 6th to 8th bits are the received frame sequence number N.
(R). The control field C is followed by an information field I having an integral multiple of 8 bits.
Next follows a frame check sequence FCS consisting of 16 bits. A CRC code is used for the frame check sequence FCS. At the end of the frame configuration, the same flag sequence F consisting of 8 bits as at the beginning is inserted.

Now, the signal based on this HDLC frame structure is sent to the modulator 24 at 4800bps or 480bps depending on each transmission path.
Modulated for 9600bps code transmission. The modulated signal is then sent out to the line 26 through each line interface 25 and reaches each receiving device 27.

Each receiving device 27 has a configuration as shown in FIG. That is, the signal sent through the line 26 is adjusted by the line interface 31, and then
The demodulation section 32 demodulates the signal. The demodulated signal is sent to the transmission control section 33, where errors in the transmitted signal for each block are detected using the CRC method.
If an error is discovered and you request retransmission,
A retransmission request signal is sent to the backward coder 34.

In this case, the configuration of the control frame C in HDLC is as shown in FIG. The 5th bit is the poll/final bit P/F, and the 6th to 8th bits are the received frame sequence number N(R).

This retransmission request signal is encoded by a backward coder 34, modulated by a backward modulator 35, and then passed through a line interface 31 to the line 2.
6 and transmitted to the transmitter.

The transmitter adjusts the retransmission request signal sent from the receiver in which a code error has been detected using the line interface 25 connected to the corresponding line, and then demodulates it at the backward demodulator 28. Then, it is decoded by the backward decoder 29,
As a result, the number of the block to be retransmitted, ie, the number based on the transmission frame sequence number N(R), is instructed to the transmission control section 23. Transmission control section 23
In response, the memory controller 22 is requested to read out the image signals from the corresponding block onward.

FIG. 5 shows the relationship between the above-mentioned requests from each transmission control section 23 and the image signal transferred from the memory 21 to the transmission control section 23. During the first time interval _t1 , the memory controller 22 detects the number of the block requesting transfer from the first line or the corresponding address in the memory 21. Then, during the next second time interval _t2 , the n-bit signal is transferred from the memory 21 to the first transmission control section 23. Thereafter, the first time interval t ₁ and the second time interval t ₂ are allocated alternately, and requests from the transmission control units of the second line, third line, etc. are detected, respectively, and the requests are sent to these transmission control units. Necessary image signals are transferred.

In this way, requests from each transmission control section 23 are processed in a time-division manner, so that each transmission control section 23 can request transfer of signals of different blocks. In other words, it is possible to respond to retransmission requests randomly generated on each line during broadcasting.

By the way, by adopting such a time-sharing method,
The number N of controllable lines can be determined by the following formula.

N=T ₁ /t ₁ +t ₂ where T ₁ is the time to transmit n bits on each line at the modem's code transmission rate m bits/second, which is equal to n/m (seconds).

Now, the image signal thus transferred from the memory 21 is retransmitted to the receiving device 27 through the line 26. Then, the transmission control unit 33 in the receiving device judges the reception result, and if there is a code error, sends out a retransmission request signal again. In this case, the image signal will be retransmitted from the transmitting device again.

On the other hand, if there is no code error in the image signal sent through the line 26 from the beginning, or if a correct image signal is sent by retransmission, the transmission control unit 33 stores the image signal of that block in the buffer memory. 36. The buffer memory 36 stores a certain amount of image signals and then sends them to the facsimile receiver to reproduce the image.

When the facsimile receiving section 37 of each line finishes reproducing one screen of images through this process, a response signal is transmitted to the transmitting device, and based on the response signal of each line, the transmission control section 22 performs necessary controls such as stopping the operation of the This is similar to the operation of the conventional transmission control section 10 shown in FIG.
Note that when the transmitter continuously transmits signals for a plurality of screens, the memory 21 stores information for the next one screen.

FIG. 6 shows in more detail the case where data is time-divisionally transferred from the memory 21 shown in FIG. 2 to each transmission control section 23. First, in order to store the signal from the facsimile transmitter in the memory 21 via the I/O port 38, the image signal obtained from the facsimile transmitter is transferred through the I/O port 38 and the data buses _D7 to _D0 to 8 bits. 44 CPUs
Incorporate into. In CPU41, address bus A ₁₅ ~
A ₈ and the upper address via the address decoder 39, and the data bus D ₇ to _{D 0} and the second
The lower address is specified to the memory 21 via the address latch ₄₀₂ , and the CPU 41 sends the captured image signal to the memory 21 via the data bus and stores it at the specified address in the memory 21. By repeating this operation, information for one screen is stored in the memory 21.

Now, in this way, the signals stored in the memory 21 are transferred to each transmission control unit 23, but in this example, DMA (Direct Memory
Access) controller is used to transfer signals from memory without going through the CPU.

That is, for example, from each transmission control unit of the first and second lines, the respective I/O ports 4
When the transfer request signal reaches the interrupt controller 43 via the signals 1 and 42, the interrupt controller 43
cyclically controls transfer request signals from each line and interrupts the CPU 44. CPU4
4 reads the frame sequence number to be transferred from the transfer request signal sent from the first I/O port 41, for example, according to the interrupt processing program. The CPU 44 then instructs the DMA 45 about the address to be transferred via the data buses _D7 to _D0 . After this, the first I/O port 4
1 sends the DRQ ₁ signal to the DMA controller 45,
Requests image signal transfer by the DMA controller 45. In response, the DMA controller 45
The HRQ signal is sent to the CPU 44 to request the CPU 44 to enter a HOLD state. The CPU 44 outputs the HLDA signal in response to this hold request. The DMA controller 45 detects this HLDA signal and uses the DACK ₁ signal to notify the first I/O port 41 that data transfer preparation is complete. In this state, the CPU, bus driver
The second address latch ₄₀₂ , which stores the lower address, becomes floating (inactive state).
The upper address is output from the data bus D ₇ -D ₀ of the DMA controller 45 via the first address latch ₄₀₁ and the address decoder 39, and the lower address is output from the address bus A ₇ -A ₀ , and the instruction is sent to the memory 21. be done. The memory 21 reads the first I/O port 41 according to the specified address.
Sequentially transfer data of a fixed size to

When the image signal transfer for the first line is completed in this way, direct memory access (DMA) is performed.
is temporarily terminated, and the operation corresponding to the transfer request of the second line begins. Thereafter, the N lines are cyclically controlled in the same manner. Here, the number of bits n of one block transmitted at one time is 256 bytes (2048 bits), and the code transmission speed of the modem (modem) is
If the speed is 9600 bps, the time T ₁ will be approximately 200 msec.
With the development of peripheral elements for microcomputers,
Since the sum of the aforementioned time intervals (t ₁ +t ₂ ) can be operated on the order of 100μ, it can be seen that the number N of lines becomes very large and it is possible to control a very large number of lines at the same time.

As described above, according to the present invention, broadcast communication can be performed on many lines, and code errors can be easily corrected.

[Brief explanation of the drawing]

FIG. 1 is a block diagram for explaining a conventional broadcast communication device, and FIG. 2 is a block diagram mainly for explaining the main parts of the transmitting side device of the broadcast communication device of the present invention. Figure 3a is
FIG. 4 is a block diagram illustrating the main parts of the receiving device shown in FIG. 2. FIG. 5 is a diagram explaining the temporal relationship between transfer requests from each line and data transfer to each line in the present invention, and FIG.
FIG. 2 is a block diagram illustrating the transfer of signals to each line by DMA. 21...Memory, 22...Memory control unit, 2
3, 33...transmission control unit, 26...line, 27...
...Receiving device.

Claims (1)

[Claims] 1 Through multiple lines from one transmitting device,
In broadcast communication in which signals with the same content are transmitted to each receiving device connected to each of these lines, a memory of a certain size is provided in the transmitting device to store the signals to be transmitted, while a memory of a certain size is provided in each of the receiving devices. A transmission control unit is provided that sends out a retransmission request signal requesting retransmission of a signal in which a code error exists, and the transmitting device transmits a corresponding signal from a memory in the transmitting device in response to the retransmission request signal from each receiving device. A device for broadcast communication characterized by time-divisionally delivering information to a corresponding transmission control unit within the system.