JPS6153891B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a logarithmic amplifier circuit, and particularly to a logarithmic amplifier circuit using a transistor circuit that can operate an NPN transistor equivalently as a PNP transistor.

[Technical background of the invention and its problems]

Generally, in an integrated circuit device in which a desired transistor circuit is constructed by combining NPN transistors and PNP transistors, the NPN transistor is composed of a vertical transistor as shown in Fig. 1b, and the PNP transistor is composed of a vertical transistor as shown in Fig. 1a. Consists of lateral transistors. This vertical NPN transistor can be configured so that the distance between the emitter 14 and the collector 16, that is, the width of the base 15, is considerably narrow, approximately 1.5 μm, by controlling the depth of diffusion, and as a result, the cutoff frequency of the NPN transistor is 200 μm. The current amplification factor h _FE of this transistor is about 100 because the current amplification factor h FE of this transistor is as high as 300 MHz and the ratio of carriers injected into the base 15 into the collector 16 becomes large. On the other hand, in a lateral PNP transistor, the spacing between the emitter 11 and the collector 13, that is, the width of the base 12, is limited by the mask accuracy of the mask used when manufacturing integrated circuit devices, so it exhibits a large value of about 10 μm. . For this reason, the cutoff frequency of the lateral PNP transistor is as low as several MHz, and the proportion of carriers injected into the base reaching the collector is small, and the current amplification factor h _FE of this lateral PNP transistor is 1.
Only low values of about 10 to 10 will be shown.

As you can see, the performance of lateral PNP transistors is very inferior to that of vertical NPN transistors, and when such NPN transistors are used together to configure a logarithmic amplifier circuit, it is not possible to obtain good input/output characteristics. There was a problem. Furthermore, the above-mentioned drawbacks of the lateral PNP transistors have been a hindrance, making it impossible to realize a high-performance integrated circuit device.

[Object of the invention] The present invention has been made in view of the above points, and
The purpose of the present invention is to provide a transistor circuit that takes advantage of the performance of NPN transistors and enables the same operation as PNP transistors, and to provide a logarithmic circuit with excellent characteristics.

[Summary of the invention]

The present invention constitutes a logarithmic amplifier circuit in which a transistor circuit formed by connecting a current inversion amplifier circuit to the collector of an NPN transistor is equivalently used as a PNP transistor.

The present invention will be described in detail below with reference to the drawings.
FIG. 2 shows the basic configuration of a transistor circuit used in the present invention, which is composed of a PNP transistor 21 and a current inverting amplifier circuit 22 connected to the collector of this transistor 21 to invert the collector current.

FIG. 3a shows a specific configuration of a current inverting amplifier circuit connected to a common base NPN transistor.
In the figure, a common base NPN transistor 21
The collector of is connected to the current inversion amplifier circuit 22. This current inversion amplifier circuit 22 includes an operational amplifier 31 having an inverting input terminal 32 connected to the collector of an NPN transistor 21, a resistor 35 connected between the inverting input terminal 32 and the output terminal 33 of the operational amplifier 31, and a non-inverting input. Terminal 34 and output terminal 3
and a resistor 36 connected between the two.

Next, the transistor circuit shown in Fig. 3a is converted to the emitter-grounded PNP transistor 3 shown in Fig. 3b.
Let's compare it with 8. Assuming that the voltage and current directions are determined as shown in the figure, the PNP transistor 38
The collector current of Iout′ is NPN transistor 21
Assuming that the collector current of is Iin and the base-emitter voltages of both transistors are represented by V _BEP and V _BEN , respectively, the following equation holds true.

Iout'=Is[expq/kT(-V _BEP )-1]…………(1
) Iin=-Is[expq/kTV _BEN -1]…………(2) Here, if V _BEN =-V _BEP , Iin is
It is simply the opposite phase of Iout′. Therefore, if this Iin is inverted by the current inverting amplifier circuit 22, the inverted current
Iout becomes Iout=Iout', and the transistor circuit of FIG. 3a operates equivalently as a PNP transistor. Therefore, in the current inverting amplifier circuit 22 shown in FIG. 22 always operates as a negative feedback amplifier. Therefore, only a slight error voltage exists between the non-inverting input terminal 34 and the inverting input terminal 32. This means that if the resistors 35 and 36 are equal, then substantially the same current will always flow through both resistors 35 and 36, so actually Iout=Iin=
It can be Iout′. In this case, if the gain of the current inverting amplifier circuit 22 is completely 1, the common base gain of the NPN transistor 21 is close to 1, so the gain of the entire circuit shown in FIG. 3a is 1. Furthermore, if the current gain of the current inverting amplifier circuit is selected to be 100, the circuit of FIG. 3a operates equivalently to a common emitter PNP transistor with a current amplification factor h _FE =100.

It is also possible to realize a similar transistor circuit by using a grounded emitter NPN transistor 41 as shown in FIG. 4a. In this case, by similarly inverting the collector current with the current inverting amplifier circuit 42, it is possible to operate exactly the same as the base-grounded PNP transistor 43 shown in FIG. 4B.

Further, as described above, the current inverting amplifier 22 supplies the current iin to the base of one transistor 51 of the differential transistor pair 51, 52 having a current mirror configuration as shown in FIG. Output current from base of 52
iout, and the transistor 51 is connected to the base of these transistors 51 and 52.
It can be concretely configured by feeding back the collector outputs of the transistor 53, the resistor 54, the transistor 55, and the resistor 56, respectively.

Equivalent operation can also be guaranteed by using a circuit as shown in FIG. 6 as the current inversion amplifier circuit 22. This circuit differs from the circuit shown in FIG. 3 in that the output of the operational amplifier 61 is not fed back to the non-inverting input terminal, and the output current
iout is from the output terminal of the operational amplifier 61 to the resistor 62
The current is taken out from the current output terminal 63 through the current. Note that the non-inverting input terminal is grounded.
However, in the case of such a circuit, the voltage at the current output terminal must be clamped. For this purpose, an NPN grounded to this current inversion circuit 22
The emitter of transistor 64 is led to a negative potential.

In the above inspection, the base 6 of the transistor 64
5 causes collector current iin to draw current from the inverting input terminal of operational amplifier 61, and this current flows through resistor 66. Therefore, the voltage v ₀ at the output terminal 67 of the operational amplifier 61 is v ₀
=iin×R. If the voltage at the current output terminal 63 is zero potential, the current flowing through the resistor 62 becomes v ₀ /R=iin·R/R=iin, which is equal to the input current. Therefore, it is possible to perform exactly the same operation with such a circuit, and in particular, this circuit has the advantage of being relatively stable because no positive feedback is applied to the non-inverting input terminal as shown in FIG.

FIGS. 7 and 8 respectively show an embodiment of a logarithmic amplifier circuit of the present invention, which uses the above-described transistor circuits to obtain an output logarithmic with the positive and negative polarities of the input voltage.

First, to explain Fig. 7, the input voltage vin
The output signal of the operational amplifier 73 is fed back from the input terminal 71 through the DC cut capacitor C and the resistor Rin 72 to the inverting input terminal via the NPN transistor 74 whose base is grounded. Similarly, the current is fed back to the inverting input terminal of the operational amplifier 73 via a transistor circuit constituted by a current inverting amplifier circuit 75 and a current inverting amplifier circuit 76. The non-inverting input terminal of the operational amplifier 73 is grounded via the bias power supply V, and a diode 77 is connected between the base and emitter of the NPN transistor 75 in the forward direction. The two NPN transistors 74 and 75 have exactly the same characteristics, and their base-emitter voltage V _BE and collector current Ic have the following relationship.

Ic=Is(expqv _BE / _kT −1) ……(1) Therefore, the voltage vin applied to the input terminal 71
A current proportional to
This current flows into the inverting input terminal of No. 3, and this current, the collector current of the transistor 74 in the output feedback loop of the operational amplifier 73, and the current whose direction of the collector current of the transistor 75 is reversed by the current inverting amplifier circuit 76 cancel each other out. Therefore, the input current iin and the collector current are equal.

Therefore, the above equation (1) is Ic=vin/Rin=Ic(expqv _BE /kT-1)......(
2), and if we take the logarithm of both, omitting the second term on the right side, lnvin = {ln (Rin・Is)・q/kT}v _BE …………(3), so the output voltage is equal to the input voltage vin is the logarithm of

In such a logarithmic amplifier circuit, the transistor circuit section of the present invention that operates as an equivalent PNP transistor consisting of the NPN transistor 75 and the current inversion amplifier circuit 76 has conventionally been a simple PNP transistor with a common base as shown in FIG. 4b. Since the other NPN transistor 74
However, if the transistor circuit of the present invention is used, the transistors 74, 7
5 are all NPN transistors, and when realized with Ic, completely equal v _BE -Ic characteristics can be obtained, so an extremely symmetrical output voltage can be obtained. In addition, in FIG. 7, the diode 77
is inserted to make the current gain of the NPN transistor and the equivalent PNP transistor the same,
It has nothing to do with essential operations.

FIG. 8 shows a current inverting amplifier circuit 76 with a grounded base.
It is inserted on the NPN transistor 74 side, and its operation is similar to that of FIG. 7. However, in this circuit, the current inverting amplifier circuit 76, which has poor frequency characteristics, is connected to the common-base transistor 74, which has better frequency characteristics than the common-emitter transistor 75, so that the frequency characteristics can be balanced. This circuit has better frequency characteristics than the circuit.

〔Effect of the invention〕

As explained above, the present invention provides a logarithmic amplifier circuit configured using a transistor circuit that can equivalently operate as a PNP transistor by inverting the collector current of the NPN transistor. According to such a logarithmic amplifier circuit, for the positive and negative polarities of the input voltage,
It is possible to obtain an output voltage with extremely good symmetry.

[Brief explanation of the drawing]

Figure 1 shows a lateral PNP transistor,
A cross-sectional view showing the configuration of an NPN transistor, FIG. 2 is a diagram showing the basic configuration of a transistor circuit used in the present invention, FIG. 3 is a diagram showing a specific configuration of a current inversion amplifier circuit, and FIG. 4 is a transistor circuit. FIG. 5 is a diagram showing a more specific configuration of the current reversing circuit, FIG. 6 is a diagram showing still another embodiment of the current reversing circuit, FIGS. 7 and 8 1A and 1B are diagrams each showing an embodiment of a logarithmic amplifier circuit of the present invention. 21, 41, 74, 75... NPN transistor, 22, 76... current inversion amplifier circuit.

Claims (1)

[Claims] 1 Provided between an amplifier to which an input current proportional to the input voltage is supplied to the input terminal and the input/output terminal of this amplifier, the amplifier responds to either the positive or negative polarity of the input current and supplies a current with the opposite polarity to the input current. A first feedback circuit including an NPN transistor that feeds back to the input terminal of the amplifier and the input/output terminal of the amplifier is provided to respond to the other polarity of the input current and supply a current with the opposite polarity to the input current to the amplifier. and a second feedback circuit that feeds back to the input terminal of the transistor, and the second feedback circuit includes an equivalent PNP transistor circuit consisting of an NPN transistor and a current inversion circuit that inverts the collector current of the transistor. Logarithmic amplifier circuit.