JPS6153741B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an easily testable logic integrated circuit, and is particularly suitable for application to regularly structured programmable logic array integrated circuits.

Programmable logic arrays (hereinafter referred to as PLA) are rapidly becoming popular as general-purpose logic integrated circuit elements with a regular structure due to their wide range of uses and ease of design, but they are also becoming more popular in terms of fault testing. It is required to be simple. However, although highly integrated, there are constraints such as a limit on the number of input/output terminals and the inability to directly refer to the internal structure.In particular, large-scale PLAs require a huge amount of time to inspect all possible input combinations. Furthermore, with the advent of PLA, which has built-in registers and can form sequential circuits with complex logic operations, fault testing has become extremely difficult.

For this reason, in such logic integrated circuits, the circuit configuration may be devised in advance to facilitate failure testing. traditionally known
The PLA circuit configuration method that is easy to test is to receive the output of the product term line of the AND logic array in a shift register and derive the contents of this shift register to the outside, and to operate the built-in register as a shift register during testing. There is a device that utilizes a so-called scan path to write test information and read test results to this shift register. However, although both of these methods make it possible to refer to internal structure information by adding a small number of observation terminals, writing to or reading from these shift registers must be performed each time each test input is applied, which is wasteful in testing. This method requires a lot of effort and time, and has drawbacks such as not being able to test dynamic circuit operation under the same conditions as during actual operation.

SUMMARY OF THE INVENTION In view of these drawbacks, it is an object of the present invention to provide an easy-to-test logic integrated circuit that allows fault testing to be performed easily and under dynamic circuit operation at high speed.

The present invention is achieved by using a feedback shift register, which has the effect of compressing and accumulating a long signal sequence, as a means of referring to information on the internal structure of the PLA.

According to the present invention, in a logic integrated circuit having a programmable logic array structure, first to nth exclusive OR circuits each having one input of each of the first to nth logic output lines; , a first receiving each output of the first to n-th exclusive OR circuits;
a modulo-2 adder receiving the output of a flip-flop at one or more predetermined positions from among the first to n-th flip-flops; The output of the 2nd adder is used as the other input of the 1st exclusive OR circuit, and each output of the 1st to (n-1)th flip-flop is used as the other input of the 2nd to nth exclusive OR circuit. a feedback shift register configured to input a test input signal sequence to the other input, and to apply a test input signal sequence to accumulate a signal sequence generated in parallel on each of the logic output lines in the feedback shift register. An easily testable logic integrated circuit is obtained, which is characterized in that the signals are converted into a serial signal sequence and derived.

Next, the present invention will be explained in detail with reference to the drawings.

FIG. 1 is a diagram showing a first embodiment of the present invention. 1 is an AND logic array consisting of a programmable diode matrix.
2 is an OR logic array, which also consists of a programmable diode matrix.
a, a', etc. represent the intersection points of the diode matrices of each of the logic arrays 1 and 2, both of which are constructed as shown in FIG.

In the same figure, 13 is a diode, and 14 is a fuse, and the fuse 14 can be electrically disconnected, for example, to connect each of the logic arrays 1 and 2.
can be programmed arbitrarily.

101 _I ,..., 101 _L are external input signal lines to this logic integrated circuit, and at the same time, AND logic array 1
This is the input signal line for the , and transmits a binary signal. 11
_I ,...,11 _L is a NOT (logical inversion) circuit,
In response to external input signal lines 101 _I ,..., 101 _L
Supplied to another input signal line of AND logic array 1. 102 ₁ , 102 ₂ , . . . 102 _M are output signal lines of the AND logic array 1, and are applied to the external input signal lines 101 _I , . . . , 101 _L according to a logical combination arbitrarily programmed in the AND logic array 1. The logical product of the binary signals obtained is output. i.e. 10
2 ₁ , 102 ₂ ,..., 102 _M are product term lines.
A power supply line 103 supplies a positive voltage. 12 ₁ , 12 ₂ , . . . , 12 _M are resistors, one of which is connected to the power supply line 103 and the other connected to each of the product term lines 102 ₁ , 102 ₂ , . . . , 102 _M to drive them. 201 _I ,…,20
_1M is an output signal line of the OR logic array and an external output signal line that transmits the binary output of this logic integrated circuit. 202 is a grounding wire. 21 ₁ ,…,
21 _M is a resistor, one of which is connected to the grounding line 402 and the other to the external output signal lines 201 _I , . . . , 201 _N. 3 is a feedback shift register added to facilitate inspection according to the present invention; 31 ₁ , 31 ₂ , ..., 31 _M is an EXOR (exclusive OR) circuit; 32 ₁ , 32 ₂ , ..., Reference _{numeral 32M} denotes a master-slave type flip-flop, and the number of flip-flops equal to the number (M) of product term lines 102 ₁ , 102 ₂ , . . . , 102 _M is provided.

33 is a multi-input EXOR circuit, that is, a modulo-2 adder, and flip-flops 32 ₁ , 32 ₂ ,...,
A feedback signal is generated by modulo-2 addition of the output signals of flip-flops at one or more predetermined positions among the 32 _M flip-flops. Product term line 1
The output signal of ₀₂₁ is modulo-2 added to the output signal of the modulo-2 adder 33 in the EXOR circuit ₃₁₁ , and is transmitted to the input of the first-stage flip-flop ₃₂₁ .
Similarly, the output signal of the product term line 1022 is modulo ₂ added to the output signal of the previous stage flip-flop 31 in the EXOR circuit ₃₁₂ , and is added to the output signal of the flip-flop 31 of the next stage.
2 ₂ , each product term line 102 ₂ ,...,10
The _2M output signal is modulo-2 added to the output of the previous flip-flop and is transmitted to the next flip-flop.

301 is a signal line that supplies a synchronization signal; 302
is a signal line that supplies an initialization signal, and this initialization signal connects the flip-flops 32 ₁ , 32 ₂ ,...,
32 _M is set to a predetermined initial state. Reference numeral 303 is an output line of the final stage flip-flop _32M and is connected to an external terminal. Generally, a feedback shift register changes its stored contents depending on a signal sequence applied in the past, and therefore has the effect of accumulating signal sequences, that is, compressing a long signal sequence. Therefore, initialize this feedback shift register 3 and connect the signal line 30.
When driving by applying a synchronization signal to 1 for a certain period of time,
The signal sequences appearing on the product term lines 102 ₁ , 102 ₂ , . . . , 102 _M are compressed and sent to the flip-flops 32 ₁ , 32 ₂ , .
Memorized by _M. At this time, the signal series derived to the output line 303 of the final stage flip-flop 32 _M is, for example, the flip-flop 32 ₁ , 32 ₂ , . . .
If it is received and observed by a shift register with the same number of bits as 32 _M , flip-flops 32 ₁ , 3
2 ₂ ,..., 32 Information equivalent to the content stored in _M is obtained. That is, when a constant test input signal series is synchronized with the synchronization signal applied to the signal line 301 and applied to the external input signal lines 101 _I ,..., 101 _L , the result of the AND operation by the AND logic array 1 is 102 ₂ , 102 _{2 ,} . The resulting signal sequence is also normal.

However, if a fault occurs at the intersection a etc. of the diode matrix of the AND logic array 1 and the intersection a etc. is excited by the test input signal series, the product term line intersecting the intersection point a etc. An erroneous signal is generated, that is, the result of the AND operation is erroneously output, and therefore the result accumulated in the feedback shift register 3 is also different from the normal one, and is further led out to the signal line 303. The signal sequence also appears different from the normal one. It has been explained above that the AND logic array 1 can be easily tested for failures. The failure test of the OR logic array 2 is performed by its output signal lines 201 ₁ ,...,2
This is easy because 0 _M can be directly referenced from the outside.
Product term lines 102 ₁ , 10 that cannot be directly referenced from the outside
2 ₂ , _. The effect of this embodiment is to improve the inspection accuracy.

Next, a case will be described in which the present invention is applied to a PLA with built-in registers.

FIG. 3 is a block diagram showing a second embodiment of the invention. In this figure, the same reference numerals as in FIG. 1 indicate the same structure or the same signal line. 11' ₁ ,...,
_11'P is a NOT circuit. 41 is an internal register, and the synchronization signal is sent from the signal line 301 to the signal line 3.
An initialization signal is applied from 02. 201' ₁ ,
..., 201' _P is a part of the output signal line of the OR logic circuit 2 and drives the internal register 41. 10
1' ₁ , . . . , 101' _P are output signal lines of the internal register 41 and input lines of the AND logic array 1. That is, 101' _I , . . . , 101' _P are internal feedback signal lines. NOT circuit 11' ₁ ,...,1
1' _P is the internal feedback signal line 101' ₁ ,..., 101' _P
It receives the signal, inverts it, and applies it to some inputs of the AND logic circuit 1. In this way, a PLA with built-in registers forms a sequential circuit. 3' is a feedback register having the same structure as the feedback shift register 3 of FIG. 31' ₁ ,...,
31' _P , 31 ₁ ,..., 31 _M are EXOR circuits, and EXOR circuits 31 ₁ , 31 ₂ ,..., 3 in FIG.
1 Works the same as _M. 32' ₁ ,..., 32' _P , 3
2 ₁ ,..., 32 _M are flip-flops, which correspond to the flip-flops 32 ₁ , 32 ₂ ,..., 3 in FIG.
2 Works the same as _M. Signal lines 301 and 30
2 and each flip-flop 32' ₁ ,..., 32' _P ,
Connections with 32 ₁ , . . . , 32 _M are omitted in the diagram.
The EXOR circuits 31' ₁ ,..., 31' _P receive internal feedback signal lines 101' ₁ ,..., 101' _P , and the EXOR circuits 31,..., 31 _M receive the product term line 10 of the AND logic circuit 1.
2 ₁ , . . . , 102 _M are received and applied to the feedback shift register 3' by modulo-2 addition. The feedback shift register 3' has the effect of compressing and storing the signal sequences appearing on the internal feedback signal lines 101' ₁ ,..., 101' _P and the product term lines 102 ₁ ,..., 102 _M of the AND logic array 1. . The failure test of this logic integrated circuit is carried out using the signal line 302.
The process starts by applying an initialization signal to set the internal register 41 and feedback shift register 3' to predetermined initial states. signal line 30
1, a certain test input signal series is applied to the external input signal lines 101 ₁ ,..., 101 in synchronization with the synchronization signal applied to the external input signal lines 101
_M , the output result of AND logic array 1 passes through product term lines 101 ₁ ,..., 101 _M , and also OR
Some output signal lines 201' ₁ of the logic array 2,
..., 201' Internal register 41 driven by _P
The output results are applied to the feedback register 3' through signal lines 101' ₁ ,..., _101'P ,
It is derived as a compressed signal sequence to the signal line 303. If an erroneous output result occurs on any of these signal lines 101' ₁ ,..., 101' _P and 102 ₁ ,..., 102 _M , the signal sequence derived to the signal line 303 will also be different from the normal one. appear.

In this way, it is possible to inspect a failure occurring in a part of the AND logic array 1, the OR logic array 2, or the internal register 41, which have output signal lines that cannot be directly referenced from the outside. However, it does not specify the location where the failure occurred.

Since the output signal lines 201 ₁ , . . . , 201 _M of the remaining part of the OR logic array 2 are directly connected to the outside, a failure test is easy. An advantage of this embodiment is that the information of each logical output line at different locations can be collected into a single observation mechanism.

As can be easily inferred through this embodiment, it is not necessary to receive each output signal line of the AND logic array 1, OR logic array 2, and internal register 41 by one feedback shift register.
They may be received by separate feedback shift registers. In this case, there are multiple lines corresponding to the signal line 303 from which the test results are derived, but the location of the failure can be identified within the AND logic array 1, OR logic array 2, or internal register 41, for example. .

Furthermore, in order to better explain the effects of the present invention, an example of the method for testing a logic integrated circuit according to the present invention will be described.

Referring to FIG. 4, 51 is a logic integrated circuit of the present invention, the following configuration should be included in a testing device for testing the logic integrated circuit 51, 52 is a random number signal generator, and 53 and 56 are expected value register, 54
is a signal sequence compressor, 55 is a shift register, 5
7 and 58 are comparators. The random number generator 52 obtains a predetermined test input as a random number signal, and the signal sequence compressor 54 receives external output signals 201 ₁ ,...,
_201M can be compressed and stored, and for example, one having the same structure as the feedback shift register 3 shown in FIG. 1 may be used. Testing is performed by indirectly comparing the output results of a regular logic integrated circuit that has been confirmed to operate normally and a logic integrated circuit to be tested. According to the testing procedure, first, a regular logic integrated circuit is set in 51. After applying an initialization signal to the signal line 302 in the test mode, if a random number signal generated by the random number generator 52 is applied to the signal line 301 along with a synchronization signal to the logic integrated circuit 51, the logic integrated circuit 5
1, which cannot be directly observed, is compressed by the feedback shift register 3 or 3' and appears sequentially through the signal line 303, so it is shifted into the shift register 55 and stored.

Further, directly observable external output signals 201 ₁ , . . . , 201 _N of the logic integrated circuit 51 are compressed and stored in the signal sequence compressor 54 . After applying a random number signal sequence of constant and sufficient length, the operation is completed. The contents stored in the signal sequence compressor 54 and shift register 55 are stored in the logic integrated circuit 51.
These are the results obtained when the functions operate normally, and are transferred as they are to the expected value registers 53 and 56, respectively.

Next, if you set the logic integrated circuit to be tested in 51 and perform the same operation as above, the output result of the logic integrated circuit 51 will be transferred to the signal sequence compressor 54.
On the other hand, the signals are compressed and stored in the shift register 55. After that, the signal sequence compressor 5
The contents of 4 are compared with the contents of the expected value register 53, and the contents of the shift register 55 are compared with the contents of the expected value register 56 by comparators 57 and 58, respectively. If matching results are output from both comparators 57 and 58, the logic integrated circuit 51 to be inspected can be determined to be non-defective with a high probability. Conversely, if a mismatch result is output to at least one of the comparators 57 and 58, it is determined that a fault exists in the logic integrated circuit 51 to be tested.

To summarize the above explanation, logic output lines that cannot be directly referenced externally, such as the product term line or internal feedback signal line of an AND logic array, can be indirectly referenced using fewer observation terminals by the principle of signal sequence compression. An advantage of the present invention is that it makes it easier to test for faults, and as a result, more logic output lines can be observed, thereby improving test accuracy.

Since the feedback shift register added for testing is installed without interfering with normal circuit operation, failure testing can be performed under exactly the same conditions as normal operation, and therefore can be performed at high speed and with high performance. Another advantage of the present invention is that it is possible to conduct a comprehensive failure test.

Another advantage of the present invention is that the fault test is simple because the result of the fault test is determined by verifying the final information accumulated in the feedback shift register.

The present invention has a remarkable effect when applied to a logic integrated circuit such as a PLA which has a regular structure and whose internal structure is difficult to directly refer to from the outside.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing a first embodiment of the present invention, and FIG.
The figure is a diagram specifically showing the diode in Figure 1, the intersection points a, a', etc. of the matrix, Figure 3 is a block diagram showing the second embodiment of the present invention, and Figure 4 is a diagram showing the effects of the present invention. FIG. 2 is a diagram showing an example of a method for testing a logic integrated circuit according to the present invention for explanation. In the figure, 1...AND logic array, 2...OR logic array, 3
...Feedback shift register, a, a'...Cross point of diode matrix, 11 ₁ ,...,11
_L , 11' ₁ ,..., 11' _P ...NOT circuit, 31 ₁ ,
31 ₂ ,...,31 _M ,31' ₁ ,...,31' _P ...
EXOR circuit, 32 ₁ , 32 ₂ ,..., 32 _M , 3
2' ₁ ,...,32' _P ...Flip-flop, 33...
Modulo-2 adder, 12 ₁ , 12 ₂ ,..., 12 _M , 2
1 ₁ ,...,21 _N ...Resistor, 13...Diode,
14...Fuse, 41...Internal register, 51...Logic integrated circuit of the present invention, 52...Random number generator, 53,
56...Expected value register, 54...Signal sequence compressor,
55...Shift register, 57, 58...Comparators.

Claims (1)

[Scope of Claims] 1. In a logic integrated circuit having a programmable logic array structure, first to nth exclusive OR circuits each having one input as each of the first to nth logic output lines; , first to nth flip-flops receiving respective outputs of the first to nth exclusive OR circuits, and one or more predetermined flip-flops from among the first to nth flip-flops. a modulo-2 adder that receives the output of the flip-flop at the position, the output of the modulo-two adder is used as the other input of the first exclusive OR circuit, and a feedback shift register configured to apply each output of the flip-flop to the other input of the second to nth exclusive OR circuits, respectively;
The test method is characterized in that the signal series generated in parallel on each of the logic output lines by applying the test input signal series are accumulated in the feedback shift register, converted into a serial signal series, and derived. logic integrated circuit. 2. The testable logic integrated circuit according to claim 1, wherein the logic output line is a product term line of an AND logic array. 3. The easily testable logic integrated circuit according to claim 1, wherein the logic output line is an internal feedback signal line. 4. The testable logic integrated circuit according to claim 1, wherein the logic output line is a composite of a product term line of an AND logic array and an internal feedback signal line.