JPS6153722A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS6153722A JPS6153722A JP17400384A JP17400384A JPS6153722A JP S6153722 A JPS6153722 A JP S6153722A JP 17400384 A JP17400384 A JP 17400384A JP 17400384 A JP17400384 A JP 17400384A JP S6153722 A JPS6153722 A JP S6153722A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- film
- substrate
- semiconductor substrate
- sb2o3
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 32
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 10
- 239000000758 substrate Substances 0.000 claims abstract description 31
- 238000000034 method Methods 0.000 claims abstract description 16
- 230000003647 oxidation Effects 0.000 claims abstract description 3
- 238000007254 oxidation reaction Methods 0.000 claims abstract description 3
- 230000001681 protective effect Effects 0.000 claims description 10
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 6
- 229910052710 silicon Inorganic materials 0.000 claims description 6
- 239000010703 silicon Substances 0.000 claims description 6
- WATWJIUSRGPENY-UHFFFAOYSA-N antimony atom Chemical compound [Sb] WATWJIUSRGPENY-UHFFFAOYSA-N 0.000 claims description 5
- 229910052787 antimony Inorganic materials 0.000 claims description 4
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical group N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 3
- WUOBERCRSABHOT-UHFFFAOYSA-N diantimony Chemical compound [Sb]#[Sb] WUOBERCRSABHOT-UHFFFAOYSA-N 0.000 claims 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical group O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims 2
- 235000012239 silicon dioxide Nutrition 0.000 claims 1
- 239000000377 silicon dioxide Substances 0.000 claims 1
- 238000009792 diffusion process Methods 0.000 abstract description 11
- 239000012535 impurity Substances 0.000 abstract description 6
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 abstract description 2
- 238000001704 evaporation Methods 0.000 abstract description 2
- 239000003960 organic solvent Substances 0.000 abstract description 2
- 229910052760 oxygen Inorganic materials 0.000 abstract description 2
- 239000001301 oxygen Substances 0.000 abstract description 2
- 239000002904 solvent Substances 0.000 abstract description 2
- ADCOVFLJGNWWNZ-UHFFFAOYSA-N antimony trioxide Inorganic materials O=[Sb]O[Sb]=O ADCOVFLJGNWWNZ-UHFFFAOYSA-N 0.000 abstract 4
- YEAUATLBSVJFOY-UHFFFAOYSA-N tetraantimony hexaoxide Chemical compound O1[Sb](O2)O[Sb]3O[Sb]1O[Sb]2O3 YEAUATLBSVJFOY-UHFFFAOYSA-N 0.000 abstract 4
- 239000000126 substance Substances 0.000 abstract 1
- 238000007669 thermal treatment Methods 0.000 abstract 1
- 239000012808 vapor phase Substances 0.000 abstract 1
- 238000005530 etching Methods 0.000 description 4
- 229910052785 arsenic Inorganic materials 0.000 description 3
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 3
- 239000003795 chemical substances by application Substances 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 239000005368 silicate glass Substances 0.000 description 2
- 238000009835 boiling Methods 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000008020 evaporation Effects 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 238000010791 quenching Methods 0.000 description 1
- 230000000171 quenching effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/22—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
- H01L21/225—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities using diffusion into or out of a solid from or into a solid phase, e.g. a doped oxide layer
- H01L21/2251—Diffusion into or out of group IV semiconductors
- H01L21/2254—Diffusion into or out of group IV semiconductors from or through or into an applied layer, e.g. photoresist, nitrides
- H01L21/2255—Diffusion into or out of group IV semiconductors from or through or into an applied layer, e.g. photoresist, nitrides the applied layer comprising oxides only, e.g. P2O5, PSG, H3BO3, doped oxides
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Bipolar Transistors (AREA)
Abstract
Description
【発明の詳細な説明】
産業上の利用分野
本発明は、半導体装置の製造方法、よシ詳しく述べるな
らば、バイポーラトランジスタの埋込みコレクタ層の形
成方法に関するものでちる。DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a method of forming a buried collector layer of a bipolar transistor.
従来の技術
バイポーラトランジスタの製造においてはコレクタのシ
リーズ抵抗を下げるために埋込みコレクタ層が半導体基
板（すなわち、シリコンウェノ・）内に形成されて、こ
の半導体基板上にエピタキシャル層が形成されている。In the manufacture of conventional bipolar transistors, a buried collector layer is formed in a semiconductor substrate (i.e., silicon wafer) to reduce the series resistance of the collector, and an epitaxial layer is formed on the semiconductor substrate.
埋込みコレクタ層を形成するためにはヒ素（Ａ８）又は
アンチモン（ｓｂ）を選択的に基板内へ熱拡散又はイオ
ン注入によって導入しているわけであるが、エピタキシ
ャル層形成時での埋込み層からの不純物（Ａｓ又はｓｂ
）のオートドーピングはｓｂのほうがＡｓよりも小さい
ので、Ｓｂが多く使用されている。In order to form the buried collector layer, arsenic (A8) or antimony (sb) is selectively introduced into the substrate by thermal diffusion or ion implantation. Impurities (As or sb
) autodoping is smaller in sb than in arsenic, so Sb is used more often.
発明が解決しようとする問題点
ｓｂの熱拡散による埋込み層の形成にはアンチモンシリ
ケートガラス（ＳｂＳＧ）を用いて行なわれているが、
半導体基板表面にロゼツトが発生することがある。この
ロゼツトとはシリコンリッチな５ｂ−８ｉ−ｏ の化合
物であシ、不純物を含むＳ１酸化膜から不純物の熱拡散
を行なうと発生し通常のエツチング液であるＩＦ液では
エツチング不可能であシ特別なエツチング液を必要とし
、さらに、このロゼツト上ではエビタシャル成長がうま
くいかない。そこで、ロゼツト発生を防止するためには
アンチモンシリケートカラスを用いずに、拡散ソースで
ある三酸化二ア／チモン（ｓｂ２ｏ、）を半導体基板に
直接塗布しｓｂ １拡散させるのが望ましい。Problem to be Solved by the Invention Antimony silicate glass (SbSG) is used to form a buried layer by thermal diffusion of sb.
Rosettes may appear on the surface of the semiconductor substrate. This rosette is a silicon-rich 5b-8i-o compound, which is generated when impurities are thermally diffused from the impurity-containing S1 oxide film, and cannot be etched with the IF solution, which is a normal etching solution. This method requires a suitable etching solution, and furthermore, the vitreous growth does not work well on this rosette. Therefore, in order to prevent the occurrence of rosettes, it is desirable to directly apply dia/thimonium trioxide (sb2o,) as a diffusion source to the semiconductor substrate and diffuse sb1 without using antimony silicate glass.
しかしながら、５ｂ２０．はその融点が６５６℃であり
、沸点が１４２５℃でおり、一方熱拡散温度が１２００
ないし１２５０℃であるた、ｌＱＫ、半導体基体中にｓ
ｂが十分に拡散されない。そのために、埋込み層の表面
抵抗が期待するほど低減されない、すなわち、コレクタ
のシリーズ抵抗が十分に下がらない。However, 5b20. has a melting point of 656°C, a boiling point of 1425°C, and a thermal diffusion temperature of 1200°C.
to 1250°C, lQK, s in the semiconductor substrate
b is not sufficiently diffused. Therefore, the surface resistance of the buried layer is not reduced as expected, that is, the series resistance of the collector is not reduced sufficiently.
問題点を解決するための手段
本発明は、上記問題点を解消して５ｂ２ｏ、を用いて埋
込みコレクタ層を形成する方法を提供するもので、工程
（７）〜（６）；（７）半導体基板上に所定・ぐターン
の酸化膜を形成する工程；（イ）半導体基板および酸化
膜上の全面に５ｂ２０５層を形成する工程；（つ）Ｓｂ
２０５層上に保護膜を形成する工程；に）Ｓｂ２Ｏ２層
からｓｂを半導体基板内へ熱拡散させる工程；および（
４）保護膜、５ｂ２０３層および酸化膜を除去する工程
；を含んでなる半導体装置の製造方法を提供する。Means for Solving the Problems The present invention solves the above problems and provides a method of forming a buried collector layer using 5b2o. Step of forming an oxide film of a predetermined pattern on the substrate; (a) Step of forming a 5b205 layer on the entire surface of the semiconductor substrate and the oxide film; (1) Sb
Step of forming a protective film on the 205 layer; 2) Step of thermally diffusing sb from the Sb2O2 layer into the semiconductor substrate;
4) A method for manufacturing a semiconductor device is provided, which includes the step of removing the protective film, the 5b203 layer, and the oxide film.
作用
本発明に係る半導体装置の製造方法では熱拡散処理を行
なう際に５ｂ２０３層が保護膜によりて覆われているの
で、５ｂ２０３の蒸発が防止されてｓｂの半導体基板へ
の拡散が促進される。Function: In the method for manufacturing a semiconductor device according to the present invention, the 5b203 layer is covered with a protective film during thermal diffusion treatment, so evaporation of 5b203 is prevented and diffusion of sb into the semiconductor substrate is promoted.
ハ
実施例
以下、添付図面を参照して本発明の好ましい実施態様例
によって本発明を説明する。C. Examples Hereinafter, the present invention will be described by way of preferred embodiments of the present invention with reference to the accompanying drawings.
第１Ａ図ないし第１Ｅ図は、本発明に係る半導体装置の
製造方法に従って埋込みコレクタ層を形成する工程を説
明する半導体基板の概略断面図でちる。1A to 1E are schematic cross-sectional views of a semiconductor substrate illustrating the process of forming a buried collector layer according to the method of manufacturing a semiconductor device according to the present invention.
まず、半導体基板１としてｐｇシリコンウェノ・を用意
し、通常の熱酸化法によって、第１Ａ図に示すように、
酸化膜２を形成する。この酸化膜２は二重化珪素（Ｓ
ｒ ０２ ）であシ、その厚さは、例えば、約４００
ｎｍである。First, a pg silicon wafer is prepared as a semiconductor substrate 1, and as shown in FIG. 1A, by a normal thermal oxidation method,
An oxide film 2 is formed. This oxide film 2 is made of double silicon (S
r 02 ), the thickness of which is, for example, about 400
It is nm.
次に、酸化膜２上にレジスト３と塗布し、露光現像によ
シ形成すべき埋込み層に相当する窓を有する所定・やタ
ーンにし、適切なエツチング剤、例えば、緩衝ＩＦ液に
よって酸化膜２を週択的にエツチングして拡散開口部４
および５を、第１Ｂ図のように形成する。したがって、
酸化膜２は開口部４および５と有する所定・々ターンと
なっている。Next, a resist 3 is coated on the oxide film 2, formed into a predetermined turn having a window corresponding to a buried layer to be formed by exposure and development, and the oxide film 2 is etched with an appropriate etching agent such as a buffered IF solution. selectively etching the diffusion opening 4
and 5 are formed as shown in FIG. 1B. therefore,
The oxide film 2 has openings 4 and 5 in predetermined turns.
そして、レノストを除去する。Then, remove Renost.
有機溶剤に溶か己た５ｂ２０．を酸化膜２に開口部４お
よび５を開けた半導体基板に直接塗布し、溶剤を揮発さ
せて５ｂ２０３層６を、第１Ｃ図に示すように、形成す
る。5b20 dissolved in organic solvent. is applied directly to a semiconductor substrate with openings 4 and 5 in the oxide film 2, and the solvent is evaporated to form a 5b203 layer 6 as shown in FIG. 1C.
次に、５ｂ２ｏ３屡ｓ上に酸素を通過させない保護膜７
（第１Ｄ図）を形成する。この保護膜７は、例えば、化
学的気相成長法（ＣＶＤ法）による窒化珪素（Ｓｉ３Ｎ
４）であシ、厚さは約１００ ｎｍでよい。Next, a protective film 7 that does not allow oxygen to pass over 5b2o3
(Fig. 1D) is formed. This protective film 7 is made of, for example, silicon nitride (Si3N) formed by chemical vapor deposition (CVD).
4) The thickness may be about 100 nm.
そして、この半導体基板を加熱炉内に入れて１２５０℃
の温度に所定時間（例えば、１時帥保持することによっ
て酸化膜開穴部に於いて半導体基板ｌと接触している５
ｂ２０３層６からｓｂを熱拡散で基板１内へ導入して、
Ｓｂ不純物導入領域である埋込みコレクタ層８および９
（第１Ｄ図）と形成する。Then, this semiconductor substrate was placed in a heating furnace and heated to 1250°C.
5 which is in contact with the semiconductor substrate l at the oxide film opening by holding the temperature at
Introducing sb from the b203 layer 6 into the substrate 1 by thermal diffusion,
Buried collector layers 8 and 9 which are Sb impurity doped regions
(Fig. 1D).
熱拡散後に、保護膜７．５ｂ２０３層６および酸化膜２
を適切な工、チング剤で除去して、半導体基板１を第１
Ｅ図のように露出させる。このように形成された埋込み
コレクタ層８および９は、例えば、その深さが約２．７
μｍであり、その表面抵抗が約２８４／ｌ］である。ま
た、半導体基板１の表面にロゼツトは発生していない。After thermal diffusion, protective film 7.5b203 layer 6 and oxide film 2
is removed using an appropriate process or a quenching agent, and the semiconductor substrate 1 is removed as the first
Expose as shown in figure E. The buried collector layers 8 and 9 formed in this way have a depth of about 2.7 mm, for example.
[mu]m, and its surface resistance is approximately 284/l]. Furthermore, no rosettes were generated on the surface of the semiconductor substrate 1.
そして、通常のエピタキシャル成長法によりて半導体基
板１上にＮ型シリコンエピタキシャル層（図示せず）を
形成し、このエピタキシャル層に所定のペース領域。Then, an N-type silicon epitaxial layer (not shown) is formed on the semiconductor substrate 1 by a normal epitaxial growth method, and a predetermined space region is formed on this epitaxial layer.
エミッタ領域、コレクタ・コンタクト領域などを公知の
バイポーラトランジスタ製造方法にしたがって形成する
ことになる。The emitter region, collector contact region, etc. are formed according to a known bipolar transistor manufacturing method.
発明の効果
本発明の方法にしたがって埋込みコレクタ層を形成する
ならば、不純物を含むＳｔ酸化膜を使用せずにＳｂを熱
拡散することが可能なので、ロゼツトを発生させること
なく所定濃度（すなわち、所定表面抵抗）の埋込みコレ
クタ層（不純物導入領域）が得られる。Effects of the Invention If a buried collector layer is formed according to the method of the present invention, it is possible to thermally diffuse Sb without using a St oxide film containing impurities. A buried collector layer (impurity-introduced region) with a predetermined surface resistance is obtained.
第１Ａ図ないし第１Ｅ図は、本発明に係る半導体装置の
製造方法の工程を説明する半導体基板の概略断面図であ
る。
１・・・半導体基板、２・・・酸化膜、４．５・・・開
口部、６・・・５ｂ２０３層、７・・・保護膜、８，９
・・・埋込みコレクタ層。1A to 1E are schematic cross-sectional views of a semiconductor substrate for explaining the steps of the method for manufacturing a semiconductor device according to the present invention. DESCRIPTION OF SYMBOLS 1... Semiconductor substrate, 2... Oxide film, 4.5... Opening part, 6... 5b203 layer, 7... Protective film, 8, 9
...Embedded collector layer.
Claims (1)
工程； （イ）前記半導体基板および酸化膜上の全面に三酸化二
アンチモン層を形成する工程； （ウ）前記三酸化二アンチモン層上に保護膜を形成する
工程； （エ）前記三酸化二アンチモン層からアンチモンを前記
半導体基板内へ熱拡散させる工程；および（オ）前記保
護膜、三酸化二アンチモン層および酸化膜を除去する工
程； を含んでなる半導体装置の製造方法。 ２、前記酸化膜がシリコン半導体基板の熱酸化による二
酸化珪素である特許請求の範囲第１項記載の方法。 ３、前記保護膜が窒化珪素である特許請求の範囲第１項
記載の方法。[Claims] 1. The following steps (a) to (e): (a) forming an oxide film in a predetermined pattern on the semiconductor substrate; (b) forming trioxide on the entire surface of the semiconductor substrate and the oxide film; (c) forming a protective film on the diantimony trioxide layer; (d) thermally diffusing antimony from the diantimony trioxide layer into the semiconductor substrate; and ( e) a step of removing the protective film, the diantimony trioxide layer, and the oxide film; a method for manufacturing a semiconductor device, comprising: 2. The method according to claim 1, wherein the oxide film is silicon dioxide formed by thermal oxidation of a silicon semiconductor substrate. 3. The method according to claim 1, wherein the protective film is silicon nitride.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17400384A JPS6153722A (en) | 1984-08-23 | 1984-08-23 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17400384A JPS6153722A (en) | 1984-08-23 | 1984-08-23 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6153722A true JPS6153722A (en) | 1986-03-17 |
Family
ID=15970946
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP17400384A Pending JPS6153722A (en) | 1984-08-23 | 1984-08-23 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6153722A (en) |
-
1984
- 1984-08-23 JP JP17400384A patent/JPS6153722A/en active Pending
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