JPS6151495B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to voltage and reactive power control for maintaining proper voltage in a power system and reducing power transmission losses, and in particular to cooperatively controlling on-load tap switching transformers and phase adjustment equipment. This is related to the method used.

Control of voltage and reactive power in a primary substation is generally performed by controlling phase adjustment equipment such as an on-load tap switching transformer, a power capacitor, and a shunt reactor using a control device. The goal of this control is to maintain the back secondary voltage and bank secondary reactive power of the transformer at their respective target values. For this reason, conventionally, based on the target value set by predicting the load in advance,
A voltage adjustment relay controls the tap switching of the transformer, and a 24-hour timer controls the opening and closing of the phase adjustment equipment.
However, in this individual control, even if the voltage is adjusted by tap switching based on the target value, the voltage changes due to the opening and closing of the phase adjustment equipment during reactive power adjustment, so the voltage may deviate from the target value. This has the disadvantage that the number of tap switching operations is increased and the life of the tap switching mechanism is shortened.Moreover, the increase in the number of operations increases the tap position to the upper and lower limits. This also leads to an increased chance of so-called "tap jam", which causes the problem that further switching operations are no longer possible during voltage adjustment, making it impossible to accurately adjust the voltage. In addition, in voltage control using conventional voltage adjustment relays, only one tap operation command is sent for each relay operation time, so even if the voltage deviates significantly from its target value, it cannot be adjusted quickly. However, there is a problem in that it is difficult to adjust the voltage according to changes in the load.

The present invention has been made in view of the above-mentioned points, and its purpose is to provide a control system that allows voltage regulation to be carried out in coordination with an on-load tap-changing transformer and a phase modifier. be. Another object of the present invention is to provide a control system that can adjust reactive power while maintaining voltage at an appropriate value.

Embodiments of the present invention will be described below with reference to the drawings. In Figure 1, T ₁ , T ₂ , T ₃ , and T ₄ are multiple load tap switching transformers (hereinafter abbreviated as LRT) that are operated in parallel, and the primary side is the upper system (e.g.
154KV) line, and a current transformer is installed on each secondary side.
It is equipped with CT ₁ , CT ₂ , CT ₃ , and CT ₄ and is connected to a bank secondary bus (hereinafter simply referred to as bus) BUS, and a load L connected to this bus BUS is
Power is being transmitted at 154KV/77KV. Also, not shown in this LRTT ₁ , T ₂ , T ₃ , T ₄
Equipped with LR control panel, busbar can be controlled by tap switching operation.
It is designed to adjust the bus voltage V _B of BUS. SC ₁ , SC _{2 .} . . SC _o are a plurality of power capacitors (hereinafter referred to as capacitors) each connected to the above-mentioned bus line BUS via the power circuit breakers CB ₁₁ , CB ₁₂ . . . CB _1o . SnR ₁ , ShR ₂ ...ShR _n is the above bus line
A plurality of shunt reactors (hereinafter referred to as reactors) are each connected to the BUS via circuit breakers CB ₂₁ , CB ₂₂ , and CB _2n . CT _B is the current transformer CT ₁ above,
A current transformer is connected from CT ₂ , CT ₃ , and CT ₄ to derive a bank total current I _B , and PT is a voltage transformer connected to the bus BUS to derive a bus voltage V _B. A is a control device that sends operation commands to the LRT, capacitor, and reactor. This will be explained. 1 is a current converter connected to the current transformer CT _B , which converts the bank total current I _B into voltage, converts it into DC, and outputs it through a filter with a constant time constant (for example, 2 seconds). It's summery. 2 is the above current transformer CT _B and voltage transformer
A reactive power converter connected to the PT calculates the reactive power by inputting the bank total current for two phases and the voltage for three phases, converts it to DC, and converts it to a fixed time constant (for example, 2 seconds). The output is passed through a filter. 3 is the above voltage transformer PT
A voltage converter connected to the bus converts the bus voltage V _B from an effective value to DC via an isolation transformer, adds the three phases, and outputs the result through a filter with a fixed time constant (for example, 0.3 seconds). ing. The outputs of the current converter 1, reactive power converter 2, and voltage converter 3 are output as digital outputs via an analog-to-digital converter 5 having a multiplexer to a calculation processing unit (hereinafter abbreviated as CPU) 6.
It is now being sent to 7 and 8 are CPU
In the storage unit connected to 6, the storage unit 7 (hereinafter referred to as
A processing program for voltage and reactive power control is stored in the PROM 7 (referred to as PROM 7), and this processing program is read out and executed by the CPU 6. In addition, the storage unit 8 (hereinafter
Various data for executing the processing program stored in the PROM 7 are stored in the RAM 8), and this data is read out according to the program and the CPU 6 performs arithmetic processing. 9 is an input/output section connected to the CPU 6, and control conditions (for example, tap positions of LRTT ₁ , T ₂ , T ₃ , T ₄ , capacitors SC ₁ , SC ₂ . . . SC _o and reactors ShR ₁ , ShR ₂ . . . Inputs a signal indicating ShR _n input, trip status, etc.) to the CPU 6, and
Convert the output of CPU6 to drive output,
It is designed to be sent as an operation command to the LRT, capacitor, and reactor. and,
The CPU 6 calculates and sets target values V _ref and Q _ref for voltage and reactive power control using the bank total current I _B read from the current converter 1, and sets the voltage converter based on the target values V _ref and Q _ref . 3. It compares and determines the bus voltage V _B and reactive power Q read from the reactive power converter 2 and sends out an output signal for voltage and reactive power control. the above
The target value V _ref for voltage control set by the CPU 6 is V _clk = V _BO + K _B · I _B ... (1) V _rer = V _clk + V _sft ... (2) However, I _B : Bank Total current (KA) V _BO : Bus voltage (KV) when bank total current I _B is zero K _B : Feeder load center point drop compensation coefficient (KV/KA) V _sft : Shift amount (KV) for bus voltage target value It is set by an arithmetic expression.
The compensation coefficient K _B in the above equation (1) is the bus voltage V _B
The ratio (△V/△I) of the difference between the maximum compensation value and the minimum compensation value (△V) of The compensation coefficient K _B (for example, 30 KV/KA) and the bus voltage V _B (for example, 71 KV) at zero current are stored in the RAM 8. In addition, the shift amount V _sft in equation (2) above may be due to irregular system configurations due to work or transmission line failures, etc.
If the amount of voltage drop in the power transmission route is different from normal, such as when supporting power is transmitted to the supply area of the next substation,
To compensate for this, multiple compensation values are set in advance (for example, 1 step is 0.8KV, and
(step) can be selected by remote or direct operation and stored in the RAM 8 via the input/output section 9. Further, the target value Q _ref of the reactive power control calculated and set by the CPU 6 is as follows: Q _clk = Q _NIT -X・I _B ² ... (3) Q _ref = Q _clk + Q _sft ... (4) However, I _{B :} Bank total current (KA) Q _NIT : Reactive power when bank total current I _{B is} ^zero (MV _ar ) _ar ) is set by the arithmetic expression.
The reactance compensation X in equation (3) above is determined by the line reactance of the upper system, the bank secondary maximum load current, etc. What is this (for example, 50) and the reactive power Q _NIT at zero current (for example, 20)? It is stored in RAM8 in advance. In addition, the shift amount Q _sft in (4) above should be adjusted when the phase adjustment equipment in the upper system is stopped due to work, or when the voltage in the upper system tends to rise excessively on special days such as Obon holidays and New Year holidays. A plurality of compensation values set in advance for compensation (for example, 2 steps up and down with 1 step of 20 MV _ar ) can be selected by remote or direct operation and stored in the RAM 8 via the input/output section 9. Further, the target values V _ref and Q _ref calculated and set by the CPU 6 are executed at extremely short fixed time intervals (for example, every 0.5 seconds).
10 is an LR control circuit provided in the input/output unit 9 corresponding to LRTT ₁ , T ₂ , T ₃ , and T ₄ , and transmitting a tap switching operation command to LRTT ₁ , T ₂ , T ₃ , and T ₄ ; It is. This is as shown in Figure 2.
Connect the changeover switch 43VQC to the "auto" side contact of the changeover switch 43A provided on the LR control panel (not shown) of LRTT ₁ , T ₂ , T ₃ , T ₄ , and connect the normally open contact of this changeover switch 43VQC (hereinafter referred to as "use"). Normally open contacts 90 of relays 90R ₁ , 90L ₁
One end of R _1a and 90L _1a are connected in parallel, and the normally closed contact of changeover switch 43VQC (hereinafter referred to as the "exclusion" side) is connected to the normally open contact of voltage adjustment relays 90R and 90L (not shown) provided on the LR control panel. 90R
One ends of the normally open contacts 90R a and 90L _a are connected in parallel, and the normally open contacts 90R ₁ are connected to the other ends of the normally open contacts 90R _a and 90L _{a .}
Connect the other ends of _a and 90L _1a , and connect the relay 9 above.
0R ₁ and 90L ₁ are connected to the control power supply so that one of them is energized by the output of the CPU 6, and the tap switching of LRTT ₁ , T ₂ , T ₃ , and T ₄ is performed by energizing the relay 90R ₁ . Operate to boost side, relay 90L ₁
The tap switch is operated to the step-down side by energizing the voltage. Then, for the relay 90R ₁ or 90L ₁ of the LR control circuit 10,
The output of the CPU 6 has a stepwise inverse time limit characteristic similar to the time limit characteristic in normal voltage regulation, and is sent out when the operating time limit determined by the deviation of the bus voltage V _B from the calculated target value V _ref is reached. I'm starting to do that. As shown in FIG. 3, a dead zone δ and an adjustment range are individually provided based on the target value V _ref , and this adjustment range is divided into a plurality of regions W ₁ , W ₂ ,
Divide into W ₃ and W ₄ and set time weights n ₁ , n ₂ , n ₃ with respect to the reference time T for each area, and calculate the clock count of the time when the bus voltage V _B is applied to each area with these time weights. Approximate integration is performed by CPU 6 using CNT ₁ , CNT ₂ , CNT ₃ , and CNT ₄ , and the value is obtained from the constant K ₉₀ (W ₁ × CNT ₁ + W ₂ × CNT ₂ + W ₃ × CNT ₃ + W ₄ × CNT ₄ ) It is designed to output when a predetermined time-up condition is reached (when the operation time limit is reached). In addition, in order to maintain the appropriate voltage even during periods when the load L fluctuates rapidly (for example, when the load rises in the morning), the operating time limit for the voltage adjustment is determined in advance by determining a time period and setting the constant K ₉₀ for that time period. It is designed to respond to load fluctuations by shortening the time (to 1/4, for example) so that the time-up condition is reached sooner. 11 is a capacitor
SC ₁ , SC ₂ . . . A plurality of SC control circuits provided in the input/output section 9 in correspondence with SC _o and respectively sending a closing or cutting command to the shield breakers CB ₁₁ , CB ₁₂ ...CB _1o . It is. This is the SC control circuit 1 for the control power supply.
Relay 43ASC is energized by closing operation of changeover switch 43A (not shown) in No. 1 to the "auto" side.
Through the normally open contact 43ASC _a of the relay SC _1C ,
One end of the normally open contacts SC _{1Ca and} SC _1Ta of SC 1T are connected in parallel, and a closing coil (not shown) of CB ₁₁ is connected to the other end of the normally _open contact SC _1Ca . Connect a trip coil (not shown) of CB ₁₁ to the end, and connect the above relay SC _1C ,
SC _1T is connected to the control power supply so that either one is excited by the output of CPU6, and the relay SC _1C
By energizing the circuit breaker, for example CB ₁₁ , it closes the capacitor, for example SC ₁ , and also the relay
By excitation of SC _1T , the circuit breaker, for example, CB ₁₁ is energized, thereby tripping the capacitor, for example, SC ₁ . 12 is reactor ShR ₁ ,
ShR ₂ ...ShR _n Corresponding to the input/output section 9, a plurality of shredder breakers CB ₂₁ , CB 22 ... CB 2n are provided with a plurality of shredder breakers CB 21 , CB ₂₂ ... which send out a cutoff command respectively to CB _2n .
This is the ShR control circuit. As shown in FIG. 5, this is the normally open contact 43 of the relay 43AShR, which is energized by closing the switch 43A (not shown) of the ShR control circuit 12 to the "auto" side in the control power supply.
Normally open contact of relay ShR _1C , ShR _1T via AShR _a
One end of ShR _1Ca and ShR _1Ta are connected in parallel, and the other end of the normally open contact ShR _1Ca is connected to a breaker, e.g., a closing coil (not shown) of CB ₂₁ , and the other end of the normally open contact ShR _1Ta is connected to a breaker, e.g. A trip coil (not shown) of CB ₂₁ is connected, and the above-mentioned relays ShR _1C and ShR _1T are connected to the control power supply so that one of them is energized by the output of CPU ₆ . The reactor, for example, ShR ₁ , is turned on by turning on the reactor, for example, CB ₂₁ , and the reactor, for example, ShR ₁ , is tripped by energizing the relay ShR _1T , which causes the breaker, for example, CB ₂₁ , to open. ing. And these SC control circuits 1
1. The output of the CPU 6 to the ShR control circuit 12 is
It is sent during voltage control and reactive power control, and during voltage adjustment, when the bus voltage V _B exceeds the bus voltage over-drop detection value V _EL or over-rise detection value V _EH stored in RAM8, LRTT ₁ , Sent when the tap positions of T ₂ , T ₃ , and T ₄ are at the upper limit (lowest output voltage) or lower limit (highest output voltage) and a "tap jam" occurs and further tap switching is required. It's becoming more and more common. Also, when adjusting the reactive power, the reactive power Q is the target value Q _ref and the maximum value Q of the single capacitance of the capacitor and reactor stored in RAM8.
Excessive delay detection value Q _EH calculated from _snax
(Q _ref +Q _snax ), excessive lead detection value Q _EL Q _ref - Q _sna
x ), and the operating value Q _pp is determined by the target value Q _ref and the unit capacitance Q _S of the capacitor or reactor of the next operation, during the period when the load increases (for example, from 6:30 to 11:30 minutes, 12:30 to 19:00, etc.), the reactive power Q increases on the delayed side, so Q
Set the calculation by _pp = Q _ref + Q _s /2 and calculate the time period when the load is reduced (for example, 0:00 to 6:30, 11:30 to 12:30
, etc.), it increases on the leading side, so Q _pp = Q
It is calculated and set to be _ref - Q _s /2, and is sent out when the reactive power Q exceeds these operating values Q _pp .

Next, its operation will be explained. First of all,
Close the switch 43A of the LR control panel (not shown) of LRTT ₁ , T ₂ , T ₃ , and T ₄ to the "auto" side,
Switch the changeover switch 43VQC to the "use" side,
Furthermore, the changeover switches 43A (not shown) of the SC control circuit 11 and ShR control circuit 12 are closed to the "auto" side. As a result, a relay 43 (not shown)
ASC, 43AShR is energized and its normally open contact 43
ASC _a and 43AShR _a are closed.

In this state, as shown in FIG. 6, the bus voltage V _B
is controlled so that V _EL < V _B < V _EH . this is
Over-fall detection value V read out from RAM 8 from bus voltage V _B read by CPU 6 via voltage converter 3
If it is compared with _EL and continues for a certain period of time (for example, 2 seconds) based on the relationship of V _B V _EL , voltage over-drop operation 101
Do this. This is done by checking the input reactors, for example ShR ₁ and ShR ₂ , and energizing the relay ShR _1T of the ShR control circuit 12, as shown in FIG. The circuit breakers CB ₂₁ and CB ₂₂ are sequentially disconnected, and then the capacitors that have been tripped, such as SC ₁ and SC ₂ , are checked, and the relay SC _1C of the SC control circuit 11 is energized to disconnect them. Insert containers CB ₁₁ and CB ₁₂ in sequence,
This is done by once increasing the bus voltage V _B until the relationship of V _B > V _ref - δ is established. At this time, if both the reactor that was turned on and the capacitor that was tripped are not present,
After confirming that the tap positions of LRTT ₁ , T ₂ , T ₃ , and T ₄ are not at the lower limit (maximum output voltage),
Energize relay _90R1 of LR control circuit 10,
Operate the tap switch to the boost side to temporarily boost the bus voltage V _B as described above. Next, the bus voltage V _B
is compared with the _over -rise detection value V _EH read out from RAM 8, and determined for a certain period of time ( _for example, 1
seconds), the voltage over-increase operation 102 is performed. This is done by checking the input capacitors, such as SC ₁ and SC _2, and energizing the relay SC _1T of the SC control circuit 11, as shown in FIG. Shishiya disconnector CB ₁₁ ,
Shut off CB ₁₂ one after another, then check the tripped reactors, such as ShR ₁ and ShR ₂ , and energize relay ShR _1C of ShR control circuit 12 to disconnect them.
By sequentially turning on CB ₂₁ and CB ₂₂ , the bus voltage V _B is reduced to V
The voltage is once lowered until the relationship _B < V _ref + δ is established. At this time, if there is no capacitor inserted or reactor tripped, LRTT ₁ ,
After confirming that the tap positions of T ₂ , T ₃ , and T ₄ are not at the upper limit (minimum output voltage), the relay 90L ₁ of the LR control circuit 10 is energized to operate the tap switching to the buck side. As described above, the bus voltage V _B is once lowered.

In this way, when the bus voltage V _B exceeds the preset over-rise or over-fall detection value, the bus voltage V _B is immediately adjusted to V _ref ±δ by operating the capacitor and reactor, regardless of the reactive power. The bus voltage V _B is controlled by raising and lowering the voltage until the voltage falls within the range.

Next, the reactive power Q is controlled to have a relationship of Q _EH >Q > Q _EL . This is determined by the reactive power Q read by the CPU 6 via the reactive power converter 2, the delayed excessive detection value Q _EH of the reactive power read from the RAM 8, and the advanced excessive detection value Q _EL , respectively, so that Q>Q _EH・Q < _QEL
If the relationship Q>Q _EH continues for a certain period of time (for example, 3 seconds), an excessive delay operation is performed. This means that the bus voltage V _B is V _ref > V _B > V _ref −δ
After confirming that there _{is a} relationship _between CB ₂₁ and CB ₂₂ are sequentially cut off, and then the capacitors are tripped, e.g.
The relay SC _1C of the SC control circuit 11 of SC ₁ and SC ₂ is energized to sequentially turn on the shield breakers CB ₁₁ and CB ₁₂ , and the reactive power Q is adjusted to the advance side until the relationship Q<Q _EH is satisfied. Let's do it. At this time, the bus voltage V _B is V _ref > V
When there is no relationship of _B > V _ref −δ, LR control circuit 1
0 relay 90L ₁ is excited and LRTT ₁ , T ₂ , T ₃ ,
After switching the _T4 tap to the buck side and adjusting the bus voltage V _B to the above relationship, perform the advance side adjustment. Further, if the reactive power Q continues for a certain period of time (for example, 3 seconds) in the relationship Q< _QEL , an excessive advance operation is performed. This means that the bus voltage V _B is V _ref < V _B < V _ref +
After confirming that there is a relationship of δ, the capacitors, for example SC ₁ and SC ₂ ,
Excite relay SC _1T of control circuit 11 and disconnect it.
ShR control circuit 1 of reactors such as SnR ₁ and ShR ₂ in which CB ₁₁ and CB ₁₂ are sequentially cut off and then tripped.
2 relay ShR _1C is energized and the breaker CB ₂₁ , CB ₂₂
are turned on one after another, and the reactive power Q is adjusted to the lag side until the relationship Q> _QEL is established. At this time, if the bus voltage V _B is not in the relationship V _ref < V _B < V _ref + δ, the relay 90R ₁ of the LR control circuit 10 is energized to boost the taps of LRTT ₁ , T ₂ , T ₃ , and T ₄ . After adjusting the bus voltage V _B to the above relationship, perform the delay side adjustment.

In this way, when it is predicted that the voltage change due to the operation of the capacitor or reactor will not exceed the dead zone based on the target voltage value, the reactive power can be adjusted without changing the taps of the transformer. control by the operation of

Next, normal operation 103 shown in FIG. 6 is performed.
As shown in FIG. 9, after determining whether the load is increasing or not, this is performed separately for the increasing load period and the decreasing load period.

First, the time period when the load increases will be explained.
This is the unit capacity Q of the next operation of the input reactor read out from RAM 8 after confirming the input reactor, for example ShR ₁ , ShR ₂ , by the control condition signal inputted by the CPU 6 through the input/output unit 9.
_S and the target value Q _ref set for interrupt calculation at fixed time intervals (for example, every 0.5 seconds) to calculate the operating value Q _pp as Q _pp =
The calculation is set as Q _ref +Q _s /2, and if the reactive power Q has a relationship of Q > Q _pp with respect to this operating value Q _pp (Q is on the lagging side of Q _pp ), the bus voltage V _B is V _B ＜ V _re
After confirming that there is a relationship of _f − δ, the reactor inserted above, for example, the ShR control circuit 12 of ShR ₁ , is
The relay ShR ₁ is energized to cause the shingle breaker CB ₂₁ to break, and then the operating value Q _S is calculated and set in the same way for the reactor that has been turned on, for example ShR ₂ , so that Q>Q _p
After confirming the relationship of _p and V _B < V _ref - δ, the breaker CB ₂₂ is turned off and the reactive power Q is adjusted to the forward side until the relationship of Q < Q _pp is satisfied ( ShR trip processing). At this time, the bus voltage V _B is V _B <
When there is no relationship of V _ref −δ, the relay 90L ₁ of the LR control circuit 10 is excited and LRTT ₁ , T ₂ , T ₃ , T ₄
Switch the tap to the buck side to set the bus voltage V _B
Once the voltage is lowered to the relationship of V _B <V _ref - δ, the above adjustment on the advance side is performed. In addition, due to the tripping operation of the above-mentioned input reactor, the reactive power Q is reduced to Q<
If adjustment cannot be made to the relationship of _Qpp , check the tripped capacitors, e.g. SC ₁ and SC ₂ , and calculate and set the operating value _Qpp using the unit capacitance _Qs of the next-order operation as described above. ＞Q _pp and V _B ＜
If the relationship is V _ref −δ, the relay SC _1C of the SC control circuit 11 is energized to sequentially close the sheath breakers CB ₁₁ and CB ₁₂ to perform advance side adjustment (SC closing process).

Adjustment of the advancing side of the reactive power Q by tripping the reactor that has been turned on and turning on the capacitor that has been tripped is performed by setting the bus voltage V _B in a relationship such that V _B <V _ref −δ (that is, once adjusting the voltage change in the direction of cancellation). ), so even if the bus voltage V _B rises, the target value V _r
This will be done to keep the voltage change to _ef to a minimum.

After the advance side adjustment is performed, voltage adjustment operation 104 is performed. As shown in FIG. 10, this means that the bus voltage V _B read by the CPU 6 via the voltage converter 3 is equal to the target value V _ref and V _B >V _ref.
Alternatively, it is determined whether the relationship is V _B <V _ref , and if the relationship is V _B > V _ref and V _B > V _ref +δ, the bus voltage V _B is +W ₄ as shown in FIG.
Clock count the time that has passed in each region of ~+W ₁ and calculate the count CNT ₄ ~ _{CNT 1}
is stored in _the RAM _{8 ,} and the integral _{(W 4 ×} CNT ₄
+W ₃ ×CNT ₃ +W ₂ ×CNT ₂ +W ₁ ×CNT ₁ ) Determine whether this value has reached the constant K ₉₀ (if it is a period of severe load fluctuation, compare it with the shortened constant K ₉₀ ) ), when the constant K ₉₀ is reached, it is assumed that the time-up condition has been reached and the clock count stored in the RAM 8 is cleared, and the control condition signal input via the input/output section 9 causes LRTT ₁ ,
After confirming that the tap positions of T ₂ , T ₃ , and T ₄ have not reached the upper limit (minimum output voltage), the relay 90L ₁ of the LR control circuit 10 is energized and LRTT ₁ ,
_{The bus} voltage _V
The bus voltage V _B is controlled in a short period of time by continuously repeating it until _B meets the relationship V _ref < V _B < V _ref + δ. At this time, when the tap positions of LRTT ₁ , T ₂ , T ₃ , and T ₄ reach the upper limit, the bus voltage V _B is reduced to Step-down control is performed until the relationship of _ref < V _B < V _ref + δ is achieved (tap clogging process).
Further, if the read bus voltage V _B is in the relationship of V _B < V _ref and the relationship of V _B < V _ref - δ, the third
The number of counts of time falling in each area of -W ₄ to -W ₁ shown in the figure is integrated in the same way as above, and when this value reaches the constant K ₉₀ , it is determined that the time-up condition has been reached.
After clearing the count stored in RAM 8 and confirming that the tap position is not at the lower limit (the highest output voltage) by using the control condition signal input via the input/output section 9, Continuously repeat the adjustment (one-tap boosting process) by exciting the relay 90R1 of the control circuit ₁₀ to switch the tap by one tap to the boosting side until the relationship of V _ref > V _B > V _ref - δ is reached. Control the bus voltage _VB .
At this time, when the tap position reaches the lower limit, the bus voltage V _B is boosted until the relationship of V _ref > V _B > _ref - δ is achieved by tripping the input reactor and closing the tripped capacitor ( Tap jam removal).

Next, a time period in which the load decreases will be explained. As shown in FIG. 9, after the CPU 6 confirms the input capacitor based on the control condition signal input via the input/output section 9, the RAM 8
For example, the operating value Q pp is calculated and set using the unit capacitance Q _s of SC ₁ and the target value Q _ref as _{Q pp =} Q _ref −Q _s /2, and this operating value Q For _pp , the reactive power Q is the relationship of Q<Q _pp (Q
is on the leading side of _Qpp ), then the bus voltage V
After confirming that _B is in the relationship V>V _ref + δ, excite the capacitor inserted above, for example, the relay SC _1T of the SC control circuit 11 of SC ₁ , and then disconnect it.
CB ₁₁ is turned off, and then the capacitor, for example SC ₂ , is turned on, and the operation value Q _pp is calculated and set in the same way as above.
After confirming the relationship of Q < Q _pp and V _B > V _ref + δ, the circuit breaker CB ₂₂ is disconnected,
The reactive power Q is adjusted to the delay side until the relationship Q>Q _pp (SC tripping process). At this time, the bus voltage V
When _B is not in the relationship of V _B > V _ref + δ, the relay _90R1 of the LR control circuit 10 is energized and the tap is switched to the boost side, so that the bus voltage V _B becomes V _B > V _ref
After the voltage is once increased to a relationship of +δ, the delay side adjustment is performed. In addition, if the reactive power Q cannot be adjusted to the relationship Q>Q _pp by tripping the input capacitor, the tripped reactor, for example ShR ₁ ,
After confirming ShR ₂ , calculate and set the operating value Q _pp using the unit capacity Q _s of the next operation and the target value Q _ref as described above, and set the reactive power Q with respect to this operating value Q _pp
If the relationship is _pp and V _B > V _ref + δ, then
The delay side adjustment is performed by exciting the relay ShR _1C of the ShR control circuit 12 and sequentially closing the shear circuit breakers CB ₂₁ and CB ₂₂ (ShR closing process).

The delayed side adjustment of the reactive power Q by tripping the capacitor that has been turned on and turning on the tripped reactor is performed with the bus voltage V _B in the relationship V _B > V _rer + δ. The voltage change caused by the application is kept to a minimum with respect to the target value V _ref .

After the reactive power Q has been adjusted on the delayed side, voltage adjustment operation 104 is performed. This is the voltage adjustment operation 1 during the time when the load increases as described above.
Since it is the same as 04, the explanation will be omitted.

When the normal operation 103 is completed, the operation is performed again according to the flowchart shown in FIG.

According to the present invention, when the bus voltage exceeds the over-drop or over-rise detection value, it is immediately adjusted by turning on or tripping the capacitor or reactor, regardless of the reactive power. Voltage control can be performed quickly without exceeding the operating time limit of the voltage adjustment relay, and the LRT tap switching operation during voltage control is performed continuously and repeatedly based on the target value, which is different from conventional As a result, the voltage regulating relay does not require an operating time limit for each tap change, and the voltage control section that follows changes in the bus voltage can be performed in a short time. In addition, when an LRT tap becomes ``tap jammed,'' voltage control is performed by turning on or tripping a capacitor or reactor. This does not occur at all, and voltage control can be performed by expanding the adjustment range of the LRT output voltage. Furthermore, since reactive power is controlled using operating values that take into account the individual capacitances of capacitors and reactors that are operated next, it is possible to perform effective control that follows fluctuations in reactive power. This is done after switching the LRT tap in the direction of canceling the change in bus voltage caused by turning on or tripping the capacitor or reactor, so it is not necessary to turn on or trip the capacitor or reactor as before. There is no need to unnecessarily increase the number of LRT tap switching operations, and the bus voltage can be controlled while maintaining it at an appropriate value. Moreover, when controlling reactive power, the capacitor and reactor turning on and tripping are restricted depending on the time period when the load increases and the time period when the load decreases. It is possible to perform appropriate control and minimize the frequency of opening/closing of disconnectors, prioritize voltage adjustment, maintain and improve appropriate voltage, and reduce power transmission losses, thereby providing benefits to consumers. It has remarkable effects, such as being able to perform voltage and reactive power control that further improves services by coordinating with LRT, capacitors, and reactor phase adjustment equipment.

[Brief explanation of the drawing]

Fig. 1 is a block diagram showing an embodiment of the present invention, Fig. 2 is a circuit diagram of the LR control circuit provided in the first input/output section, Fig. 3 is an explanatory diagram showing the time characteristic of voltage regulation, and Fig. 4 5 and 5 are circuit diagrams of the SC control circuit and ShR control circuit provided in the input/output section of FIG.
Figure 7 is a flowchart explaining the main control operation.
6 is a flowchart for explaining the voltage over-drop operation in FIG. 6, FIG. 8 is a flow chart for explaining the voltage over-rise operation in FIG. 6, and FIG. 9 is a flow chart for explaining the normal operation in FIG. 6. FIG. 10 is a flowchart illustrating the voltage adjustment operation of FIG. 9. 1: Current converter, 2: Reactive power converter, 3: Voltage converter, 6: Arithmetic processing unit, 7, 8: Storage unit,
9: Input/output section, 10: LR control circuit, 11: SC control circuit, 12: ShR control circuit, A: control device,
T ₁ , T ₂ , T ₃ , T ₄ : Tap-change transformer on load,
SC ₁ , SC ₂ ... SC _o : Power capacitor, ShR ₁ ,
ShR ₂ ...ShR _n : Shunt reactor, CB ₁₁ , CB ₁₂ ...
...CB _1o , CB ₂₁ , CB ₂₂ ...CB _2n : Shiya breaker.

Claims (1)

[Claims] 1. A plurality of on-load tap switching transformers, and a bank 2.
A control device is equipped with a plurality of power capacitors and shunt reactors connected to the secondary bus, and inputs the load current and bus voltage of the transformer. In a control method that adjusts the voltage and reactive power by turning on and tripping, when the bus voltage exceeds a preset over-rise or over-fall detection value, the power capacitor, The voltage is adjusted by sending an operation command to the shunt reactor, and the reactive power is adjusted using the power capacitor.
When it is predicted that the voltage change due to the operation of the shunt reactor will not exceed the dead band based on the voltage target value, an operation command is sent to the power capacitor and the shunt reactor to control the power capacitor and the shunt reactor without performing tap switching of the transformer. A voltage and reactive power control method characterized by: 2. The voltage and reactive power control system according to claim 1, wherein when the transformer taps are clogged, the voltage is adjusted by operating commands to the power capacitor and the shunt reactor.