JPS6151269A - Data processing device - Google Patents

Abstract

PURPOSE:To set a bit reverse reading processing part to a vector and to process data with high speed which needs to replace data by installing a bit replacing means and a shift means of the vector data. CONSTITUTION:A register (REG)A is a register which stores data d0, d1...dm-1 of an (m) bit composition read from a vector register by a data line 300. An inverting circuit BRV is an inverting data output part which outputs one lower level bit o REGA, namely, data bm-1,...bm-l+1, bm-l by inverting a bit storing posi tion from dm-1 to dm-l. Composite data of a m bit from data b0 to bm-1 becomes input data of a shifter SFT and 0 or 1 of a constant C is forcibly inputted from b0 to bm-l+1. These data are shifted from right to left by the shifter SFT, by indication of a shift mode MOD, (m) bit data up to data k0-Km-1 are stored in REGB, and are sent through a data line 600 to the vector register.

Description

[Detailed description of the invention]

[Industrial Application Field] The present invention relates to a data processing device that processes vector data. [Prior Art] As the application fields of computers expand. The demand for high-speed computer processing is expanding without limit. Supercomputers have been particularly actively developed in recent years to meet such demands in the science and technology fields. In general, many supercomputers achieve high speed by having a vector processing device that processes huge amounts of vector data in a pipeline. By the way, fast Fourier transform (F
FT). FFT is applied to fields such as science, engineering, social science, analysis of boundary value problems of partial differential equations, 7 vector analysis of various signals such as audio signals, seismic waves, brain, wave, and economic fluctuation data. , With the recent advent of high-speed vector processing devices, there are a number of new features: 1. FFT
Research on algorithms is also gaining momentum. FFT
The algorithm was developed by C! in 1'965. ooley and Tu
Paper on FFT by key” An Algor
Ithm for the Machil, e Ca1c
ulation of I:! complex four
-ier 5eries', Math, C! om
Various algorithms have been proposed since the publication of ``Put,'' 19+ 297-301 (1965'). One of the features of this type of FFT algorithm is that the data is bit-continuous (bit reversed) during the conversion process.
There will be cases where this is necessary. For example, if input data f (i) is Fourier transformed by the fast Fourier transform unit 900 and F (i) is the result, then FIG.
As shown in a) (8 data f(i) (i = 0
7), the input data f(i) may be left as is, but there are cases where bit reversal is required at the time of output. Furthermore, as shown in Section 26 (b), there are cases where input data f(1) is bit-reversed so that F(1) can be left as is at the time of output. Kuraguchi [Problems to be Solved by the Invention] Figure 3 shows an example of a program used in a conventional FFT, in which the part corresponding to step A in the program processes so-called consecutive bits of input data. This is the part where you are. When rearranging memory data based on bit continuity, bit continuity processing and shift processing are generally required when generating a memory address for the memory data based on the number of elements and data width of the target data. Conventionally, these processing parts have been considered difficult to vectorize, and therefore have been performed using scalar operations. Therefore, when the amount of input data is large, the time required for these processes is large. This has the disadvantage that the execution performance of FFT is significantly reduced. An object of the present invention is to eliminate the above-mentioned drawbacks by providing a bit swapping means and a shifting means for vector data, and to enable vectorization of bit contiguous processing parts, thereby enabling high-speed data processing that requires data swapping processing. The objective is to provide a data processing device that achieves [Means for Solving the Problems] According to the present invention, data processing is provided that includes a plurality of vector registers that hold vector data consisting of a plurality of elements, and processes vector data sequentially taken out from the Peltle registers. In the apparatus, one of the vector registers
For vector element data of m bits (m≧2) sequentially extracted from data, one bit (1≦
m), an inverting means for inverting the bit storage position and outputting it; a constant outputting means for outputting a predetermined constant for the remaining (m-1) bits; and output constant data of the constant outputting means. holding means for holding a shift mode that defines a shift operation for the composite data of and the data generated by the inverting means and for holding a shift number; and a shift operation means for shifting the composite data by the holding means. A data processing device is obtained which is characterized by having the following features. DESCRIPTION OF THE PREFERRED EMBODIMENTS [Embodiments] Next, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a diagram showing a data processing apparatus according to a first embodiment of the present invention. In the first cause. 10 and 20 are vector registers each holding vector data consisting of a plurality of elements; 30 is a selection circuit for selecting subsequent data from one of the vector registers 10 and 20; and 40 is a selection circuit for selecting successive data from one of the vector registers 10 and 20. A selection circuit 50 selects write data, and 50 decodes the command and controls read/write to the vector register. A control circuit that instructs the selection circuit 50, 40 to select, and instructs the functional circuit 60 to start operation, etc., and 60 is a feature of the present invention that performs bit swapping, which will be described later, on data selected by the selection circuit 30. It is a functional circuit that Normally, several functional circuits are connected in parallel under the 9 selection circuit 30. The flow of normal vector processing will be briefly explained using FIG. First, prior to calculation, vector data is read from a memory (not shown) and loaded into a vector register by the number of row elements. In this case, the data read from the memory is sent to the present data processing device via the data line 700. The control circuit 50 decodes the command word, selects the data line 700 in the selection circuit 40 using the 2 selection line SL1, and the selected data 401 or 402 is 2. Write instruction line WE1 or WB2 for specified vector register 10 or 20
and is written to the vector register specified by write address WA1 or WA2. Next, the loaded vector data is transferred to the data line 100 or 20 by the read address R'A I or RA2.
0 on the selection line SL2 in the 2 selection circuit 30.
one of them is selected and sent out sequentially to the functional circuit 60 via the data line 600. Functional circuit 60 executes arithmetic operations on the sent data in response to operation instruction line MOD, and sequentially sends the results to the vector register via data line 600. The vector register is set to the write address WA1 according to instructions from the vector control unit 50.
Alternatively, the calculation results are sequentially written into the area specified by Wi2. Further, when storing the calculation result in the memory, data is read from the vector register using the read address RA1 or RA2, and sent to the memory section via the data line 701. FIG. 4 shows the functional circuit 60 of the first cause. The functional circuit 60 includes a register REGA that stores input vector data having a 1 m bit configuration, and an inversion circuit BRV that extracts 1 bit from the register REGA, inverts the storage position, and outputs the data. A shifter circuit SFT that receives the inverted and output data and a constant for (m-1) focus portions, a flip-flop MR that holds a shift mode for the shifter SFT, and a shift number for the shifter SFT. It is composed of a register BCR that stores the output data of the shifter SFT, and a register REGB that stores the output data of the shifter SFT. Figure 5 shows the fourth factor, the inverting circuit BRV and the shifter circuit SFT.
FIG. 3 is a diagram illustrating a specific circuit example of a portion including. REG
'A is m-bit data dO+dl+d2 read from the vector register via the data line 300
+・・・・dm 1+ dm 1+1 +・・・・
.... This is a register that stores am-1. BRV is REG
The lower 1 bit of A, that is, the data (im-'1 to a, +
5. Invert the bit storage positions for the two pairs. data bml+b
m-1+1. ...This is an inverted data output section that outputs bm-1. The m-bit composite data from data bO to 1)m-1 becomes the input data of the shifter circuit SFT, and at this time, from bo to 1)m-1-1 is a predetermined constant C (C=O or 1). ) is forcibly entered. Details of such a bit combining section are shown in Table 1. Table 1 That is, input the constant C from bit bo to 1) m-1-1, and input the data of RE()A from +bm-1 to bl-1 dm-1+ dm-2+ """+ dm- 1-
Input H+ dm-1. The above data is then processed by thick circuit SFT. Shifted to the right/left. For thick circuit SFT,
Each flip-flop MR and SCR are connected via a shift mode line M and a shift number instruction line SFC, and data kO to k shifted by these instruction lines are connected. −
Data of m bits up to 1 is stored in register REGB and sent to the vector register via data line 600. As an example, Table 2 is a diagram showing the circuit operation of FIG. 5 when m=8.1=4, and the effective shift number is from O to 4 bits (left shift when 1M-0), M When =1, a right shift is performed. In addition, in the case of left shift, it is assumed that ``0'' is inserted in the vacant position. In Figure 5 and Table 2, the 7 generation circuit is shown for kO ~ when C = '0. In the figure, tO to t7 is a signal obtained by decoding the number of shifts 870 in Table 2 by decoder D. For example, 5yc
If =o, then to=1, and if 5FC=4, then t4=1. Further, G1 represents an AND gate, and G2 represents an OR gate. Next, using the data processing device of the first cause. A specific example of a vector data interchange operation often used in FFT and the like will be explained with reference to FIG. The reference address MA is stored in the memory 70 shown in FIG. 6(a).
2ω byte width (ω≧0) data f(0) sequentially from
f(1),..., f(i) are stored, and F
A case will be described in which input data is exchanged as shown in FIG. 2(b) in the FT process using a 1-bit inversion circuit BRV. In this case, the number of effective bits of element number 1 is p
Then, shift mode M and shift number SFC are defined as follows. - For example 1i=71 ω-: 2+ 1-4+ p-
Case 3 is shown in FIG. First, as in Section 6e(b),
Pointer 1 (effective number of bits: 6) is sequentially loaded into the vector register 10. Next, the vector data of the vector register 10, ie, the pointer 1, is sent via the selection circuit 30 to the functional circuit 60 having an inversion circuit with a shifter. Since the data width of f(1) is 4 bytes, 1-p-1
, ω-2, and the shift mode MR at this time is 0”,
Set "001" in F2O,H. The bit inversion circuit with thick (the part including BRV and SFT in Figure 4) converts the lower 4 bits of the 32-bit data (including pointer 1) stored in REGA. The bits are inverted and a constant "0" is output for the upper 28 bits, and the combined data is shifted by one pin point to the left by the shift circuit SFT and stored in the register REGB (fourth factor). , the contents of the vector register 10 are converted as follows.

[0] Chi24.00000000 (0) →

[0]■2
4.00000000 (0)

[0] Chi 24.0000
0001 (1) → [0:], X-24,00010
000 (16)

[0] Tsunai 24.00000010 (
2)→

[0] Chi24.00001000 (8)

[0]
Chi24.00000011 (3)→

[0] Kaoru 24.0
0011000 (24)

[0] Meal 24.0000 [
1100 (4) →

[0] Chi24.00000100 <
4)

[0] Dinner 24.00000101 (5) → [
0] Child 24.00010100 (20)

[0] Ao24
．． 000001.10 (6)→

[0] Koku 24,000
11000 (12)

[0] Straw 24.00000111
(7) →

[0] Straw 24. [I[]01111]Cl
(28) (Note) [0': l*n...indicates that the data for one bin of n are all "0°'. These data are sequentially passed through the selection circuit as shown in Figure 6 (C). 4
0 is stored in the vector register 10. Next, eight elements of the reference address MA on the memory 70 are sequentially stored in the vector register 20. After that, the contents of the vector register 10 and the contents of the vector register 20 are read out for each element, and an adder circuit (not particularly shown) performs an operation, and the result is transferred to the vector register 20 as shown in FIG. 6(d).
,Store. At this point, each element data in the vector register 20 indicates the memory address of the vector data f(1) on the memory. Therefore, the contents of the vector register 20 are sequentially taken out in the fifth step, and the retrieved data are read out sequentially from the memory; ). Letting the data stored at memory address j be M (j), as can be seen from the sixth factor. M(MA + [1) → f(0n, M(M
A +1(S) → f(4nM(MA+8) →f
(2), M(MA+24)→f(6)M(MA+4
)→f(1), M'(MA+20)→f(5nM(
MA+12) → f(3), M(MA+28) → f(
7), and the vector register 10 sequentially stores f(0)
. f(4), f(2), f(6), f(1)
, f(5), f(3), f(7). In other words, the replaced data is stored. In addition, when bit-reversing the output of FFT converted data as shown in Figure 2 (A-2), an address calculation is performed using the same inverting circuit with thick as described above, and the address is stored in the vector register 1o. FFT result F
(0), F (1), ... River F (6),
? (7) may be sequentially stored in the contents of the vector register 20, that is, on the memory addresses. That is, it is stored in memory as shown below. M(MA+ 0)←F([1), M(MA+ 4)
←F(4)M(MA+8)←F(2), M(M
A+ 12)←F(6)M(MA+16)4-F(1)
, M(MA+20)4-F(5)MCMA+24)
←F(3), M (MA + 28)←F(7)
Furthermore, FIG. 7 shows a functional circuit 60 of a data processing apparatus according to a second embodiment of the present invention, which has the same effects as the embodiment described in Section 2. In the circuit shown in FIG. 7, the connection between the inverting circuit BRV and the shift circuit SFT is reversed to that in the circuit shown in FIG. 4. That is, m-bit data do, d1 . ...The shift circuit 13FT performs a shift operation specified by shift mode M and shift number SFC for dm-1. Next shifted data kOrk
j...km-1,...+km The lower 1 bit of I is input to the inversion circuit BRV. The output bm-1+, bm-1 of the inverting circuit BRV contains data r km Sr km- whose bit storage pupil is inverted.
2+...km-141+km 1 is output, and at this time, the upper (m-1) focus, that is, bO+b++・
...+bm (constant C (O or 1) for -+
is constantly output and the 8 combined data is stored in register REG.
It is stored in B. [Effects of the Invention] As explained above, the present invention has the effect that the inverting circuit with thick enables the processing of continuous pits to be vectorized and speeds up the processing of exchanging data on the memory. This can be an effective means of high-speed data processing.

[Brief explanation of drawings]

The first factor is block factor 1 which shows the data processing device according to the first embodiment of the present invention. 2(2) is a block diagram showing data exchange during fast Fourier transform, FIG. 3 is a diagram showing an example of a conventional fast Fourier transform program, and the fourth factor is the functional circuit 60 of the first factor. A block diagram showing an example, the fifth part is a circuit diagram of a portion including the inversion circuit BRV and shifter circuit SFT in FIG. Figure 7 (8) is a block diagram showing a functional circuit 60 of a data processing device according to a second embodiment of the present invention. 10.20... Vector register, 30.40...
Sorting circuit, 50... control circuit, 60... functional circuit. REGA, RKGB, SC! R...Register, M
R...flip-flop, G1...logical product)
, G2...OR gate, D...decoder. Agent (7127) Patent attorney Yosuke Goto:) 60 functional circuit ND Fig. 6 (α) MA Sumitsubo address f(0) to f(7): Kogutle data (e) Kori Torrezusta (1ω

Claims (1)

[Claims] 1. In a data processing device that includes a plurality of vector registers holding vector data consisting of a plurality of elements and processes vector data sequentially taken out from the vector registers, one of the vector registers Extract 1 bit (1≦m) of the m-bit (m≧2) vector element data sequentially extracted from the data,
Inverting means for inverting and outputting the bit storage position, and the remaining bit storage position (
m-1) For bits, a constant output means for outputting a predetermined constant, and a shift operation for converting the output constant data of the constant output means and the data generated by the inversion means into composite data are defined. A data processing device comprising: holding means for holding a shift mode and a shift number; and shift operation means for shifting the composite data using the holding means. 2. In a data processing device that includes a plurality of vector registers holding vector data consisting of a plurality of elements and processes vector data sequentially taken out from the vector registers, m bits sequentially taken out from one of the vector registers. (m≧2) retains a shift mode that defines a shift operation for vector element data of the configuration;
and a holding means for holding a shift number, a shift operation means for shifting the vector element data by the holding means, and one bit (1≦m) of the m-bit shift data generated by the shift operation means. A data processing device comprising: inverting means for inverting and outputting a bit storage position; and constant output means for outputting a predetermined constant for the remaining (m-1) bits.