JPS6150395A - Method of producing ceramic multilayer circuit board - Google Patents

Method of producing ceramic multilayer circuit board

Info

Publication number
JPS6150395A
JPS6150395A JP17267484A JP17267484A JPS6150395A JP S6150395 A JPS6150395 A JP S6150395A JP 17267484 A JP17267484 A JP 17267484A JP 17267484 A JP17267484 A JP 17267484A JP S6150395 A JPS6150395 A JP S6150395A
Authority
JP
Japan
Prior art keywords
weight
multilayer circuit
circuit board
ceramic
ceramic multilayer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP17267484A
Other languages
Japanese (ja)
Inventor
章三 山名
上山 守
秀次 桑島
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Resonac Corp
Original Assignee
Hitachi Chemical Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Chemical Co Ltd filed Critical Hitachi Chemical Co Ltd
Priority to JP17267484A priority Critical patent/JPS6150395A/en
Publication of JPS6150395A publication Critical patent/JPS6150395A/en
Pending legal-status Critical Current

Links

Landscapes

  • Non-Metallic Protective Coatings For Printed Circuits (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【発明の詳細な説明】 (産業上の利用分野) 本発明はセラミック多層回路基板の製造法に関する。[Detailed description of the invention] (Industrial application field) The present invention relates to a method of manufacturing a ceramic multilayer circuit board.

(従来の技術) 従来セラミック多層回路基板は、予め焼結されたセラミ
ック基板上に導体ペーストを印刷後、絶縁ペーストを印
刷し、これを複数回く9返して多層回路を形成した後、
焼成して製造していた。
(Prior Art) Conventional ceramic multilayer circuit boards are manufactured by printing a conductive paste on a pre-sintered ceramic substrate, printing an insulating paste on it, repeating it multiple times to form a multilayer circuit, and then
It was manufactured by firing.

(発明が解決しようとする問題点) しかしながらこの方法によると予め焼結されたセラミッ
ク基板の熱膨張率と絶縁ペーストの焼成収84率とが異
なるため絶縁層の剥離やクラックが発生する欠点があっ
た。
(Problems to be Solved by the Invention) However, this method has the disadvantage that the thermal expansion coefficient of the pre-sintered ceramic substrate is different from the firing yield of the insulating paste, which causes peeling and cracking of the insulating layer. Ta.

この欠点を補うためセラミックグリーンノートる方法が
試みられたが、この方法でも導体回路上の絶縁層が焼結
される際に剥離したりクランクが発生するという欠点が
あった。
A method called Ceramic Green Note was attempted to compensate for this drawback, but this method also had the drawback of peeling and cranking when the insulating layer on the conductor circuit was sintered.

本発明はかかる欠点のないセラミック多層回路基板の製
造法を提供することを目的とするものである。
The object of the present invention is to provide a method for manufacturing a ceramic multilayer circuit board free of such drawbacks.

(問題点を解決するための手段) 本発明者らは絶縁層の剥離や絶縁層に発生するクラック
は絶縁層の焼成収縮、耐熱衝撃性、耐薬品性に起因する
ことに着目し1種々検討を行なった結果、従来使用して
いた絶縁ペーストに代えて絶縁ペーストを構成するセラ
ミック質粉体中にジルコニアを5〜30重i%およびフ
ラックスを35〜6.0重量%含有させたところ、導体
回路上の絶縁層の剥離やクラックの発生のないセラミッ
ク多層回路基板が製造できることを見い出した。
(Means for solving the problem) The present inventors focused on the fact that peeling of the insulating layer and cracks that occur in the insulating layer are caused by firing shrinkage, thermal shock resistance, and chemical resistance of the insulating layer, and conducted various studies. As a result, when the ceramic powder constituting the insulating paste contained 5 to 30% by weight of zirconia and 35 to 6.0% by weight of flux in place of the conventionally used insulating paste, it was found that the conductor It has been discovered that a ceramic multilayer circuit board can be manufactured without peeling or cracking of the insulating layer on the circuit.

本発明は導体ペーストとセラミック質の絶縁ペーストと
をグリーンシート上に複数回印刷し、同時焼成してセラ
ミック多層回路基板を製造する方法において、絶縁ペー
ストを構成するセラミック質粉体中にジルコニアを5〜
30重量%およびフラックスを3.5〜6.0重量%含
有するセラミック多層回路基板の製造法に関する。
The present invention is a method of manufacturing a ceramic multilayer circuit board by printing a conductive paste and a ceramic insulating paste multiple times on a green sheet and firing them simultaneously, in which zirconia is added to the ceramic powder constituting the insulating paste. ~
The present invention relates to a method for manufacturing a ceramic multilayer circuit board containing 30% by weight and 3.5 to 6.0% by weight of flux.

本発明において使用されるセラミック質粉体の主成分と
しては特に制限はないが、アルミナを使用することが好
ましい。またジルコニアの粒径は何ら制限はないが、使
用するセラミック質粉体の主成分と同等またはそれよシ
小さい粒径のものを使用することが好ましい。さらに本
発明で使用されるグリーンシートは、厚さ、材質7など
何ら制’     Ia、、i7k < 、 4に−<
−、< l−O#* 、 EIJJla e 、!’に
ついても何ら制限はない。
The main component of the ceramic powder used in the present invention is not particularly limited, but it is preferable to use alumina. Although there is no restriction on the particle size of zirconia, it is preferable to use a particle size that is equal to or smaller than the main component of the ceramic powder used. Furthermore, the green sheet used in the present invention is subject to no restrictions such as thickness, material 7, etc.
−, <l−O#*, EIJJla e,! There are no restrictions on '.

本発明は絶縁ペーストを構成するセラミック質粉体中に
ジルコニアを5〜30重ZS、好ましくは10〜20重
侶°チ含有することが必要であり。
In the present invention, it is necessary to contain 5 to 30 ZS, preferably 10 to 20 ZS, of zirconia in the ceramic powder constituting the insulating paste.

5M量チ未満であると熱衝撃特性が悪くなC,a。If the amount is less than 5M, the thermal shock properties will be poor.

重量%超えると焼結温度が高くなシ高価となる。If it exceeds % by weight, the sintering temperature will be high and it will be expensive.

またスラックスはセラミック質粉体中に3.5〜6.0
重量チ、好捷しくけ40〜5.0重量%含有することが
必要であり、3.5重量%未満であると焼結性が悪くな
9.6.0重量%を超えると収縮率が変化し1機械的強
度、熱衝撃特性が悪くなる。
In addition, slack is 3.5 to 6.0 in ceramic powder.
It is necessary to contain 40 to 5.0% by weight of the weight, and if it is less than 3.5% by weight, the sinterability will be poor, and if it exceeds 9.6.0% by weight, the shrinkage rate will be low. 1 Mechanical strength and thermal shock properties deteriorate.

本発明におけるセラミック質粉体中には上記組成物の他
に必要に応じコープイライト、ムライト等の無機物が添
加される。
In addition to the above-mentioned composition, inorganic substances such as copierite and mullite may be added to the ceramic powder of the present invention, if necessary.

(実施例) 以下、実施例圧より本発明を説明する。(Example) The present invention will be explained below using examples.

実施例 平均粒径2μmの高純度アルミナ(アルミナ純1i99
.5%以上)96重量部にフラックス(タルク87.5
重量部とドロマイト115重量部との溶融物)を4重量
部添加し、均一に混合して原料粉とし、た。
Example High purity alumina with an average particle size of 2 μm (alumina purity 1i99)
.. 5% or more) 96 parts by weight of flux (talc 87.5
4 parts by weight of a melt of 115 parts by weight of dolomite and 115 parts by weight of dolomite were added and mixed uniformly to obtain a raw material powder.

この原料粉1007JC景部にバインダーとしてポリビ
ニルブチラール樹脂8型破部+ ”]塑剤としてフタル
酸エステル4重量部、溶剤としてフリノール20重量部
およびトリクロルエチレン50重量部ヲ添加し、ボール
ミルにて50時間均一に混合してセラミックスリップと
した後、テープキャスティング法によシ厚さ0.8肛の
グリーンシートを得た。
4 parts by weight of phthalate ester as a plasticizer, 20 parts by weight of furinol and 50 parts by weight of trichlorethylene as a solvent were added to this raw material powder 1007JC as a binder, and then milled in a ball mill for 50 hours. After uniformly mixing to form a ceramic slip, a green sheet with a thickness of 0.8 mm was obtained by tape casting.

上記とは別に平均粒径2μmの高純度アルミナ(アルミ
ナ純度99.5−以上)に平均粒径1.8μmのジルコ
ニアと上記の7ラツクスを第1表に示す比率に配合し、
均一に混合してセラミック質粉体Nnl〜漸8を得た。
Separately from the above, zirconia with an average particle size of 1.8 μm and the above 7 lux are blended into high purity alumina (alumina purity 99.5- or higher) with an average particle size of 2 μm in the ratio shown in Table 1,
The mixture was uniformly mixed to obtain ceramic powder Nnl~8.

次にこのセラミック質粉体丸1〜l1k18 100重
量部にバインダーとしてポリビニルブチラール樹脂8重
量部、可塑剤としてフタル酸エステル4重量部および溶
剤としてテルピン油30重量部を添加し、らいかい機に
て5時間均一に混合して絶縁ペーストN111〜N11
8を得た。
Next, 8 parts by weight of polyvinyl butyral resin as a binder, 4 parts by weight of phthalate ester as a plasticizer, and 30 parts by weight of terpine oil as a solvent were added to 100 parts by weight of this ceramic powder round 1 to 11k18, and the mixture was processed in a sieving machine. Mix uniformly for 5 hours to make insulation paste N111~N11
I got 8.

次いで前述のグリーンシートに直径0.3 nunのス
ルーホールを形成した後、このスルーポールに市販のタ
ングステン(W)導体ペーストを充填し、さらにグリー
ン7−トの表、裏それぞれに前述と同じW導体ペースト
を印刷し回路を形成し、その上部に前述の絶縁ペースト
尚1〜尚8を70±1011mの厚さに印刷し、この工
程を表側4回、裏側4回繰り返し8層の多層回路を形成
し、さらにこの最外側にメタライズ端子を印刷した。そ
の後。
Next, after forming a through hole with a diameter of 0.3 nm in the green sheet, this through hole was filled with a commercially available tungsten (W) conductive paste, and the same W as described above was added to each of the front and back sides of the green sheet. A circuit is formed by printing conductive paste, and on top of that, the above-mentioned insulating pastes 1 to 8 are printed to a thickness of 70±1011 m, and this process is repeated 4 times on the front side and 4 times on the back side to form an 8-layer multilayer circuit. Then, a metallized terminal was printed on the outermost side. after that.

弱還元性雰囲気中で1500℃で1時間焼成して本発明
になるセラミック多層回路基板を得た。
The ceramic multilayer circuit board of the present invention was obtained by firing at 1500° C. for 1 hour in a weakly reducing atmosphere.

このセラミック多層回路基板について外観を観察した結
果、第2表に示す通シNch3〜尚6の絶縁ペーストを
用いて絶縁層を形成したものは絶縁層の剥離、クラック
の発生はなかった。
As a result of observing the external appearance of this ceramic multilayer circuit board, it was found that there was no peeling of the insulating layer or occurrence of cracks in those in which the insulating layer was formed using the insulating paste of Nch 3 to Nch 6 shown in Table 2.

また、このセラミック多層回路基板にリード端子を銀ロ
ーで接続した後、150℃で10分。
Also, after connecting lead terminals to this ceramic multilayer circuit board with silver solder, it was heated at 150°C for 10 minutes.

−195℃で10分の熱衝撃を10回繰り返し行なって
も絶縁層にクラックは発生しなかった。
No cracks occurred in the insulating layer even after repeated thermal shock for 10 minutes at -195°C 10 times.

これに対しNnlの絶縁ペーストを用いて絶縁層を形成
したものは焼成後にクランクが発生し、NQ2の絶縁ペ
ーストを用いて絶縁層を形成したものはリード端子銀ロ
ー付後にマイクロクラックが発生した。またぬ7および
N118の絶縁ペーストは1500℃の温度では焼結不
足であった。
On the other hand, in the case where the insulating layer was formed using the Nnl insulating paste, cracks occurred after firing, and in the case where the insulating layer was formed using the NQ2 insulating paste, microcracks occurred after the lead terminals were soldered with silver. The insulation pastes of Takinu 7 and N118 were insufficiently sintered at a temperature of 1500°C.

(発明の効果) 本発明は絶縁ペーストを構成するセラミック質粉体中に
ジルコニアを5〜30重量%およびフラックスを3.5
〜6.0重量%含有するので絶縁層の耐熱衝撃性が向上
し、導体回路上の絶縁層の剥離やクラックの発生のない
セラミック多層回路基板を製造することができる。
(Effects of the Invention) The present invention contains 5 to 30% by weight of zirconia and 3.5% of flux in the ceramic powder constituting the insulating paste.
Since the content is 6.0% by weight, the thermal shock resistance of the insulating layer is improved, and a ceramic multilayer circuit board can be manufactured without peeling or cracking of the insulating layer on the conductor circuit.

Claims (1)

【特許請求の範囲】[Claims] 1、導体ペーストとセラミック質の絶縁ペーストとをセ
ラミックグリーンシート上に複数回印刷し、同時焼成し
てセラミック多層回路基板を製造する方法において、絶
縁ペーストを構成するセラミック質粉体中にジルコニア
を5〜30重量%およびフラックスを3.5〜6.0重
量%含有することを特徴とするセラミック多層回路基板
の製造法。
1. In a method of manufacturing a ceramic multilayer circuit board by printing a conductive paste and a ceramic insulating paste multiple times on a ceramic green sheet and firing them simultaneously, zirconia is added to the ceramic powder constituting the insulating paste. 30% by weight and 3.5 to 6.0% by weight of flux.
JP17267484A 1984-08-20 1984-08-20 Method of producing ceramic multilayer circuit board Pending JPS6150395A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP17267484A JPS6150395A (en) 1984-08-20 1984-08-20 Method of producing ceramic multilayer circuit board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP17267484A JPS6150395A (en) 1984-08-20 1984-08-20 Method of producing ceramic multilayer circuit board

Publications (1)

Publication Number Publication Date
JPS6150395A true JPS6150395A (en) 1986-03-12

Family

ID=15946264

Family Applications (1)

Application Number Title Priority Date Filing Date
JP17267484A Pending JPS6150395A (en) 1984-08-20 1984-08-20 Method of producing ceramic multilayer circuit board

Country Status (1)

Country Link
JP (1) JPS6150395A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0284795A (en) * 1988-09-21 1990-03-26 Nippon Denso Co Ltd Integrated circuit device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0284795A (en) * 1988-09-21 1990-03-26 Nippon Denso Co Ltd Integrated circuit device

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