JPS6150360B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a memory address control method, and in particular to obtaining address information of a memory to be accessed from (X, Y) coordinate values that indicate the XY coordinates of an image, such as when performing image processing. This invention relates to a memory address control method that enables

A device that reads and processes two-dimensional image information, such as OCR, stores this image information in a memory. In this case, the memory is normally accessed by continuous addresses as shown in FIG. 1 (FIG. 1 shows an example in which continuous addresses are assigned in byte units such as 0, 1, 2, etc.). However, in the case of image processing, it is very convenient to handle information in two-dimensional coordinates of X and Y. For example, when calculating the distance between areas A and B, such two-dimensional・It would be very convenient if data could be handled using the Y coordinate.

However, since the address of the memory 1 is continuous one-dimensional information as described above, conventionally, when X and Y coordinates are given, it is necessary to perform complicated calculations to calculate the address to be accessed.

Therefore, it is an object of the present invention to provide a memory address control system that can extremely easily determine an access destination designated by X and Y coordinates such as two-dimensional image data. For this reason, in the memory address control method of the present invention, in a data processing device that has a memory into which image information is input and processes this image information,
An X register into which the X coordinate value of the two-dimensional coordinates is input, a Y register into which the Y coordinate value of the two-dimensional coordinates is input, and a shift that shifts at least part of the address information input from the X register and the Y register. and selection instruction signal means for generating a selection instruction signal for the address conversion section, and controls the shifting means based on the selection instruction signal to convert at least part of the input address information. The present invention is characterized in that whether or not to shift is selectively controlled.

Before describing one embodiment of the present invention in detail, the operating principle of the present invention will be explained based on FIG. 2A. As shown in Figure 1, 32 bytes in the Y direction, that is, 0
In memory with Y addresses of ~255,
Point A (100,
30), input the binary number "01100100" of 100 into the X register 3,
Enter the binary number ``00011110'' of 30 into Y register 2. Then, as shown in Figure 2 A, the bottom 3
Shift the bits and set them in address register 4 (this means converting the Y direction bit address to a byte address). At this time, the upper three bits of address register 4 are filled with "0". ``0C83'' (hexadecimal) set in the address register 4 becomes the access destination address, and of the 8-bit data read by this address, what is indicated by the lower 3 bits ``110'' shifted as described above. , that is, the 7th bit is
This is the data for the point A (100, 30).

Of course, when processing image information, it is not only necessary to use two-dimensional coordinate data as described above, but also to store a dictionary in memory 1 or to have a work area, so it is not necessary to process image information as usual. It is often accessed using one-dimensional address information. Therefore, in such a case, it is necessary to set the data in the address register 4 as is without shifting, as shown in FIG. 2B.

In addition, when configuring the Y register 2 to directly indicate the Y-direction byte address calculated by a microprocessor, etc., as shown in FIG.
By outputting only the lower 5 bits as is from the Y register 2 and shifting the coordinate data set in the X register 3 by 3 bits to the lower order side, the byte address of the access destination can be obtained.

Next, one embodiment of the present invention will be described in detail based on FIGS. 3 and 4.

FIG. 3 shows the configuration of an embodiment of the present invention, and FIGS. 4A and 4B are examples of conversion circuits used in the address conversion section.

In the figure, the same reference numerals as the others indicate the same parts, 10 is an address translation processing device, 11 is a processor, 12
13 is a Y address input register, 14 is an X address input register, and 15 is a selection instruction register.

The address translation processing device 10 includes a processor 11
The address conversion unit 12, Y
It has an address input register 13, an X address input register 14, a selection instruction register 15, and the like.

The address conversion unit 12 shifts the entire address input to the Y address input register 13 and the X address input register 14 as shown in FIG.
Alternatively, it selectively converts and outputs so as to shift it partially, and its operating state is controlled by a selection instruction signal transmitted from the selection instruction register 15.

This address conversion unit 12 is configured, for example, in FIG.
A first address conversion circuit 16 and a second address conversion circuit 17 are provided as shown in FIG.

The first address conversion circuit 16 shown in FIG.
It selectively performs the operations shown in FIG. ,
It includes AND circuits 21-0 to 21-12, OR circuits 22-0 to 22-11, and the like.

In addition, the second address conversion circuit 1 shown in FIG.
Reference numeral 7 selectively performs the operations shown in FIG. 2 (b) and (c), and includes a Y input register 2-2, an 25-
10, AND circuits 26-0 to 26-7, OR circuits 27-0 to 27-7, etc.

(1) Next, the operation of the first address conversion circuit 16 shown in FIG. 4A will be explained.

When "1" transmitted from the selection instruction register 15 is inputted to the control signal input register 18, the inverter 19 outputs "0", turns off the AND circuits 20-0 to 20-15, and inputs the AND circuit instead. Circuits 21-0 to 21-
12 is turned on. Therefore, the signals of the 0th to 2nd lower three bits of the Y input register 2-1 input from the Y address input register 13 are not output, and the signals of the 4th to 7th bits are AND circuits 21-0 to 21-
OR circuit 22-0 to 22-4 via 4
is transmitted and output. The 0th to 7th bit signals of the X input register 3-1 transmitted from the 12 and output from these OR circuits. Then, the memory 1 is accessed by this address signal, and data is read/written.

However, when "0" is input to the control signal input register 18, the inverter 19 becomes "1".
is output, and the AND circuits 20-0 to 20-15 are turned on, but the AND circuits 21-0 to 21-
12 is turned off. As a result, Y input register 2-1 and X input register 3-1
The bit signals set to are outputted via AND circuits 20-0 to 20-15, respectively. When "1" is set in the control signal input register 18 in this way, the second
It can be controlled in the operating state shown in FIG. 2B, and when "0" is set, it can be controlled in the operating state shown in FIG.

(2) Further, the operation of the second address conversion circuit 17 shown in FIG. 4B will be explained.

Now, when "1" is input to the control signal input register 23, the interface 24 outputs "0",
AND circuits 25-0 to 25-10 are turned off, and AND circuits 26-0 to 26-7 are turned off instead.
turns on. Therefore, the fifth to seventh bit signals of the Y input register 2-2 are not output. The 0th to 7th bit signals of the X input register 3-2 are sent to the OR circuit 2 via AND circuits 26-0 to 26-7.
It is transmitted to 7-0 to 27-7 and output from these OR circuits.

However, when "0" is input to the control signal input register 23, the inverter 24 outputs "1" and the AND circuits 25-0 to 25-10 are turned on, and conversely, the AND circuits 26-0 to 26- 7
is in the off state. As a result, the bit signals set in the Y input register 2-2 and the X input register 3-2 are output as they are or via the AND circuits 25-0 to 25-10. In this way, when "1" is set in the control signal input register 23, control can be performed in the operating state shown in FIG. 2C, and when "0" is set, the operating state is shown in FIG. 2B. can be controlled with.

Therefore, the processor 11 outputs, for example, a bit conversion signal C, one bit of which selects the first address conversion circuit 16 or the second address conversion circuit 17, and the other bit selects the operating state as shown in FIG. The address conversion described above can be arbitrarily selected by instructing whether to enter the through state shown in FIG. 2 or the shift state shown in FIG. 2 A or C.

As explained above, according to the present invention, during data processing, the memory 1 can be accessed using X and Y coordinate information, or controlled using normal address information, or controlled using byte addresses. Especially when processing image information, data processing can be performed at extremely high speed.

[Brief explanation of the drawing]

Fig. 1 is an explanatory diagram of the memory when performing image processing, Fig. 2 is an explanatory diagram of the operating principle of the present invention, Fig. 3 is a configuration diagram of an embodiment of the present invention, and Fig. 4 A and B are diagrams of the present invention. This is an example of an address conversion circuit. In the figure, 1 is a memory, 10 is an address translation processing device, 11 is a processor, 12 is an address translation unit,
13 is a Y address input register, 14 is an X address input register, and 15 is a selection instruction register.

Claims (1)

[Claims] 1. In a data processing device that has a memory into which image information is input and processes this image information, 2.
an X register into which the X coordinate value of the dimensional coordinate is input;
a Y register into which a Y coordinate value of two-dimensional coordinates is input; an address converter comprising a shift means for shifting at least a part of address information input from the X register and the Y register; and selection for the address converter. It is characterized by comprising a selection instruction signal means for generating an instruction signal, and controlling the shifting means based on the selection instruction signal to selectively control whether or not to shift at least a part of the input address information. Memory address control method.