JPS6150256A - Recording and reproducing device - Google Patents

Abstract

PURPOSE:To obtain a recording and reproducing device which can correspond to plural Fs (sampling frequency) with a simple composition by installing a sampling circuit which samples a clock of a maximum frequency. CONSTITUTION:The PCM magnetic recording reproducing device corresponds to type 3 of Fs of f1-f3 (f1>f2>f3). A Fs designating signal from a switch 50 goes to (01), an output of a f1 detecting circuit 53 goes to (1) and a selector 48 supplys the output 43a of an OR gate 43 to a memory circuit 4. A sample fetched into a latch 22 by a latch clock 33b at time f1 is written in a memory during time f3-f4. Since time f3-f3 is period when a hatched part of a reading 29h is evaded, the sample can be written without shooting with other output. Thus, by setting the clock of the highest frequency of plural pcs of Fs, the device which can correspond to the plural pcs of Fs can be realized.

Description

[Detailed description of the invention] [Technical field of invention] The present invention relates to a recording/reproducing device, and more particularly.

The present invention relates to memory control of a PCM recording and reproducing device that is compatible with a plurality of sampling frequencies. In the following explanation, a two-head helical force scan type PCM magnetic recording/reproducing device will be taken as an example.

[Prior Art] FIG. 1 is a block diagram of a conventional two-head helical scan type PCM magnetic recording and reproducing device.
(1) is an input terminal, (2) is a low-pass filter, (3)
is an analog-digital conversion circuit (hereinafter referred to as AD conversion circuit), (0 is a memory circuit, (5) is an encoding circuit, (6 is
) is the modulation circuit, (7) is the changeover switch, (8),
(9) is a magnetic head, (1o) is a J exchange switch, (1
1) is a demodulation circuit, (12) is a memory circuit, (13) is a decoding circuit, (14) is a digital-analog conversion circuit (hereinafter referred to as DA conversion circuit), and (15) is! Low bass filter, (1B) is the output terminal, (1?)
shows a clock generation circuit that generates the system clock, which includes a low-pass filter (2) and an AD conversion circuit (3).
), memory circuit (4), encoding circuit (5), modulation circuit (
6) constitutes a recording system, including a demodulation circuit (It).

A reproduction system is composed of a memory circuit (12), a decoding circuit (+3), a DA conversion circuit (14), and a low-pass filter (15).

Next, we will explain the operation, starting with the recording system. The analog signal to be recorded is input from the input terminal (1), high frequency components are removed by the low-pass filter (2), and then the analog signal is converted into a digital signal at a sampling frequency fl (hereinafter referred to as Fs) by the AD conversion circuit (3). 7 (hereinafter referred to as samples) and stored in the memory in the memory circuit (4).

The encoding circuit (5) reads the samples stored in the memory, generates a check signal for error correction or error detection in units of samples generated in one unit time, and stores it in the memory.Encoding is completed. Then, the sample and check signal for one unit time are time-compressed and read out from the memory, and after being converted into a signal suitable for magnetic recording and reproduction in the modulation circuit (6), a changeover switch ( 7)
The information is recorded on the RJI tape by the magnetic head (8) or the magnetic head (9) via the magnetic head (8) or magnetic head (9).

Next, the operation of the reproduction system will be explained. Magnetic head (
8) and the magnetic head (8) are alternately supplied to the demodulation circuit (11) via a changeover switch (LO) that is switched at intermediate time intervals to generate the signal before f-modulation. The data is restored and stored in the memory in the memory circuit (12). The decoding circuit (13) sequentially reads the reproduced signals from the memory and performs error correction in units of reproduced signals of one unit time.The decoded samples in the memory are Tl (=l
/fl) and is read out at fixed time intervals, and the DA conversion circuit (
After being converted into an analog signal in step 14), high frequency components are removed in the next stage low-pass filter (15), and the signal is output from the output terminal (16).

Note that the lock necessary for the above signal processing is supplied from the clock generation circuit (17).

Next, the detailed operation of the recording system will be explained using FIG. 2 and FIG. 3, taking the case of Fs=f1 as an example. Second
The figure shows the memory circuit (4) and clock generation circuit (17) in Figure 1 in detail, so in Figure 1, (2
2) is a latch that takes in the sample output from the AD conversion circuit (3) and outputs the latched sample when the output control terminal C is "0"; (23) is divided into two areas A and B; The selected memory (24) has a selection signal of “0”.
A selector (2) outputs the output signal of the address generation circuit L (25) to the address input of the memory (23) when
5) is the aforementioned address generation circuit 1 that generates an address for writing the sample output from the latch (22) into the memory (23), and (27) is the address generation circuit 1 that generates the address for writing the sample output from the latch (22) into the memory (23)
(23a) is a signal pass line; (2B) is an address generation circuit that generates a memory address for extracting code 5 and record No. 41 to latch (27); (23a) is an address generation circuit 2. (2B) is a clock generation circuit 1 that generates a control clock (28a) for writing samples into the memory (23);
(2B) is the input clock (28c) of the address generation circuit 1 (25), the sample loading clock (28a) for loading the sample into the memory (23), and the latch clock (28b) of the latch (22). Output.
(29) is an address clock (29a) that is output to the address generation circuit 2 (2B).

A clock that generates the latch clock (29b) of the latch (27), the encoding clock (29c) input to the encoding circuit (5), and the write clock (29f) for storing the check signal in the memory (23). A generating circuit 2,
Clock generation circuit 1 (28) and clock generation circuit 2
(29), the output clocks are generated while maintaining a synchronous relationship with each other. (100) indicates an AND gate, the output of which is given to the tl clock input terminal WE of the memory (23). In FIG. 2, the lines with diagonal lines on the connections other than the pass line (23a) indicate a plurality of signal lines. Further, Φ to ■ indicate terminal numbers of the memory circuit (4).

Figure 3 shows a time chart, (28a),
(28b) are the sample writing 1 mentioned above, respectively.
°y') k5rl+') all, (2°d) ('
) 641a tfls If H% indicates a time range in which the input/output signal of the other circuit (5) and the recording signal taken into the latch (27) can exist on the pass line.

The signal output from the AD conversion circuit (3) with a period Tl (=l/f 1) is latched into the latch (22) at the rising edge of the latch clock (28b), and is latched to "0" of the sample write clock (28a). i() is stored in area A of the memory (23) during the period. At this time, selector (24)
is the output of the address generation circuit 1 (25) to the memory (23
) to output to the address manually. This operation is repeated for a period of unit time {circle around (2)}, and nL (=V/Tl) samples are written in area A. In this period area B, the encoding of n1 samples already written in the previous unit time and the reading of the encoded signal to the modulation circuit (6), that is, the recording signal, are carried out through the line (23a). It is done through The clock generation circuit 2 (29) is connected to the pass line (23
a) Address generation circuit 2 (2E
l), outputs a clock that controls the code encoding circuit (5), latch (27), and memory (23).

Roughly in the next unit time, a sample is written in area B, and in area A, only encoding and reading of the recorded signal are performed, and the area of the memory (23) is sequentially switched every unit time to manually record the signal. Encode and record.

FIG. 4 shows the signal processing of area A and area B, where the side line part of E is the time-compressed Q signal, A1 and B1 show the signal processing of area A and area of the memory, respectively, and a is Sample writing, b indicates sample reading for encoding and check signal occupation, and C indicates recording signal reading.

As described above, the signal processing required for each circuit is performed in a time-division manner via one path line.

The same goes for the reproduction system; the sample write clock (28a) in FIG. 3 corresponds to the readout clock of the signal output to the DA conversion circuit (10), and (29d) performs interpolation and error correction of the reproduction signal. Corresponds to the area.

However, in the above conventional method, multiple Fs
It had the disadvantage of not being able to respond to That is, for example, considering the case corresponding to two Fs, fl and f2, samples generated at Fs, f2 (=L/T2), are written at a constant sampling period T2 shown in (35a) in Fig. 3. In this case, sample writing is performed in the shaded area of (2i3d), and the signal for encoding and recording and 1
There are cases where the generated samples are simultaneously output onto the pass line, and +L normal signal processing cannot be performed.

In order to avoid this problem, the time and date clock generation circuit L (2B) and the clock generation circuit 2 (2B) are used exclusively when Fs=f2.
By providing a clock generation circuit corresponding to 9) and selecting one of them using FS, it is possible to perform signal processing with a positive t〒, but this has the disadvantage of increasing the number of circuit branches.

[Summary of the Invention] This invention II was made in order to eliminate the above-mentioned drawbacks of the conventional technology, and includes a plurality of sampling clock generating means, the first . By providing a second selection means, a detection means for detecting the highest frequency mode, and a sampling circuit for extracting the highest frequency clock, a plurality of Fs can be obtained with a simple configuration.
The purpose is to provide a recording/playback device that can handle

[Embodiments of the Invention] Hereinafter, as embodiments of the present invention, three types of Fs, that is, f
PC compatible with l, f2, f3 (fl-f2>f3)
The M magnetic recording/reproducing device will be explained with reference to one drawing.

FIG. 5 is a block diagram showing an embodiment of the PCM magnetic recording/reproducing apparatus. In FIG. 5, the details of the memory circuit (4) and the encoding circuit (5) are the same as those shown in FIG. (33) and (34) are.

Address generation circuit 1 when Fs is f2 and f3, respectively
Clock generation circuit 3 and clock generation circuit 4, (33a) and (34a) which generate the input clock of (25) and the latch clock of latch (22) are the above-mentioned clock generation circuit 3 (33) and clock generation circuit 4, respectively. (34) The two types of clock outputs mentioned above, (3
3b), , (34b) indicate latch clocks.

(28d) is Fs”゛(7) j9 h (1
) 7 )" Lx Z Q '1""6" (25E7
) shows the latch clock of the A cuff lock and latch (22).

(50) is a switch for specifying the sampling frequency, (51) is the three outputs (33a), (34a)
, (28d) is a selector which is manually operated and outputs any one of the six signals by S IJI' according to a 2-bit Fs designation signal inputted from a switch (50). Here, when Fs designation number S is ro 0J, Fs=f1. ro
When lJ, Fs=f2. It is assumed that Fs=f3 is defined when "rlo". (52) is the output (33b),
(34b) is a selector as an input, (53) is an f1 detection circuit that outputs "O" when the Fs finger/toe signal is specified as Fs=fl, (41) is a selector whose D input is connected to the power supply. (52) has the output (52a) of D-flip-flop (41) as the clock input, and (42) has the non-inverted output (41a) of the D-flip-flop (41) as the D input.
A D-flip-flop whose clock input is a base clock (28e) having a frequency greater than fl generated by the clock generation circuit 1 (28), (43) is a D-flip-flop (42) (1) inverted output ( 42a) and
An interrupt clock (2
(48) is an OR gate that receives the above write clock (28a) and (43) as an input, and a selector that takes the output (43a) of (43) as an input and uses the output of the f1 detection circuit (53) as a selection signal. is shown, and the selector (4
The output of 8) is the AND game in the memory circuit (4)) (1
00) can be used as one input.

Next, the operation will be explained with reference to the time chart shown in FIG.

First, the operation when Fs=fl will be explained. At this time, the "OO" signal is input from the switch (50), and the selector (51) outputs the clock generation circuit 1 (28
) is supplied to the memory circuit (4). f
The l detection circuit (53) detects that the Fs designation signal is "00" and outputs "0" to the select terminal of the selector (48).
1, and the selector (48) outputs the sample write clock (28a) to the memory circuit (4). In this case, the situation is similar to that described in the conventional example, and the sixth
As shown in the figure, the clock is generated so that :''r writing of the input sample is performed at the "0" part of the sample write clock (28a), and the encoding and recording signal reading are performed at the shaded part (29h). Since circuit 2 (29) is configured, there is no problem.

Next, the operation in the case of Fs=f2 (<f1) will be explained. In this case, the Fs designation signal from the switch (50) becomes "01", and the selectors (51) and (52) select and output the signal from the clock generation circuit 3 (33). In addition, the output of the f1 detection circuit (53) becomes "1", and the output of the selector (48) (OR game) (43)
43a) to the memory circuit (4).

In FIG. 6, at time t1, period T2 (=1/f2)
At the rising edge of the latch clock (33b), the non-inverted output (41a) of the D-flip-flop (41) becomes "1".
At time t2, the reference clock (28e) rises and the inverted output of the D-flip-flop (42) (
42a) becomes "0" and the OR gate (43) outputs the sample write clock (28a).

At time t3, the output (43a) of the OR gate (43) becomes "0" and the D-flip-flop (41)
will be reset. Then, at time t4, the D-flip-flop (42) becomes "1" at the rising edge of the clock (28e), and the two D-flip-flops (41) and (42) The initial state is 8.The output of the selector (48), that is, the OR gate (43
) output (43a) is supplied to the write clock input terminal of the memory (23) via the AND gate (+00) in the memory circuit (4), and the latch clock (33a) is supplied to the write clock input terminal of the memory (23) at time t1.
The sample taken into the latch (22) in b) is written into the memory (23) during the period from time L3 to time t4.

As shown in FIG. 6, the time t3 to t4 is (29h)
Since the period avoids the shaded area, it is possible to write samples without shorting with other outputs.

In this way, by using the clock with the highest frequency among multiple Fs as the sample write timing for all Fs modes, and performing encoding and recording signal retrieval in a period that avoids the above sample write timing, multiple Fs 1 Apparatus Realization-c's Compatible with 3 types of Fs were explained in the above embodiment, but by providing a clock generation circuit for each Fs, it is possible to support 3 or more types of Fs. It is possible to configure a recording/reproducing device.

Furthermore, ■ All bits of a sample are written in with one clock, but ■ When the number of bits of a sample is divided by m^1 and written with m clocks, the clock generation circuit 1 (28
This is possible by providing the sample write clock (28a) of ) with an area that can be written m times within one sample period.

Although the reproduction system is not explained in the above embodiment, memory reading is performed at the timing of the output signal of the selector (48) when outputting data to the DA conversion circuit every Fs, and writing of the reproduction signal and The decryption process is (2
It is clear that regenerative signal processing corresponding to a plurality of Fs becomes possible by performing the regeneration signal processing using the shaded period of 9h).

[Effects of the Invention] As described above, according to the present invention, a plurality of sampling clock generating means each generating clocks having different sampling periods.

A sampling mode specifying means for specifying one of a plurality of sampling modes, and an output excluding the highest frequency output from among the outputs of a plurality of sampling clock generating means, and based on the output from the sampling mode specifying means. a first selection means for selecting an input;
A detection means receives the signal from the sampling mode designation means and detects that the highest frequency is designated, and inputs the output of the highest frequency among the output of the first selection means and the output of the sampling clock generation means. and a sampling circuit that extracts at least one of the clocks with the highest frequency existing within one cycle of the output of the selection means of 7iSl, and the outputs of the clock with the highest frequency and the sampling circuit are input, and the output of the detection means is selected. A second selection means is provided, and the output of the second selection means is used to write the human signal into the memory or read the reproduced signal from the memory, and at other timings, encode and record the signal. Since reading or decoding processing and writing of the reproduced signal into the memory are performed, it is possible to realize a recording/reproducing apparatus capable of supporting a plurality of sampling frequencies with 1) a small f5 configuration.

[Brief explanation of the drawing]

Fig. 1 is a block diagram showing a conventional recording/reproducing device, Fig. 2 is a block diagram showing details of the memory circuit and clock generation circuit in the FT51 diagram, and Fig. 3 is a time chart for explaining the operation of Fig. 2. , FIG. 4 is a diagram for explaining signal processing in area A and area B, FIG. 5 is a block diagram showing an embodiment of the recording/reproducing apparatus according to the present invention, and FIG. 6 explains the operation of FIG. 5. This is a time chart for (28)...Clock generation circuit 1, (29)...Clock generation circuit 2, (33)...Clock generation circuit 3
．． (34)...Clock generation circuit 4. (41), (4
2)...D-flip-flop, (43)...O
R gate, (48)...Selector, (50)...
Switch, (52)...Selector, (53)...
f1 detection circuit. In addition, in FIG. 1, the same reference numerals indicate the same or corresponding parts.

Claims (1)

[Claims] (1) During recording, a digital signal generated at a fixed sampling period is input, this input signal is stored in a recording memory, and a check signal for error correction and error detection is added and encoded. After that, the signals are sequentially read out from the recording memory and recorded on the recording medium, while at the time of playback, the playback signals are stored in the playback memory and subjected to error correction processing, and then the original signals are read from the playback memory at sampling intervals. The recording and reproducing apparatus reads and outputs a digital signal, and is capable of performing the recording and reproducing process at a plurality of sampling frequencies, comprising: a plurality of sampling clock generating means for generating clocks each having a different sampling period; , a sampling mode specifying means for specifying one of a plurality of sampling modes, and an output excluding the highest frequency output among the outputs of a plurality of sampling clock generating means, and an output from the sampling mode specifying means. a first selecting means for selecting an input based on the input; a detecting means for receiving a signal from the sampling mode specifying means and detecting that the highest frequency is specified; and an output and sampling of the first selecting means. a sampling circuit that takes as input the output of the highest frequency among the outputs of the clock generation means and extracts at least one clock of the highest frequency existing within one cycle of the output of the first selection means; a second selection means having the output of the circuit as an input and the output of the detection means as a selection signal;
The input signal is written to the memory or the reproduced signal is read from the memory at the output of the selection means, and the encoding and recording signal are read out, or the decoding process and the reproduced signal are written to the memory at other timings. A recording/reproducing device characterized by: