JPS6149517A - Pulse generating circuit - Google Patents

Abstract

PURPOSE:To improve the cost performance by constituting a semiconductor integrated circuit as the pulse generating circuit composed of a differential amplifier to which an input signal is inputted, a slow differential amplifier, a fast differential, an AND circuit, and an OR circuit. CONSTITUTION:An unipolar input Vin is supplied to the 1st differential amplifier consisting of transistors (TR) Q3 and Q4 to generate outputs Va and Va'. Then, they are inputted to the 2nd slow differential amplifier consisting of TRs Q5 and Q6 through the level shifting circuit composed of TRs Q3 and Q4 and converted into polarity-inverted outputs Vb and Vb' a certain time later. Further, they are inputted to the 3rd fast differential amplifier consisting of TRs Q7 and Q8 and converted into polarity-inverted rectangular waves Vc and Vc'. The waves are inputted to the OR circuit composes of a resistance R10 through respective AND circuits composed of TRs Q9-Q11 and Q12-Q14, thereby generating a pulse output. Thus, the pulse width is determined by the delay time and the cost performance is improved.

Description

[Detailed Description of the Invention] [Technical Field of the Invention] This invention relates to the rise of a rectangular wave in a semiconductor integrated circuit,
When generating a pulse at each falling point, it can be configured without providing an external capacitor or resistor.51CLy:
It concerns the pulse generation path.

[Prior art]

Conventionally, when generating pulses from the rising and falling parts of a rectangular wave, two sets of pulsing circuits such as a polarity inverting circuit and a monostable multivibrator are used, and a C which determines the pulse width t is used.
(capacitor), R (resistor element, etc.) were required.

When constructing a conventional pulse generating circuit Z using a semiconductor integrated circuit, an external KC is required in order to match the pulse width and the bearings at rise and fall.

This has the drawback that the number of IC pins and external elements increases, which increases the cost, since the pulse width is set by providing a gate such as R and the like.

[Summary of the invention]

In order to eliminate the above-mentioned drawbacks of the conventional BA, this BA uses the n-time rkQY of the transistor, and is simple and inexpensive by using 5K, which can omit external bins and elements such as external C and R. This provides a pulse generation circuit. Hereinafter, one embodiment of the present invention will be explained with reference to the drawings.

[Embodiments of the invention]

FIG. 1 is a circuit diagram showing an embodiment of this invention.
Input, vrel kl reference voltage source, Q,, Q2 are transistors, R1+R2&'f, load resistor +Cs+
is a constant current source, and Cott et al. Q+ −Qx , R+
, R2 and C,l constitute a first differential amplifier i-+ n
Ru.

Further, the level shift circuit includes transistors Q3 and Q4, level shift resistors R3 and R4, and constant current source Cm.
2r 0g3 n, delay time τpd (propa
(delay time) The second differential amplifier designed to generate Y is the transistors Qs and Qa.
and load resistor Rs HR6, level soft resistor R
7° diode D3. It consists of a constant current source C,4. Furthermore, the third differential amplifier is a transistor Q to perform waveform shaping to obtain a stable delay time of τ, d/2.
7. Q,, °Load resistor Rs r Rs + diode D21 Consists of constant current source 0.5 n, negative logic AN
D circuit is transistor Q e + Q+o+ Q+++
A constant current source C1 constitutes a negative logic AND circuit, and a negative logic AND circuit consists of transistors Q+z jQ+z l Q101 constant current sources C and g. Note that VreL2 is a reference voltage source, To is an output terminal, and vc! is the power supply voltage.

FIG. 2 is a waveform diagram for explaining the operation of FIG. 1, where the horizontal axis is the time axis, the vertical axis is the input vIfi, the output v, η, and the delay n time τd of the first differential amplifier. The output vb of a predetermined second differential amplifier for generating , and the output ve of a third differential amplifier for waveform shaping.

η, the output vd + ve of the negative logic AND circuit, and the output To' of the OR circuit.

FIG. 3 is a waveform diagram for explaining the operation when the rise time and fall time of the second differential amplifier are different.
The Y solid line and the broken line are superimposed, and the horizontal axis is time t, and the vertical axis is l1cva + vb + 'b l Ve
It shows.

Next, I will explain about the operation.

In FIG. 1, when a rectangular wave input V1m is applied to the first differential amplifier, its load resistor RI.

Through R2 and buffer transistors Q, , Q4, bipolar outputs v, , v, are obtained.

Through the level shift resistors R1 and R4', the outputs V m + V A are Rs Iz and R4Is, respectively.
level shift. In this case, the output of the original square wave v1. It is assumed that the phase is the same as that on the time axis, and the delay n time can be ignored. Then the output V, , V.

is added to the second differential amplifier to generate the delay time 7, and an output of vl, , 9b is obtained. The respective rising and falling slope voltages vbr+π and Vbfl are equal.

The next K, output Vb+'b is applied to a predetermined third differential amplifier for waveform shaping, and each rising and falling slope voltage Vbr
and four voltage levels are equal, and each falling and rising slope voltage vbt is reversed at a time t3, which is equal to
An output whose output voltage is Ver-ma) is obtained, n, v,
, v, respectively r (l + + τD2 delay r. Here, the rise and fall times of vbl and vl, respectively, differ due to the influence of parasitic capacitance when integrated circuits are implemented, but transistors QIll and Q61 resistors If the characteristics of R5-R6 are aligned and balanced, the rising voltage Vbr will increase as described above.
+ τ1 and falling voltage vbf + 951 can be made equal, and under these conditions the delay time τ. 1. τ
The fact that D2 becomes equal will be explained using FIG. 3.

Constant current source C in FIG. 1, 4Tl-current bias current generator.

By choosing an arbitrary value, the delay time τDl + τnz'l
Assume that an example of setting a certain size is shown in FIG. 3. As is clear from Fig. 3, time t
Vjr from 0 to t1 and from t2 to t3, ■
are equally straight and the slopes of t0 to t and t2
When the slopes of vbt T'Ib from t3 to t3 are equal and straight, the indicators τD1 and τD2 have the same value (here, lrL is τ) from the starting point to the intersection.

The rectangular waves n, v, , v,', ve, -9 obtained in this way are obtained by two sets of AND circuits forming a negative logic, transistor Q 9 a Q1o+ Qll and transistor Q lzr Qsx* Q14, and v
ll ・ve = vd, v& ・vc =
v.

is obtained, and at the terminal of the resistor R1° constituting the OR circuit, v, =v4 +v.

An output of n is obtained. Here, l4 = 50 μA.

When R,=16 is Ω, and Rs=16 is ΩK L rs, τ
50 na in D is obtained.

The pulse generating circuit according to the present invention determines the pulse width by the delay time, and when the pulse width is particularly narrow, it has a stable pulse width χ and can generate pulses at the rising and falling parts of the input rectangular wave.

〔Effect of the invention〕

As explained above, this invention has a unipolar input vInV.
Bipolar output vll from the first differential amplifier from c.

These n outputs vll, -- are passed through a low-speed second differential amplifier and converted into outputs vb, Vj with a certain time delay ft and inverted polarity.
The outputs vb+v6' from vb+v6' are passed through a high-speed third differential amplifier to invert the polarity and generate a rectangular wave v8. 7d2v11 ・
Vcl V, =7.・Convert to an output v8, and convert these n outputs v4. v, V using an OR circuit from VC
It consists of a circuit that generates a pulse output sound of O = v, 1 + v, so when it is configured as an integrated circuit, the time width of the pulse? Since the C and R elements and external terminals can be eliminated, an inexpensive pulse generating circuit with good cost performance can be constructed, and there is an advantage that it can be widely used in various industrial fields.

[Brief explanation of the drawing]

FIG. 1 is a pulse generation circuit diagram according to an embodiment of the present invention.
FIGS. 2 and 3 are typical waveform diagrams for explaining the operation of FIG. 1. In the figure, vl. is the input, Vrefl r Vrefl is the reference voltage source, Q8 to Q14 are transistors, R□l
R1+ Ra1R6, R81R9 are load resistors/Ra
, R4, R7 is a bell shift resistor, Ca I"-CB7 k1 constant current source, DI-02 is a diode, To is an output terminal,
wee is the power supply voltage. Note that the same reference numerals in the figures indicate the same or corresponding parts. Agent Masuo Oiwa (2 others) Figure 2 - Sait P1t

Claims (1)

[Claims] Unipolar input v_i_n causes bipolar output v_a, @
a first differential amplifier that generates v_a@, and the output v
a low-speed second differential amplifier that converts _a, @v_a@ into an output v_b, @v_b@ with a certain time delay and inverted polarity, and a rectangular wave with inverted polarity due to the output v_b, @v_b@ a high-speed third differential amplifier that converts the output v_c, @v_c@, and further v_d=@v@
_a・@v_c@, two sets of AND circuits that convert the output to v_e=v_a・v_c, and the outputs v_d, v_e
1. A pulse generating circuit comprising an OR circuit that generates a pulse output of v_0=v_d+v_e, wherein each of the differential amplifiers, the AND circuit, and the OR circuit are constructed of semiconductor integrated circuits.