JPS6149509A - Signal level equalization processor - Google Patents

Abstract

PURPOSE:To improve responsiness, and to eliminate an oscillation phenomenon and to attain stabilization by controlling a level control circuit on the basis of the bit information of a digital signal obtained by converting an input signal and performing equalization processing. CONSTITUTION:When an input signal is applied to an input terminal Ti, its amplitude is converted by an A/D converter 11 into an (n)-bit digital signal, which is passed through an absolute value circuit 12 to obtain an absolute value ¦X¦. The absolute value ¦X¦ is stored in a memory part 13 so as to obtain a desired level value V0 at a signal output terminal To. Storage parts of the memory part 13 for respective bits are formed of an OR gate and a D type FF and when each bit of the absolute value ¦X¦ is 1, the maximum value of the absolute value ¦X¦ is stored unless the output value of the memory part 13 is reset and respective relays of a control circuit 10 are switched in correspondence to respective bits, so that the signal at the terminal To is controlled to the desired level V0.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a signal level equalization processing device that can amplify or attenuate an unknown signal to a predetermined level.

[Conventional technology]

When measuring or observing the level of an unknown signal, or when inputting a signal with large amplitude fluctuations to a control device, compare the level of the unknown signal with a reference voltage that is the reference level, and check the level of the unknown signal. Level equalization processing may be performed to amplify or attenuate the unknown signal using the difference signal.

FIG. 1 shows an example of a conventional device that performs such signal level equalization processing, where T1 is a signal input terminal to which an unknown signal is input, and To is a signal output terminal to which an equalized signal is output. , 1 is a level control circuit that can amplify or attenuate the signal level, 2 is a low-pass filter for detecting the signal and peak level, 3a, 3b, . . .
, 3n are reference voltages 4a, 4b, . . . , respectively.
4n is a comparator, 5 is the comparator 3a, 3b,
.......

This is a level calculator that generates a control signal for the level control circuit 1 from the output signal of 3n.

In this signal level equalization processing device, the signal level of the signal output terminal To is a plurality of reference voltages 4a.

4b, .
Even when an unknown signal is input, a signal at a predetermined level can always be obtained at the signal output terminal TO.

However, since this control device is equipped with a low-pass filter 2 that converts an analog signal into a DC level, it has the disadvantage that the time constant of the low-pass filter 2 increases the time it takes for the output DC level to stabilize.
There was a problem with poor responsiveness.

Furthermore, since a plurality of reference voltage sources are required, the adjustment work is complicated and the circuit is also complicated.

Another problem is that oscillation is likely to occur when the analog input and reference voltage are close to each other.

[Purpose of the Invention] The present invention was made with the aim of solving the above problems, and by introducing digital signal technology to signal level control, it speeds up the level equalization process and also reduces the effects of aging. The present invention provides a signal level equalization processing device with less noise.

〔Example〕

Hereinafter, an overview of the present invention will be explained based on the block diagram of FIG. 2.

In this figure, 10 is a level control circuit that can amplify or attenuate the signal level according to a digital signal, 11 is an A/D converter that can convert an analog signal to a digital signal, and 12 is a converted digital value. An absolute value circuit converts X into an absolute value IXI, and 13 represents a memory section that stores the absolute value lxl.

Next, the operation of this signal level equalization processing device will be explained.

First, the level control circuit 10 is set to the through state [
Gain A= (AH+A2 +−・・−・−+An)=
0]. The level control circuit 10 is 6dB as shown in FIG.
Amplifier A 1 + A2' + A3..."" +
” are connected in series, for example relays R+, R2, R3
.

......, switch S1 + S2 by Rn
+83+..., the gain is A when Sn is controlled to be on. Signal “0°” to all relays R1+R2, R3,..., Rn
', the gain A of the level control circuit 10 can be set to O.

When the input signal e1 is applied to the input terminal Ti in this state, its amplitude is changed by the A/D converter 11 to an n-bit digital signal (aO+ al+E"2+ """ +
ELn ) (ao indicates MSB). This digital signal (ao l aI +a2+...
, an) through the absolute value circuit 12, the absolute value l
X I (0+ al + R2+...

an) is obtained.

■ The desired level value obtained from the signal output terminal To. In order to do this, the absolute value 1xl obtained as described above is stored in the memory section 13.

In the memory section 13, for example, as shown in FIG.
3b, each bit (0, al, R2.

..., when In) becomes 1, the memory section 13
The output value of B (0, bl, b2..., bn)
Then, unless that bit is set as I, the signal “
I 11 is stored and retained.

Therefore, the maximum value of the absolute value lxl is stored in this memory section 13. Note that in order to store the maximum value of X, IXI may be a negative absolute value.

In other words, if the absolute value 1xl changes within the range from (000...0) to (00101...01), the "1'" state of each bit is stored, so 0
0111...11 will be stored.

Therefore, each relay RI + of the level control circuit 10
R2+ R3+ “”” + R” is each bit (bi
), and in the above example, the relays R, , R2 are turned off by the signal ``0'', and the output is 6dBX2.
It will have a gain of

Therefore, the thickest and thinnest signal of the signal output terminal To is v
The level is controlled to a desired level value of O.

By applying a reset signal to the memory section 13, the level control circuit 10 becomes OdB, and can control other input signals having different levels to a desired level value.

The desired level value VO, that is, the appropriate level in the explanation so far, is the digital signal (aO+a1900.0
0. , an) for al + R2+ ”900.
The absolute value of the amplitude of +an is lO...0 to 11.
...I explained the levels up to l,
This appropriate level can be selected at any level. For example, from 010...0 to Oll...
- If the level is selected to be in the range of 1, that is, 6 dB lower than the above-mentioned appropriate level, if there is a level higher than this principle, it is necessary to attenuate it to the above-mentioned appropriate level.

Of the level control circuit 10, the amplifier controlled by relay R is set as an attenuator and turned off by the signal "1", and the parts controlled by relay R2 and after are set as amplifiers, and the amplifier controlled by the signal "°O" is set as an attenuator. To be controlled off. In this case, output B is 111...
・When it becomes l, only relay R1 is controlled off, and 6
By operating the dB attenuator, the output signal is controlled to an appropriate level.

In addition, if the appropriate level is selected to be 6 dB or more lower than the above level, the output B will be 0010...
When the value becomes O~0011...1, the output signal is similarly controlled to an appropriate level.

As can be understood from the above embodiments, the signal level equalization processing device of the present invention converts an analog signal into a digital signal, processes the converted digital signal, and then converts the signal “1” contained in each bit of the signal level equalization processing device into a digital signal. Since the level control is performed according to the number of , the level equalization process becomes faster than before, and there is no aging and oscillation phenomenon can be eliminated.

Furthermore, although the above description has been made regarding the input of analog signals, since digital values are used for signal level equalization processing, by providing a digital level control circuit that amplifies and attenuates the digital signals, It is also possible to equalize the digital signal at an appropriate level as it is.

As is clear from the explanation of the case where 6 dB steps are equalized in the above embodiment, the output value B of the memory section 13 stores the "°1" state of each bit of the signal. 0100...0 and 0111...
...l can be treated as the same signal. In other words, it is observed with an accuracy of 6 dB.

Furthermore, in order to perform fine level control, it is necessary to detect at which level within the 6 dB range the maximum value of the signal is. As this detection method, a circuit is provided to obtain the following output value B' in addition to the output value B described above. When controlling with an accuracy of β (0 × β < 6) dB, as shown in FIG.
The output obtained through the memory section 13' is multiplied by B'.
(o, b,',...,bn'). The output value B (0, bl + b2 + ...... +
bn) for B'(0, b5', b2',...
, bn') is a range of 16 dB from the signal level O, then b1' is from 0-β dB to -6-β
To indicate a dB range, when bl is 1, if b1' is 1, the signal level is in the range of 0 to 1 β dB, and if b1' is O, the signal level is - β
This corresponds to a range of -6-βdB from . In the latter case, if an amplifier with a gain of .beta.dB is provided in the level control circuit 10 instead of 6 dB, and the relay is controlled by the digital signal b', level control finer than 6 dB can be achieved. In this way, it becomes possible to control the level with a precision even finer than 6 dB.

FIG. 5 shows a block diagram when the signal level equalization processing device of the present invention is applied to a level meter.

In this figure, 20 is a first stage amplifier, 21 is a level control circuit, and there are four amplifiers 21A and 21B.

An example in which 21C and 21D are used is shown.

21Rr, 21R2', 21R3, 214 are contacts 31
~ Shows the relay that switches S8, and this relay 21R1 ~
60 in 6dB steps by controlling 21R4.
It is configured to obtain a gain of up to dB.

Reference numeral 22 represents a high frequency limiting filter, 23 represents a sampling hold circuit 23, and 24 represents an A/D converter.

The signal converted into a digital signal by the A/D converter 24 is sent to a digital filter 25 .
Square law detector 26. Integrator 27. It is output as data via an output meter 28 and an adder circuit 29.

On the other hand, the output signal of the A/D converter 24 is transmitted to the level control circuit 2.
In order to form a control signal of 1, the signal is inputted via the absolute value circuit 30 to an OR circuit 31° register 32 constituting a storage section, where the digital value of the maximum level of the input levels is stored. 33 is a decoder that converts the data stored in the register 32; 34 is an interface circuit; 35
36 indicates a microprocessor (CPU) and an input device (keyboard, etc.).

Next, the operation of this level meter will be explained.

The unknown input signal supplied to the first stage amplifier 20 is
Under the control of the CPU 35, each amplifier 21A to 21D of the level control circuit 21 is taken in a through state, and the level value of at least one cycle of the signal is taken into the register 32 as a digital signal. Since this value is the absolute maximum value of the input signal as described above, the amplification information of this data is first outputted by the CPU 35, and based on the amplification information, the contacts S1 to S of the level control circuit 21 are
Open and close 8.

For example, when the amplification information is 30 dB, relay 21R1 and relay R4 are driven by the output of CPU 35, and amplifiers 21A and 2'ID are connected in series. Then, the measurement frequency band and the type of measurement level (effective level, average level, power level) are input from the input device 36 to the CP.
When input to U35, digital filter 2
5, square law detector 26, etc. are controlled according to the instruction contents.

Since the indicated value of the output meter 28 indicates the deviation value from the reference level of the signal equalized to the appropriate level,
With respect to the indicated value of the output meter 28 by the addition circuit 29,
By adding 30 dB, the actual level data of the input signal can be obtained.

Note that when the input signal level fluctuates and falls outside the output level instruction range, the register 32 may be reset, amplification information may be newly calculated in the CPU 35, and the gain of the level control circuit 21 may be reset.

〔Effect of the invention〕

As explained above, the signal level equalization processing device of the present invention converts an input signal into a digital signal, and then controls a level control circuit using the bit information of the digital signal to perform signal level equalization processing. This has the advantage that an equalized output signal can be obtained quickly, and since digital processing means is used, there is little influence from aging. Furthermore, even when the set level and the input level are close to each other, it is stable without causing any oscillation phenomenon, so it can be applied to measuring instruments, process control circuits, etc.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an example of a signal level equalization processing device according to the prior art, FIG. 2 is a block diagram of a signal level equalization processing device according to the present invention, and FIG. 3 is a configuration showing an example of a level control circuit. 4 is a specific circuit configuration diagram of the memory section, and FIG. 5 is a block diagram of a device in which the signal level equalization processing device according to the present invention is applied to a level meter. In the figure, 10 is a level control circuit, 11 is an A/D converter, 1
Reference numeral 2 indicates an absolute value circuit, and reference numeral 13 indicates a memory section.

Claims (1)

[Claims] A level control circuit that receives a control signal, amplifies or attenuates the input signal level and outputs it; and an A/D that converts the analog signal output from the level control circuit into a digital signal.
a converter; and a memory section that stores the absolute maximum value of the digital signal output from the A/D converter, and uses the absolute maximum value of the digital signal stored in the memory section as the control signal. A signal level equalization processing device, characterized in that the output signal level from the level control circuit is subjected to equalization processing.