JPS6149243A - Diagnostic interface system - Google Patents

Diagnostic interface system

Info

Publication number
JPS6149243A
JPS6149243A JP59171084A JP17108484A JPS6149243A JP S6149243 A JPS6149243 A JP S6149243A JP 59171084 A JP59171084 A JP 59171084A JP 17108484 A JP17108484 A JP 17108484A JP S6149243 A JPS6149243 A JP S6149243A
Authority
JP
Japan
Prior art keywords
signal
diagnosed
data
diagnostic
fault
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP59171084A
Other languages
Japanese (ja)
Inventor
Kyoichi Okumura
奥村 享一
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP59171084A priority Critical patent/JPS6149243A/en
Publication of JPS6149243A publication Critical patent/JPS6149243A/en
Pending legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00Error detection; Error correction; Monitoring
    • G06F11/22Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Quality & Reliability (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Test And Diagnosis Of Digital Computers (AREA)

Abstract

PURPOSE:To shorten the diagnosing time by producing the answer signals in response to the commands given from a diagnosing device and transmitting the answer signal to the diagnosing device when no fault signal is produced in case the data given from the diagnosing device has an error. CONSTITUTION:A diagnosing device 1 write and reads data to and out of devices 2-N to be diagnosed through an interface 10. These devices 2-N report the presence or absence of connection of their own devices as well as the generation of faults to the device 1 via the diagnosis enable signal 11. Here a comparator 21 compares the address data on the devices to be diagnosed which are given from the device 1 with the data on an address register 23 of own device. Then an FF22 is turned on with the data error detecting signal sent from the device 1 and the fault detecting signal of the device 2. An AND between the output signals of the comparator 21 and the FF22 is secured through an AND gate 20. Then the signal 11 is turned on and off.

Description

【発明の詳細な説明】 (技術分野) 本発明は情報処理システムの診断インタフェース方式に
関する。
TECHNICAL FIELD The present invention relates to a diagnostic interface method for an information processing system.

(従来技術) 従来の診断インタフェース方式においては診断装置は指
定する被診断装置が診断インタフェース上に接続されて
いるかどうかについてただちに判別する手段は備わって
おらず、この為診断装置は該被診断装置の特定のレジス
タを読出して接続の有無を判別している。
(Prior Art) In the conventional diagnostic interface method, the diagnostic device is not equipped with a means to immediately determine whether or not the specified device to be diagnosed is connected to the diagnostic interface. A specific register is read to determine whether there is a connection.

さらに、診断を実行している際被診断装置に送出したデ
ータの誤りや該被診断装置側に発生した障害等をただち
に発見出来る手段も従来の診断インタフェース方式には
備わっていない。この為診断装置はデータを送出ししば
らく時間が経過した後の被診断装置からの読出しデータ
により始めて障害がダ発生したことを知ることがでさた
Furthermore, the conventional diagnostic interface system does not have a means for immediately discovering errors in data sent to a device to be diagnosed or failures occurring on the device to be diagnosed during diagnosis. For this reason, the diagnosing device could not know that a fault had occurred until the data was read from the device to be diagnosed some time after the data had been sent out.

以上のように従来の診断インタフェース方式では診断装
置が被診断装置の接続の有無及び障害の発生を知るのに
時間がかかった為診断を実行する時間も長くなるという
欠点がるる。
As described above, the conventional diagnostic interface method has the drawback that it takes time for the diagnostic device to know whether the device to be diagnosed is connected or not and whether a fault has occurred, so that the time required to execute the diagnosis is also increased.

(発明の目的) 本発明の目的に診断インタフェース上に、指定する被診
断装置が診断インタフェース上に接続されておυかつ該
被診断装置が正常に動作していることを示す信号線を新
たに設けることにより診断時の診断時間を短かくできる
診断インタフェース方式を提供することにある。
(Objective of the Invention) The purpose of the present invention is to add a new signal line on the diagnostic interface to indicate that the designated device to be diagnosed is connected to the diagnostic interface and that the device to be diagnosed is operating normally. It is an object of the present invention to provide a diagnostic interface system that can shorten the diagnostic time during diagnosis by providing the diagnostic interface method.

(発明の構成) 本発明の装置は、複数の被診断装置が分岐接続されてい
る診断インタフェース方式において、診断装置からの指
定に応答して指定された被診断装置から応答信号を発生
する応答信号発生手段と、前記診断装置から被診断装置
に供給されるデータに誤9が発生したときまたは被診断
装置に障害が発生したときの少なくともいずれかの場合
に障害信号を発生する障害信号発生手段と、前記応答信
号の供給をうけ前記障害信号発生のときには前記応答信
号を阻止し前記障害信号の発生のないときには前記応答
信号を通過せしめる信号処理手段と、前記複数の被診断
装置の前記信号処理手段からの出力信号r前記診断装置
に供給する信号処理手段とを含んで構成される。
(Structure of the Invention) The device of the present invention uses a response signal that generates a response signal from a designated device to be diagnosed in response to a designation from the diagnostic device in a diagnostic interface system in which a plurality of devices to be diagnosed are branch-connected. and a fault signal generating means for generating a fault signal when an error 9 occurs in data supplied from the diagnostic device to the device to be diagnosed or when a fault occurs in the device to be diagnosed. , signal processing means that receives the response signal and blocks the response signal when the fault signal occurs and passes the response signal when the fault signal does not occur; and the signal processing means of the plurality of devices to be diagnosed. and a signal processing means for supplying an output signal r to the diagnostic device.

(実施例) 次に本発明について図面を参照し詳細に説明する0 第1図は本発明の一実施例を示すブロック図である。(Example) Next, the present invention will be explained in detail with reference to the drawings. FIG. 1 is a block diagram showing one embodiment of the present invention.

第1図の診断インタフェース方式において診断装置lr
iインタフェース10により被診断装置2゜3・・・・
・・Nに対しデータの舊込み、読出しを行う。
In the diagnostic interface method shown in Fig. 1, the diagnostic device lr
The i-interface 10 allows the device to be diagnosed 2゜3...
...Data is input and read from N.

被診断装置2.3・・・・・・Nは自装置の接続の有無
及び障害発生の有無を診断可能信号11により診断装置
lに報告する。
The devices to be diagnosed 2.3, . . . .

第2図は第1図の被診断装置の一部回路図を示す。例と
して被診断装f2について説明する。
FIG. 2 shows a partial circuit diagram of the device to be diagnosed in FIG. As an example, the device to be diagnosed f2 will be explained.

第2図にポす被診断装置2の一部回路は被診断装置2の
自装置アドレスデータを格納している自装置アドレスレ
ジスタ23と、診断装置1がらインタフェースlOr介
して供給される被診断装置アドレスデータと自装置アド
レスレジスタ23に格納されているデータとを比較し一
致したときにオン1g号を発生する比較回路21と、被
診断装置2に障害が発生したときその障害検出信号によ
りオンになりまた診萌装[1がらインタフェース10を
介して供給されるデータに誤りがめったときにその[検
出信号によりオンになるフリップフロップ22と、比較
回路21の出力信号と7リツプフロンプ22の出力信号
(フリップフロップ22がオフのときはオンになりフリ
ップフロップ22がオンのときにはオフになる)との崗
理槓をとるアンドゲート20とを含んで構成されている
A part of the circuit of the device to be diagnosed 2 shown in FIG. The comparison circuit 21 compares the address data with the data stored in the own device address register 23 and generates the ON signal 1g when they match, and turns ON by the failure detection signal when a failure occurs in the device to be diagnosed 2. In addition, when an error occurs in the data supplied via the interface 10, the diagnosis signal is turned on by the flip-flop 22, the output signal of the comparison circuit 21, and the output signal of the 7-lip flop 22 ( The gate is turned on when the flip-flop 22 is off, and is turned off when the flip-flop 22 is on.

次に第2図の回路の動作について説明する。診断装置1
からインタフェース10により被診断装置2に被診断装
置アドレスが送出された場合、あらかしめ記憶している
自装置アドレスレジスタ23に格納されている自装置ア
ドレ′スとともに比較[O1路21に人力され、これら
が一致した場合は出力をオンとする。ここでフリップフ
ロップ22がオフの場合はアンドゲート20の出力つま
シ診断可能信号11がオンになり診断装置1は被診断装
置2が接続されていることを知る。一方比較回路21の
結果が不一致の場合、フリップフロップ22がオンの場
合又は被診断装置2そのものが接続されていないときは
診断可能信号11はオフとなり被診断装置!t2の未接
続を知る。又診断中破診断装置2において診yfr装f
tlからのデータにエラーを発見したか又は自装置にお
いて障害が発生した場合にはそれらの誤り検出信号また
は障害検出信号によシフリップフロップ22t−オンに
する。これによりアントゲ−)20の出力つまり診断可
能信号11はオフになる。診断装置1は診断中に前記診
断可能信号11がオフになった事によシ該被診断装置2
に障害が発生した事を知る。
Next, the operation of the circuit shown in FIG. 2 will be explained. Diagnostic device 1
When the device address to be diagnosed is sent from the interface 10 to the device to be diagnosed 2, it is compared with the device address stored in the device address register 23 which is preliminarily memorized. If these match, the output is turned on. If the flip-flop 22 is off, the output diagnosable signal 11 of the AND gate 20 is turned on, and the diagnostic device 1 knows that the device to be diagnosed 2 is connected. On the other hand, if the results of the comparison circuit 21 do not match, if the flip-flop 22 is on, or if the device to be diagnosed 2 itself is not connected, the diagnosable signal 11 is turned off and the device to be diagnosed! Know that t2 is not connected. In addition, in the diagnosis intermediate damage diagnosis device 2, the diagnosis yfr equipment f
If an error is found in the data from tl or a failure occurs in the own device, the shift flip-flop 22t is turned on by the error detection signal or failure detection signal. As a result, the output of the computer game 20, that is, the diagnosable signal 11 is turned off. The diagnostic device 1 detects the device to be diagnosed 2 due to the diagnosable signal 11 being turned off during diagnosis.
learn that a problem has occurred.

(発明の効果) 本発明には診断装置と被診断装置との間に診断可能信号
?i−設けることにより被診断装置の診断町叱状悲金短
時間で仰ることができ診断時の診断時間を短鰯出米ると
いう効果がめる。
(Effects of the Invention) The present invention includes a diagnosable signal between a diagnostic device and a device to be diagnosed. By providing i-, a diagnosis can be made in a short time for the device to be diagnosed, which has the effect of shortening the diagnostic time at the time of diagnosis.

−囲の間417r説明 第1図は本発明の一実施例を示すブロック図、第2図は
第1図に示した彼診Vr装置の部分回路図でめる。
- Explanation of the Surrounding Room 417r FIG. 1 is a block diagram showing an embodiment of the present invention, and FIG. 2 is a partial circuit diagram of the patient diagnosis Vr device shown in FIG. 1.

1・・・・・・診fdT装置、2.3・・・N・・・・
・・被診断装置、20・・・・・・アンドゲート、21
・・・・・・比較回路、22・・・・・・フリップフロ
ラフ゛、23・・・・・・自装置アドレスレジスタ。
1... Diagnosis fdT device, 2.3... N...
...Diagnosed device, 20...And gate, 21
... Comparison circuit, 22 ... Flip flow circuit, 23 ... Own device address register.

第 1 図 茅2 図Figure 1 Kaya 2 diagram

Claims (1)

【特許請求の範囲】 複数の被診断装置が分岐接続されている診断インタフェ
ース方式において、 診断装置からの指定に応答して指定された被診断装置か
ら応答信号を発生する応答信号発生手段と、 前記診断装置から被診断装置に供給されるデータに誤り
が発生したときまたは被診断装置に障害が発生したとき
の少なくともいずれかの場合に障害信号を発生する障害
信号発生手段と、 前記応答信号の供給をうけ前記障害信号発生のときには
前記応答信号を阻止し前記障害信号の発生のないときに
は前記応答信号を通過せしめる信号処理手段と、 前記複数の被診断装置の前記信号処理手段からの出力信
号を前記診断装置に供給する信号供給手段とを含むこと
を特徴とする診断インタフェース方式。
[Scope of Claims] A diagnostic interface system in which a plurality of devices to be diagnosed are branch-connected, comprising: response signal generating means for generating a response signal from a designated device to be diagnosed in response to a designation from the diagnostic device; a fault signal generating means for generating a fault signal when an error occurs in data supplied from the diagnostic device to the device to be diagnosed or a fault occurs in the device to be diagnosed; and supplying the response signal. signal processing means for blocking the response signal when the fault signal occurs and passing the response signal when the fault signal does not occur; A diagnostic interface method comprising: signal supply means for supplying a signal to a diagnostic device.
JP59171084A 1984-08-17 1984-08-17 Diagnostic interface system Pending JPS6149243A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP59171084A JPS6149243A (en) 1984-08-17 1984-08-17 Diagnostic interface system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59171084A JPS6149243A (en) 1984-08-17 1984-08-17 Diagnostic interface system

Publications (1)

Publication Number Publication Date
JPS6149243A true JPS6149243A (en) 1986-03-11

Family

ID=15916704

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59171084A Pending JPS6149243A (en) 1984-08-17 1984-08-17 Diagnostic interface system

Country Status (1)

Country Link
JP (1) JPS6149243A (en)

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