JPS6148893A - Driver-built-in active matrix panel - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to an active matrix panel with a built-in driver formed of thin film transistors (hereinafter abbreviated as TPT).

[Prior art]

Trial production of active matrix panels in which a T7T matrix for switching was formed using a thin film layer of polycrystalline silicon or amorphous silicon on a transparent substrate was successful in various places, and LCD televisions using active matrix panels were mass-produced and commercialized. It's coming. The aforementioned switching T? Attempts have also been made to form drivers for scanning lines or data lines on the same transparent substrate on which the T matrix is formed, and the results have already been announced. (Y, 0ana S Engineering I) 84D Engineering Gl! :S
'r, P.

312, S, Morozumi, et hIS 84
The conventional driver built into the active matrix panel, especially the data line driver, is configured as shown in Figure 1, with the data lines 111°, 112.・・・・・・
Each analog switch 1a16°107,...
. . . are connected to shift registers 101, 102 . It is controlled by the output signal of... In the figure, 121 is a video signal line, and 122 is a scanning line. When the data line driver is configured as described above, the shift register must operate at the same frequency as the sampling frequency of the video signal, and high speed is required. However, in general T
The on-resistance of IFT is high, and single crystal silicon MO8FET
It is not possible to expect such high-speed operation. Therefore, according to conventional active matrix panels with built-in drivers, TIFT
The characteristics of the video signal limit the sampling frequency of the video signal, and there is also a limit to high definition. [Objective] An object of the present invention is to solve the above-mentioned drawbacks of the prior art and to perform sampling of the video signal at a high frequency. The goal is to create an active matrix panel with a built-in driver that has high display quality.

[Summary] The present invention has a configuration in which an active matrix panel having N data lines is driven by an output signal of an i-stage shift register built in the active matrix panel and at least external clock signals. That's the gist of it.

〔Example〕

Hereinafter, the present invention will be described in detail based on Examples.

FIG. 2 is a block diagram for explaining the present invention in detail. In the figure, 201 to 203 are shift registers, 204 to 206 are sampling pulse generation circuits,
207 to 209 are reset clock signal lines, 21
0 is a video signal line, 211 to 219 are analog switches for sample and hold, and the above blocks constitute a data line driver. On the other hand, 229 to 231 are shift registers forming a scanning line driver. Further, 220 to 228 are data lines, 232 to 234 are scanning lines, and 255, 256, 237, etc. are pixels. FIG. 2 shows an example in which N data lines are driven by a one-stage shift register and a sampling pulse generation circuit.

Figure 3 shows a specific embodiment of the present invention. This embodiment is also an example in which N data lines are driven by a one-stage shift register. In the figure, 301 is a shift register;
Its output terminal is P type TIl'T302.303,304
and reset clock signal lines 514, 515.
, 516 are N-type TFTs 506, 508, and 31, respectively.
Connected to the gate of 0. TIFT302~510
Output terminals 517, 318, and 319 of the sampling pulse generation circuit configured by are connected to control terminals of sample and hold analog switches 311, 312, and 315, respectively. Further, 520 and 521 are respectively the piezoelectric power source and the negative power source of the sampling pulse generation circuit, and 522 is the
This is a video signal line. FIG. 4 is a diagram for explaining the operation of the embodiment of FIG. 3. In FIG. 4, 4o1 is the transfer lock of the shift register 501, 405 is the transfer data of the shift register 301, 402.40!1,40
4 are reset clock signals transmitted by 314, 315, and 316 in FIG.
8 is a timing chart of sampling pulses output to terminals 317, 318, and 319 in FIG. 3, respectively. First, at the falling point 409 of the shift register output,
P type T]l'T502 to 504-1); Turn off and turn off N type T
The sampling pulses 406, 407, and 408 are set to high level by the 1FTs 305, 507, and 609 being O]FIr. Next, at the time of 41o, the shift register output falls and TPT302.305.504 becomes 01F1r, and '1'lF'l'505.307.50
9 turns ON, the reset clocks 402, 40
5.404 (7) TFT506, 30 respectively at the rising edge
8.310 turns ON, sampling pulses 406, 407, and 408 are sequentially reset to low level at timings 410, 411, and 412. The analog switches 511, 312, 313 in FIG.
By configuring the sampling pulse to turn ON when it is high and turn 0IFF when it is low, the sample hold of the video signal can be set to 410, 411 . 412,413
, 414, . . . . As described above, according to the present invention, N data lines can be driven by a negative stage shift register. however,
K is the number of outputs of one sampling pulse generation circuit.

In the above-mentioned embodiments, the pulse width T of the sampling pulse is different as shown in FIG. 4Q6, 407, and 408. If the on-resistance of the analog switch constituted by T7T is not sufficiently low, display unevenness may occur on the active matrix panel due to the difference in pulse width of the sampling pulse.

An example in which the pulse widths of all sampling pulses are made equal is shown in Figure @5. This embodiment has a structure in which P-type transistors 501, 502, and 505 are added to the sampling pulse generation circuit in the embodiment shown in FIG. In FIG. 5, the same reference numerals as in FIG. 3 mean the same things as explained in FIG. FIG. 6 is a diagram for explaining the operation of the embodiment shown in FIG. 5. In the figure, numerals 401 to 405 mean the same things as 401 to 405 in FIG. Also, 601.602
, 605 are terminals 317, 318, 31 of groove 5, respectively.
FIG. 9 is a timing diagram of sampling pulses in FIG.

In FIG. 5, the output terminal 52 of the shift register 501
During the period when the low level is being output to
Sampling pulses 601, 602, 603 are set to high level as clock signals 404, 402, 403 applied to the gates of 502, 503 fall in sequence. Next, the shift register □After the output terminal 323 of the raster 301 rises from low level to high level, N
The sampling pulses 601, 602, and 603 are reset to low level as the clock signals 402, 405, and 404 applied to the gates of the type TPTs 306, 308, and 510 fall in sequence. By performing the same operation in all bits of the shifter register, the video signal is sampled and held using sampling pulses of equal pulse width T.

〔effect〕

As mentioned in the prior art section, TPTs made of polycrystalline silicon, amorphous silicon, etc. are monocrystalline silicon FTs! Its characteristics are inferior to JT, especially its ON resistance is high. For this reason, the shift register built into the thin film active matrix panel has a limited operating speed. According to the present invention, the shift register is required to be provided with a means for driving N data lines by a seven-stage shift register and a sampling pulse generation circuit for each stage of the shift register. The operating speed can be lowered to that of the conventional i.

Furthermore, according to the present invention, the number of stages of the shift register is smaller than that of the conventional i.
Instead, as shown in Figure 3 and glIE5,
Since a sampling pulse generation circuit composed of 5 to 4 T7Ts is used per stage, the number of TPTs constituting the driver as a whole is reduced. Therefore, the area occupied by the driver portion is reduced, manufacturing yield is improved, and power consumption is further reduced.

According to the present invention, the above-mentioned remarkable effects are brought to an active matrix panel with a built-in driver.

[Brief explanation of the drawing]

FIG. 1 is a diagram for explaining the prior art. FIG. 2 is a block diagram of an embodiment of the present invention. FIG. 5 is a diagram showing an embodiment of the present invention. FIG. 4 is a diagram for explaining the effect of FIG. 5. FIG. 5 shows another embodiment of the present invention. FIG. 6 is a diagram for explaining the operation of FIG. 5. Figure 2 Ward ゛ 0 To the sect, Akira ^

Claims (1)

[Claims] In an active matrix panel with a built-in driver, which includes a pixel section made up of thin film transistors arranged in a matrix and a driver section made up of thin film transistors, the output signal and phase of a shift register with a number of stages smaller than the number N of data lines is 1. An active matrix panel with a built-in driver, comprising a data line driver having means for generating sampling pulses for N data lines, which are set and reset by a plurality of different external clock signals.