JPS6148797B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention provides easy and reliable series connection in thin film solar cell panels that form a single substrate;
The present invention relates to a thin film solar cell device that can provide high output voltage and obtain high panel efficiency due to reduction in series resistance loss.

One way to reduce the cost of power solar cells is to use large-area wafers, from 3-inch wafers to 4-inch wafers, and then 5-inch wafers, in order to reduce process costs by using silicon single crystals. . in this case,
The optimal operating voltage of silicon crystal solar cell elements in AMO is constant at 0.40 to 0.55V, and the optimal operating current is 30 to 50 mA/cm ² per unit area, so 4-inch wafers (area 81 cm ² ) and 5-inch Each wafer (area 127cm ² ) is 2400 to 4000m.
A/sheet, 3800 to 6300 mA/sheet, which is an extremely large current, and unless the series resistance of the element is made considerably small, the power loss due to this series resistance cannot be ignored.
If the series resistance is to be reduced, the ratio of the electrode area to the light-receiving area (electrode area occupancy) will actually increase, leading to a decrease in the effective photoelectric conversion efficiency of the solar cell element. One possible solution to this problem is to take out a plurality of lead wires from the light-receiving surface side electrode and interconnect the solar cell elements, but this leads to an increase in connection wiring costs. Furthermore, in consumer solar cells, in order to obtain an arbitrary high output voltage, it is necessary to connect a plurality of solar cell elements in series because the operating voltage of a unit solar cell element is constant at 0.25 to 0.5V.

The present invention was made in view of the problems of increased electrode area occupancy, increased mutual wiring cost, and series connection to obtain a predetermined output voltage in the conventional devices, and is a feature of thin-film solar cells. This takes advantage of the fact that the thickness of the thin film semiconductor layer is 1 to 10 μm, which is about one hundredth of that of a silicon crystal solar cell, and the high lateral spreading resistance of the thin film.
In other words, in a plurality of thin film solar cell elements connected in series on a single substrate and having reverse p-n junction structures, the intrinsic semiconductor thin film layers or high resistivity semiconductor thin film layers of adjacent elements are connected in a continuous common manner. Each pair of p-type layer and n-type layer with an inverse structure formed on both sides of this common semiconductor layer is configured without physical separation, and is electrically connected in series, and the electrode area occupation rate is The objective is to provide a small, low-process, low-cost, high-reliability thin-film solar cell. Here, a set of solar cell elements in which the p-n junctions have an inverted structure means that the elements are laminated in the order of p-i-n on the substrate on which the elements are provided, and the elements have an n-i-p structure. , also p
-nn for elements stacked in the order of n-n
The -p structures each have an inverted structure, and the PN junctions are formed in a symmetrical relationship with each other.

First, using Figure 1, connect the
Thin film solar cell element with reverse p-n junction structure p ⁺ −i−n ⁺
It is electrically proven that there is no need to completely physically and mechanically separate the structural element and the n ⁺ −i−p ⁺ structural element, that is, there is no problem in operation even when the semiconductor layers are connected. will be explained in detail. In Fig. 1, a thin film solar cell element 1 having an n ₁ ⁺ -i ₀ -p ₁ ⁺ stacked structure and a thin film solar cell element 1 having a p ₂ ⁺ -i ₀ -n ₂ ⁺ stacked structure have an intermediate intrinsic semiconductor thin film layer. Alternatively, the high resistivity semiconductor thin film layer i ₀ is used in common, and the p-n junctions are formed in reverse structures. Between the two adjacent elements, the third layer is formed by continuously forming the _p1 layer and _n2 layer of the adjacent element via the boundary B without mechanically dividing, while the _n1 layer and p2 layer of the first layer _{The two} layers are separated by a distance l.

In the thin film solar cell having the above structure, the electrical conductivity of the intrinsic semiconductor thin film layer or the high resistivity semiconductor thin film layer i ₀ is σ ₀ and the film thickness is t ₀ , and the electrical conductivity of the p ₁ ⁺ thin film layer is σp ₁ and the film thickness If tp ₁ is the gap between the n ₁ ⁺ thin film layer and the p ₂ ⁺ thin film layer, the depth is w cm, and the photogenerated voltage by the n ₁ ⁺ −i ₀ −p ₁ ⁺ structural element is Evolt, then the gap l is The maximum voltage across both ends is 2Evolt. The leakage current j ₀ (A) at the boundary B between the p ₁ thin film layer and the n ₂ thin film layer is the width of the area where the lateral leakage current is acting at the boundary B between the p ₁ thin film layer and the n ₂ thin film layer. When △l, J ₀ <E (voltage) x w (length) x (conductivity) x (thickness)/(width) =E・w・(σ _p1・t _p1 /△l+σ _o2・t _o2 /
Δl) =E・(w/Δl)(σ _p1 t _p1 +σ _o2 t _o2 ) can be calculated. For example, in the case of amorphous silicon produced by glow discharge of SiH ₄ /H ₂ gas, E<1 volt, σp ₁ <10 ^-1 /Ωcm, σn ₂ <
1/Ωcm, tp ₁ <300Å=3×10 ^-6 cm, tn ₂ <300Å
= 3×10 ^-6 m ² , so σp ₁ tp ₁ +σn ₂ tn ₂ <
10 ^-1 × 3 × 10 ^-6 + 1 × 3 × 10 ^-6 = 3.3 × 10 ^-6 , and if w = 1 cm, J ₀ (μA) < 1 × 1/△l × 3.3
× 10 ^-6 ×10 ⁶ = 3.3/△l, that is, △l>10μm = 10 ^-3 cm
Then, it is calculated that J ₀ (μA)<1000μA (1mA). The photogenerated current of power solar cells is 30~50mA/
cm ² , even a value of J ₀ <1 mA is not so large as to deteriorate the characteristics of the element. Furthermore, the p ₁ ⁺ layer and the n ₂ ⁺ layer are electrically connected through a highly conductive layer, but especially in the case of amorphous silicon, the junction between the p ₁ ⁺ layer and the n ₂ ⁺ layer exhibits ohmic properties and has no rectifying properties. does not indicate. Furthermore, as shown in FIG. 1, the p ₁ ⁺ layer and the n ₂ ⁺ layer are
Since they are connected by , and have almost equal potential, the value of E in the above equation for leakage current J ₀ (A) is not 1 volt but less than one-tenth of it.
After all, as long as σp ₁ , σn ₂ ≫σ ₀ , σp ₁ .tp ₁ and σ
The value of n ₂ .tn ₂ becomes very small, the leakage current at boundary B is negligible, and even if the p ₁ ⁺ layer and n ₂ ⁺ layer are formed as a continuous semiconductor thin film layer, there is no electrical connection at electrode 3. There is no problem even if it happens. Furthermore ^, the p ₁ ⁺ layer and the n ₂ ⁺ layer do not need to be formed adjacently as the same thin film _{semiconductor} layer as shown in the figure, and as shown in FIG. Even if the shape covers a part of the p ₁ ⁺ layer (and vice versa), there is no problem as long as the boundary between the p ₁ ⁺ layer and the n ₂ ⁺ layer is located between the gap l. Furthermore, there is no problem even if the p ₁ ⁺ layer and the n ₂ ⁺ layer are separated by a minute gap (≪l).

Next, the above p ₁ ⁺ layer via the intrinsic semiconductor thin film layer i ₀ ,
For the n ₁ ⁺ layer and p 2 ⁺ layer opposite to the n ₂ + layer, the relationship between _{n 1 +} ⁻ⁱ ₀ −p ₁ ⁺ structural element 1 and p ₂ ⁺ −i ₀ −n ₂ ⁺ structural element ² is The current i flowing through the boundary region 4 generated in the intrinsic semiconductor thin film layer i ₀ becomes the maximum leakage current between a pair of reversely structured elements. The maximum voltage, which is the sum of the photogenerated voltages by the two elements, is applied between the bottom ends of the boundary region 4 on both sides (the part indicated by the broken line) of these two elements.
2Evolt is applied, and the top of the boundary region 4 is electrically connected by the highly conductive layer (p ₁ ⁺ , n ₂ ⁺ ) as described above, and when it is made of amorphous silicon, p ₁ ⁺ , The current in the n ₂ ⁺ junction is mostly ohmic and does not exhibit any rectifying properties. Therefore
There is almost no potential difference between p ₁ ⁺ and n ₂ ⁺ , a value close to zero, so that at the top of the boundary region 4 the voltage difference is practically zero, and the potential difference on both sides of the boundary region 4 is It is a value obtained by dividing the maximum voltage 2Evolt by the thickness t ₀ of the intrinsic semiconductor layer i ₀ , and for example, the potential difference at a position where the thickness from the top of the boundary region 4 is x is (2Ex/t ₀ ).

Therefore, the leakage current △J between the two elements at this point is So, the total leakage current is becomes.

As a result, it can be seen that when l2E×(W/J)σ ₀ ·t ₀ , the maximum leakage current is J.

Specifically, E<1 volt, W=1 cm, σ ₀ <
10 ^-4 /Ωcm, t ₀ = 1 μm = 10 ^-4 cm, J < 200 μA =
2×10 ^-4 A, then l>2E(w/i)σ ₀ t ₀ =10 ^-4 cm = 1 μm, that is, if the gap l between elements is selected to be 1 μm or more, the leakage current is This indicates that the leakage current can actually be reduced to 2 μA or less if l is selected to be 100 μm or more. Although the value of l may vary depending on the growth technique of the thin film semiconductor layer, the leakage current is very small within the range where normal growth techniques are applied, and the influence on the operation of the solar cell element is very small. Also, it is the value of the electrical conductivity σ ₀ of the intrinsic semiconductor layer i ₀ for AM2100mW/cm ² input,
In the dark, σ ₀ is 10 ^-7 to 10 ^-8 /Ω due to the photoconductive effect.
Since the leakage current is drastically reduced to about cm, the leakage current becomes even smaller. Therefore, by shielding the light-receiving area corresponding to the boundary area 4 that provides the above-mentioned l from light in advance, the electrical isolation effect can be further enhanced.

Next, an element with an n ₁ ^{+ −i} ₀ −p ₂ ⁺ structure is considered to be composed of the n ₁ + layer, the i ₀ layer, and the p ₂ ⁺ layer, but as mentioned above, the horizontal distance between the boundary regions 4 The length of l is n ₁ ⁺
If the diffusion length Ln of electrons and holes photogenerated at the junction of −i ₀ −p ₂ ⁺ is larger than twice Lp, that is, l>
For 2Ln and 2Lp, the above n ₁ ⁺ layer − i ₀ layer − boundary region 4
A solar cell composed of −i ₀ layer − p ₂ ⁺ layer practically does not generate electromotive force, and both n ₁ ⁺ layer − i ₀ layer and p ₂ ⁺ layer − i ₀ layer are electrically independent. . Specifically, in the case of amorphous silicon, since Ln and Lp<0.5 μm, it is sufficient that l>1 μm, that is, l is 1 μm or more. FIG. 3 shows a state in which a large number of sets of thin film semiconductor solar cell elements having the opposite structure shown in FIG. 1 are provided on the same substrate 20 and electrically connected to each other in series. A plurality of solar cell elements connected in series are all formed using an intrinsic semiconductor thin film or a high resistivity layer in common. In the above embodiment, a single p ⁺ −i−n ⁺ −(p ⁺
−n ⁻ −n ⁺ ) structure, but in the case of a multi-layered solar cell that has been developed to obtain high output, for example, a transparent electrode 5 is used between the solar cell elements stacked as shown in FIG. Device inserted with
The present invention can be similarly applied to a device in which layers are stacked without using a transparent electrode as shown in the figure.

A specific method for manufacturing a high output voltage thin film solar cell panel according to the present invention is shown in FIGS. 6a to 6e.

In FIG. 6a, reference numeral 21 denotes a glass substrate (borosilicate glass), on which a 1TO (In ₂ O ₃ -SnO ₂ ) transparent conductive film 22 is deposited at intervals of 0.20 mm or less using an ion plating device at a substrate temperature of 200 to 450°C. Film thickness 0.10~
Form a 0.15μm mask. The sheet resistance of the 1TO film 22 at this time is 10Ω/mouth or less. Glass substrate 2
1 also serves as a constituent material on the light-receiving surface side of the solar cell panel. Next, monosilane (SiH ₄ ) was added to the hydrogen gas base.
The raw material is a mixture of gas (SiH ₄ /H ₂ ) with 10% addition and a small amount of phosphine (PH ₃ /H ₂ ) gas added.
By low-pressure glow discharge, an n ₁ ⁺ amorphous silicon thin film layer (100 to 300 Å thick) is formed in the form of islands on the substrate using a mask 23 as shown in FIG. 6b. In this case, the gas pressure is 0.5~5torr, and the substrate temperature is 250~300
Perform at °C. Next, using a raw material prepared by adding a small amount of diborane (B ₂ H ₆ /H ₂ ) gas to SiH ₄ /H ₂ gas,
As shown in FIG. 6c, a p ₁ ⁺ amorphous silicon thin film layer (100-200 Å thick) positioned relative to the island region of the n ₁ ⁺ thin film layer is formed. The mask 23 used for positioning when forming the p ₁ ⁺ layer is obtained by translating the mask 23 used for forming the n ₁ ⁺ layer. Since it is a low-pressure glow discharge, there is some leakage from the sides of the mask, but this is not a problem because the film thickness is extremely thin. Next, an undoped amorphous silicon thin film layer i ₀ (5000 to 10000 Å thick) which becomes an intrinsic semiconductor layer or a high resistivity layer is formed over the entire surface of the p ₁ ⁺ layer and the n ₁ ⁺ layer. (Figure 6d) Furthermore
_n2 amorphous silicon thin layer (200-300 Å thick) followed by _p2 ⁺ amorphous silicon thin layer (100-200 Å thick)
thickness) is positioned between the n ₁ ⁺ layer and the p ₁ ⁺ layer. Next, an Ag to Al back electrode 24 (1 to 3 μm thick) is formed as a mask using an ion plating device (FIG. 6e). At this point, the thin-film solar panel is completed. 7th solar cell seen from the back
As shown in the figure. It has an extremely simple structure, and the effective element area is more than 95% of the substrate area.

As described above, according to the present invention, a solar cell element is formed through an intrinsic thin film semiconductor layer or a high resistivity layer, and the intrinsic thin film semiconductor layer or a high resistivity layer is formed through an intrinsic thin film semiconductor layer or a high resistivity layer without physically or mechanically dividing the series connected elements. By providing a common layer, it is possible to create thin-film solar panels with an arbitrary high output voltage at an extremely low cost compared to the conventional method in which each element is physically separated and then electrically connected in series. This solves all of the problems such as increased electrode area occupancy, increased power loss due to electrode resistance, and increased phase-to-series wiring costs, resulting in highly reliable and highly efficient thin-film solar cell panels. Further, according to the present invention, one conductive region of a unit solar cell element formed on both sides with a common layer between the p-type region and the n-type region of a pair of adjacent solar cell elements. Since they are formed continuously and integrally without being physically separated, there is no wasted light-receiving area of the semiconductor layer, and a high-efficiency thin-film solar cell panel that can obtain large amounts of power is provided. It is.

[Brief explanation of the drawing]

Figure 1 is a principle diagram for explaining the present invention, Figure 2
The figure is a sectional view of a main part showing another embodiment according to the present invention.
FIG. 3 is a cross-sectional view showing one embodiment of the present invention, FIGS. 4 and 5 are cross-sectional views showing other embodiments of the present invention, and FIGS. A sectional view for explaining the method, Figure 7 is Figure 6e
FIG. 1: n ₁ ⁺ −i ₀ −p ₁ ⁺ thin film solar cell element, 2: p ₂ ⁺
−i ₀ −n ₂ ⁺ thin film solar cell element, 3: electrode, 20:
substrate.

Claims (1)

[Claims] 1. In a thin film solar cell device in which a plurality of unit solar cell elements formed by laminating amorphous thin film semiconductor layers are connected in series on a single substrate, one side from the substrate side is in the order of pins. and the other is laminated in the order of nip, and the i-layers of the adjacent solar cell elements are formed into a continuous common layer, and the conductive regions of one of the unit solar cell elements formed on both sides are connected via the common layer. , the p-type region and n-type region of one pair of adjacent solar cell elements are continuous and integrally formed without physically separating them, and the p-type region and n-type region of the other pair of solar cell elements are formed integrally. The mold region is formed physically separated from the mold region, and the other conductive region corresponding to one conductive region of the unit solar cell element formed on both sides via the common layer is connected to the adjacent pair of conductive regions. The n-type region and the p-type region of the solar cell element are physically separated and formed, and the n-type region and the p-type region of the other pair of solar cell elements are made to be continuous without being physically separated. A p-type region and an n-type region formed integrally and physically continuous between unit solar cell elements adjacent in the spreading direction of the substrate and physically continuous with each other in the pair of adjacent solar cell elements.
A thin film solar cell device characterized in that the solar cells are connected in series by electrodes integrally formed on a mold region. 2. The thin film solar cell device according to claim 1, wherein the unit solar cell element is formed by stacking a plurality of solar cell elements in the stacking direction of the thin film semiconductor layers.