JPS6148297B2 - - Google Patents
Info
- Publication number
- JPS6148297B2 JPS6148297B2 JP52107514A JP10751477A JPS6148297B2 JP S6148297 B2 JPS6148297 B2 JP S6148297B2 JP 52107514 A JP52107514 A JP 52107514A JP 10751477 A JP10751477 A JP 10751477A JP S6148297 B2 JPS6148297 B2 JP S6148297B2
- Authority
- JP
- Japan
- Prior art keywords
- frequency
- output
- voltage
- circuit
- frequency divider
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 239000013078 crystal Substances 0.000 description 6
- 239000004020 conductor Substances 0.000 description 5
- 238000005259 measurement Methods 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 230000010355 oscillation Effects 0.000 description 2
- 239000003990 capacitor Substances 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 238000001514 detection method Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000007599 discharging Methods 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
Description
【発明の詳細な説明】
本発明は分周器の出力周波数調整装置に関する
ものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an output frequency adjusting device for a frequency divider.
一般に水晶時計の緩急調整は、水晶発振器の外
付けコンデンサの容量を調整し、その発振周波数
を調整していた。 Generally, the speed and speed of a crystal clock is adjusted by adjusting the capacitance of the external capacitor of the crystal oscillator and adjusting its oscillation frequency.
ところがこれによると湿度による影響とか経時
変化によつて発振周波数が変動するという欠点が
あつた。 However, this method had the disadvantage that the oscillation frequency fluctuated due to the influence of humidity or changes over time.
また上記の他に分周器への入力パルスを所望の
周期で１パルスずつ除去するものがある。これは
上記入力パルスを受けるカウンタ等を具備した制
御回路から数本の制御端子を導出し、各制御端子
を選択的に“１”および“０”に設定して、パル
スを除去する上記所望の周期を設定するものであ
つた。これによると分周器および制御回路を集積
化したとき、数本の制御端子を導出しなければな
らず不都合であつた。また各端子を“１”および
“０”のいずれかに固定するため、はんだ付を行
なわなければならず、煩雑であつた。 In addition to the above, there is a method that removes input pulses to the frequency divider one pulse at a desired period. This is done by deriving several control terminals from a control circuit equipped with a counter etc. that receives the input pulses, and selectively setting each control terminal to "1" and "0" to eliminate the pulses. It was used to set the cycle. According to this, when the frequency divider and the control circuit are integrated, several control terminals must be led out, which is inconvenient. Further, in order to fix each terminal to either "1" or "0", soldering had to be performed, which was complicated.
そこで本発明は一本の端子に印加する電圧を調
整することにより分周器の出力周波数を制御する
ようにし、従来の欠点を除去するものである。 Therefore, the present invention eliminates the conventional drawbacks by controlling the output frequency of the frequency divider by adjusting the voltage applied to one terminal.
以下本発明の一実施例を図面に基づいて説明す
る。第１図において１は水晶発振器、２は分周
器、３はカウンタ、４はデコーダであり、本例で
はその出力端子P1……Ｐoはカウンタ３がそれぞ
れ104，２×104……２n-1×104パルスをカウント
すると順次“１”に反転するように設定してあ
る。５は第１の手段を構成する比較回路、６はゲ
ート回路であり、これとカウンタ３およびデコー
ダ４とにより制御手段を構成するものである。
D1……Ｄoはダイオード、R1……Ｒo-1は抵抗であ
り、これらにより変換手段を構成するものであ
る。以上の構成は水晶発振器１の一部を除いて集
積化してある。７は分周器２の出力パルスの周波
数を計測する計測回路、８は設定回路であり、所
望の周波数値を設定してある。９は比較回路であ
り、これと計測回路７および設定回路８とにより
検出手段を構成する。１０は充電回路を構成する
積分回路、１１は電圧レベルコンバータである。
１２はスタートスイツチ、Rnは抵抗である。 An embodiment of the present invention will be described below based on the drawings. In FIG. 1, 1 is a crystal oscillator, 2 is a frequency divider, 3 is a counter, and 4 is a decoder. In this example, the output terminals P 1 ... P o of the counter 3 are 10 4 and 2×10 4 , respectively. ...It is set so that it is sequentially inverted to "1" after counting 2 n-1 ×10 4 pulses. Reference numeral 5 designates a comparison circuit constituting the first means, and reference numeral 6 denotes a gate circuit, which together with the counter 3 and decoder 4 constitute the control means.
D 1 . . . D o is a diode, R 1 . . . R o-1 is a resistor, and these constitute a conversion means. The above configuration is integrated except for a part of the crystal oscillator 1. 7 is a measuring circuit for measuring the frequency of the output pulse of the frequency divider 2, and 8 is a setting circuit, in which a desired frequency value is set. Reference numeral 9 denotes a comparison circuit, and this together with the measurement circuit 7 and setting circuit 8 constitute a detection means. Reference numeral 10 represents an integrating circuit constituting the charging circuit, and reference numeral 11 represents a voltage level converter.
12 is a start switch, and Rn is a resistor.
第２図および第３図はダイオードD2の出力と
抵抗R1，R2間の交点Ａを示したものである。同
図において１３はダイオードD2に接続した導電
体膜、１４は絶縁体膜、１５は抵抗R1，R2を構
成する抵抗体膜である。抵抗体膜１５と導電体膜
１３間の電位差がν0Vに達したとき導電体膜１
３の狭幅部１３ａが破壊されるように設定してあ
る。 FIGS. 2 and 3 show the intersection A between the output of diode D 2 and resistors R 1 and R 2 . In the figure, 13 is a conductor film connected to the diode D 2 , 14 is an insulator film, and 15 is a resistor film forming resistors R 1 and R 2 . When the potential difference between the resistor film 15 and the conductor film 13 reaches ν 0 V, the conductor film 1
The narrow portion 13a of No. 3 is set to be destroyed.
なお他のダイオードの出力と抵抗間との交点も
上記と同様に構成してある。 Note that the intersections between the outputs of other diodes and the resistors are also configured in the same manner as above.
つぎに動作について説明する。 Next, the operation will be explained.
まず初期状態においては、比較回路５からダイ
オードD1……Ｄoを介して電流が流れており、各
端子q1……ｑoは“０”に保持されているものと
する。そこでスタートスイツチ１２を閉成して積
分回路１０の充電を開始させる。これによりその
出力電圧が徐々に上昇し、電圧レベルコンバータ
１１の出力電圧も上昇する。そして電圧レベルコ
ンバータ１１の出力電圧がν0Vにまで上昇する
とダイオードD1に接続した導電体膜の狭幅部が
破壊され、ダイオードD1の出力とアース間が電
気的に遮断される。そのため比較回路５の端子q1
が“１”に反転する。したがつてカウンタ３が１
０４パルスをカウントしたとき、デコーダ４の出
力端子p1……ｐoと比較回路５の端子q1……ｑoの
電圧レベルがそれぞれ一致する。すなわちカウン
タ３が、１０４パルスをカウントするごとに比較
回路５からは“０”のパルスが生じ、ゲート回路
６を閉じて水晶発振器１からの出力パルスを１パ
ルスだけ除去するように設定してある。 First, in the initial state, it is assumed that current flows from the comparator circuit 5 through the diodes D 1 ...D o , and each terminal q 1 ...q o is held at "0". Then, the start switch 12 is closed to start charging the integrating circuit 10. As a result, its output voltage gradually increases, and the output voltage of the voltage level converter 11 also increases. When the output voltage of the voltage level converter 11 rises to ν 0 V, the narrow portion of the conductive film connected to the diode D 1 is destroyed, and the output of the diode D 1 is electrically cut off from the ground. Therefore, terminal q 1 of comparison circuit 5
is inverted to “1”. Therefore, counter 3 is 1
When 0 4 pulses are counted, the voltage levels of the output terminals p 1 . . . p o of the decoder 4 and the terminals q 1 . That is, it is set so that every time the counter 3 counts 104 pulses, a "0" pulse is generated from the comparator circuit 5, and the gate circuit 6 is closed to remove only one pulse from the output pulse from the crystal oscillator 1. be.
こうして調整された分周器２の出力パルスの周
波数が計測回路７で計測され、この周波数が設定
回路８に設定した所望の周波数と異なるとき比較
回路９の出力は“０”に保持され、積分回路１０
は充電を継続し、電圧レベルコンバータ１１の出
力電圧は上昇を続ける。そして交点Ａにおける導
電体膜１３の狭幅部１３ａと抵抗体膜１５間の電
圧がν0Vに達すると、狭幅部１３ａが破壊さ
れ、比較回路５の端子q2が“１”に反転する。し
たがつてカウンタ３が２×104パルスをカウント
するごとに水晶発振器１からの出力パルスが１パ
ルス除去される。 The frequency of the output pulse of the frequency divider 2 thus adjusted is measured by the measurement circuit 7, and when this frequency differs from the desired frequency set in the setting circuit 8, the output of the comparison circuit 9 is held at "0", and the integral circuit 10
continues charging, and the output voltage of the voltage level converter 11 continues to rise. When the voltage between the narrow part 13a of the conductor film 13 and the resistor film 15 at the intersection A reaches ν 0 V, the narrow part 13a is destroyed and the terminal q 2 of the comparator circuit 5 is inverted to "1". do. Therefore, one output pulse from the crystal oscillator 1 is removed every time the counter 3 counts 2×10 4 pulses.
こうして分周器２の出力パルスの周波数が所望
の周波数に一致するまで順次ダイオードD3……
Ｄoの出力側の導電体膜の狭幅部が破壊されてい
く。そして分周器２の出力パルスの周波数が所望
の周波数になると、比較回路９の出力が“１”に
反転し、積分回路１０の充電電荷が放電され、調
整が終了する。 In this way, the diode D 3 .
The narrow portion of the conductor film on the output side of D o is being destroyed. When the frequency of the output pulse of the frequency divider 2 reaches a desired frequency, the output of the comparison circuit 9 is inverted to "1", the charge in the integration circuit 10 is discharged, and the adjustment is completed.
以上詳述したごとく本発明によれば、設定手段
の入力端子の電位を選択的に放電破壊していくこ
とにより分周器の出力周波数を調整し、所望周波
数になつたときに放電破壊を停止するようにした
ので、ROM等の複雑な回路を必要とせず、自動
的に分周器の出力周波数を調整でき人手を煩わせ
ることがない。 As described in detail above, according to the present invention, the output frequency of the frequency divider is adjusted by selectively discharging and destroying the potential of the input terminal of the setting means, and when the desired frequency is reached, the discharge breakdown is stopped. As a result, the output frequency of the frequency divider can be automatically adjusted without the need for a complicated circuit such as a ROM, and without the need for human intervention.
第１図は本発明の一実施例を示した電気回路
図、第２図は第１図の一部の具体的な構成を示し
た正面図、第３図は第２図の―線断面図であ
る。
２……分周器、３……カウンタ、４……デコー
ダ、５……比較回路、６……ゲート回路、７……
計測回路、８……設定回路、９……比較回路、１
０……充電回路、D1〜Ｄo……ダイオード、R1〜
Ｒo-1……抵抗。
Fig. 1 is an electric circuit diagram showing an embodiment of the present invention, Fig. 2 is a front view showing a specific configuration of a part of Fig. 1, and Fig. 3 is a sectional view taken along the line - - of Fig. 2. It is. 2... Frequency divider, 3... Counter, 4... Decoder, 5... Comparison circuit, 6... Gate circuit, 7...
Measuring circuit, 8... Setting circuit, 9... Comparing circuit, 1
0...Charging circuit, D1 ~D o ...Diode, R1 ~
R o-1 ...Resistance.
Claims (1)
上昇する電圧発生回路と、 この電圧発生回路の出力に一端を接続してあ
り、他端を所望の電位に保持した抵抗体膜と、 複数の入力端子のそれぞれをダイオードおよび
設定電圧で破壊される導電体膜を介して所望の電
位端子に接続した第１の手段と、 上記導電体膜と上記抵抗体膜との間のそれぞれ
に介在させた絶縁体膜と、 基準周波数を分周する分周器と、 第１の手段の上記入力端子の電位に応じて上記
分周器の出力周波数を調整する制御手段と、 この分周器の出力周波数を計測する計測手段
と、 目標周波数値を設定する設定手段と、 上記計測手段による計測値と上記目標周波数値
とを比較する比較手段とからなり、 この比較手段から一致出力が発生したときに上
記電圧発生回路からの出力電圧を停止することを
特徴とする分周器の出力周波数調整装置。[Claims] 1. A voltage generating circuit that gradually increases the output voltage upon arrival of a start command; and a resistor whose one end is connected to the output of the voltage generating circuit and whose other end is held at a desired potential. a first means connecting each of the plurality of input terminals to a desired potential terminal via a diode and a conductive film that is destroyed by a set voltage; an insulating film interposed between each, a frequency divider that divides the reference frequency, a control means that adjusts the output frequency of the frequency divider according to the potential of the input terminal of the first means, and a frequency divider that divides the reference frequency; It consists of a measuring means for measuring the output frequency of the frequency generator, a setting means for setting a target frequency value, and a comparing means for comparing the measured value by the measuring means with the target frequency value, and a matching output is obtained from the comparing means. An output frequency adjustment device for a frequency divider, characterized in that the output voltage from the voltage generation circuit is stopped when the voltage generation circuit occurs.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10751477A JPS5440547A (en) | 1977-09-07 | 1977-09-07 | Device for adjusting output frequency of frequency divider |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10751477A JPS5440547A (en) | 1977-09-07 | 1977-09-07 | Device for adjusting output frequency of frequency divider |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5440547A JPS5440547A (en) | 1979-03-30 |
| JPS6148297B2 true JPS6148297B2 (en) | 1986-10-23 |
Family
ID=14461123
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP10751477A Granted JPS5440547A (en) | 1977-09-07 | 1977-09-07 | Device for adjusting output frequency of frequency divider |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5440547A (en) |
Families Citing this family (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| IL56265A (en) * | 1977-12-28 | 1982-08-31 | Om Lab Sa | Process for preparing imidazolyl methylthio guanidine derivatives and a novel intermediate therefor |
| LU81178A1 (en) * | 1978-05-12 | 1979-09-10 | Crc Ricerca Chim | NEW THIOLD DERIVATIVES OF IMIDAZOLE |
| YU41689B (en) * | 1980-01-14 | 1987-12-31 | Lek Tovarna Farmacevtskih | Process for preparing imidazole derivatives |
| JPS59130274A (en) * | 1983-01-14 | 1984-07-26 | Tokawa Tetsuo | Preparation of imidazole compound |
| JPS59130273A (en) * | 1983-01-14 | 1984-07-26 | Tokawa Tetsuo | Preparation of imidazole compound |
-
1977
- 1977-09-07 JP JP10751477A patent/JPS5440547A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5440547A (en) | 1979-03-30 |
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