SU866707A1 - Pulse generator - Google Patents

Description

(54) GENERATO PULSES

Claims (2)

The invention relates to a pulse technique and can be used as a master oscillator in analog digital devices. A generator of rectangular pulses is known, containing an R $ -trigger, the current RC circuit, and input AND NAND logic gates, whose outputs are connected to RS setup inputs — a trigger .; However, this generator does not provide frequency stability when changing HanpsH power supply. The closest solution to the proposed one is a pulse generator containing I-41E element and time setting RC - circuit 1 ,. A disadvantage of the known device is the low stability of the pulse frequency. The purpose of the invention is to increase the stable pulse frequency. The set of tset is achieved by the fact that the R6 trigger is entered into the pulse generator containing three AND-NOT elements and the time specified by the RC circuit, 5 — the input of which is connected to the output of the first AND-NOT element whose input is connected to P — the trigger input The RC circuit and with the output of the third NAND element, the input of which is connected to the output. the house of the second NAND element, the output of the RS trigger is connected to the RC circuit and to the input of the third NAND logic element, and the counting trigger, the input of which is connected to the output of the new {NAND element. In the drawing Gfnveden | f incistive scheme of the pulse generator. The pulse generator contains the elements AND-NOT 1-3, time zakadnuyu RC ... circuit consisting of a resistor 4 and a condenser 5, RS-trigger 6. and counting trigger 7 with outputs 8 and 9. The pulse generator works as follows. Let at the given moment the timing of the direct output of the trigger 6 logical level, the capacitor 5 is discharged, at the second and the output of the AND-NE element 3 the logical level zero, at the output of the connector AND the NO-1 logic level, at the outputs 8 and 9 trigger 7 logic levels are set depending on the rate of relaxation processes in the trigger. The capacitor 5 charges the resistor 4. at the input of the element AND-HE 2 increases. When the potential threshold value is reached, the AND-HE 2 element opens, a logical zero is set at its output, and the logical one at the output of the AND-HE element 3. On the second output RS - the trigger enters a logical one, and on the first input through the element IS-NOT 1 - the level of logical zero. Trigger 6 abruptly changes the state and a logic zero level is set at its direct output. The voltage drop from the logical unit to zero at the input of the trigger 7 changes the values of the translations on (outputs 8 and 9 on the npoTHBonojKHbtei-iB this moment begins with over-discharge to the on-capacitor a 5, the potential at the input of the AND-NOT 2 element decreases and upon reaching the trigger threshold and its output, the logical logic level is set, and the E / Emment I-ffi 3 output is set to the logical nui level. Through the AND-NE I element, the voltage drop from the logical zero to the logical unit, u) is input to the trigger 7 and this trigger 7 does not change the state of the outputs. The output of trigger 6 sets the level of the logical unit. The process then repeats. When the supply voltage varies, the charging and discharging time of the capacitor 5 varies, but the pulse duration at the output of the AND-NE element 1 remains constant due to the fact that the total charging and discharging time of the capacitor remains constant. An inventive pulse generator comprising three AND-NES elements and a setting time, characterized in that, in order to increase the stability of the pulse-tracking frequency, RS is a trigger, the S-input of which is connected to the output of the first AND-NOT element whose input connected to R - trigger input, the time of setting RC izapyr and with the output of the third non-IS output, the input of which is connected to the output of the second AND-NOT element, with the output of the trigger connecting the jjjeH with the RC - and the input of the second element AND-NOT, and the counting trigger, whose input is soyugaen with the output of th NAND. Sources of information taken into account in the examination 1. USSR author's certificate number 496657, cl. H 03 K 3/02, 23.O6.73. 2. Gutnikeda V.S. Integral electronics in measuring devices. Energie, 1974, p. 112, Fig. W (b), (prototype).