JPS6148053A - Memory control device - Google Patents

Abstract

PURPOSE:To shorten a suppressing time by installing a circuit to prohibit new registration to a line designated by a cache memory, a circuit to sweep out data of a designated line and a memory access inhibit circuit from an input output control device. CONSTITUTION:A line designation new allocation prohibit bit 119 to prohibit that a line corresponding at the time of mishitting a cache memory 131 is a contrast to replacement, a sweeping-away control circuit 123 to sweep away cache memory data to a main memory device 201 of line unit by the request from a requesting party, and a sweeping-away row address counter 122 and an input output control device request reception inhibit bit 124 to inhibit a memory access to a memory control device 101 by an input output control device 401 when it is set are installed in the memory control device 101. Thus, a memory access suppressing time is shortened and a dynamic alteration processing of a system composition is improved.

Description

DETAILED DESCRIPTION OF THE INVENTION (Technical Field) The present invention relates to a memory control device, and in particular to a method for writing out cache memory data to a main memory device in an information processing system that is fully equipped with a cache memory system that uses a set-anonymous method and a store-swap method. The present invention relates to a memory control device according to the present invention.

(Prior Art) In large-scale information processing systems, the processing speed of the memory element for the main memory device has not been improved relative to the improvement in the processing speed of the arithmetic and control unit. In order to absorb the difference in processing speed between the two, there is a system in which a store-swap type cache memory is installed in the memory control device to shorten the average memory access time and improve the load on the main memory device. In a system with only a store-swap type cache memory, the latest memory data exists on the main memory device during operation, but in a system like the one described above with a store-swap type cache memory, depending on the memory data, the latest memory data exists on the main memory device. does not necessarily exist on the main memory device, but may exist only on the cache memory. Such non-currentness of main memory device data poses a major hindrance to dynamic changes in logical connections between devices in the system configuration. 1 to 3 show examples of connections between devices. Memory controller 101.10
2 is connected to main memory devices 201, 202, 203, 204, and further connected to arithmetic and control devices 301, 302, and input/output control devices 401, 402. Solid lines between devices are logical.

A broken line indicates a physically connected state but a logically disconnected state. All the devices shown in FIG. 1 are logically connected and operated as a so-called multiprocessor. The system shown in FIG. 2 is divided into two parts, and both are operated independently as a duplex system. Further, the memory control device 102 shown in FIG. 3 is in a disconnected state due to a failure or the like.

It is desirable that state changes between these system configurations be performed without affecting users who are using the system. Particularly when the system is used online, impacting the end users must be avoided.

In a system having a store-swap type cache memory in the memory control unit 101, 102, FIGS.
As shown in the figure, a configuration is generally adopted in which only one memory control device is logically connected to one main memory device.

As a result, even if the main memory device data is registered in the cache memory in the memory control device to which this main memory device is logically connected, it is not registered in the cache memory in the memory control device to which the main memory device is logically unconnected. Data between the cache memories becomes exclusive, and there is no need to control data interference between the two cache memories.

In such a configuration, for example, when transitioning from the system configuration of FIG. 3 to the system configuration of FIG. 1, the main memory device 203 logically connected to the memory control device 102 after the transition
, 204 exists on the cache memory in the memory control device 101, simply switching the logical connection relationship will not allow normal memory access to the main memory devices 203 and 204 after system configuration migration. do not have.

The following method can be used to transition from the system configuration shown in FIG. 3 to the system configuration shown in FIG. 1 without inconsistency in the latestness of memory data.

The first method is to stop the system once, change the logical connections between devices, and then restart the system starting with system initialization (main memory data continuity is not required). In this case, it takes a lot of time to complete restarting after stopping the system, which has a big impact on the users who are using the system.

The second method is to stop and suspend the processing of the arithmetic control units 301 and 302 at the command break, and also to suppress the start of new input/output operations. The cache memory data in the main memory is written out to the main memory device. Upon completion of this writing, the main memory device 203. The data in ``204'' becomes the latest state. After that, the logical connection relationship between the devices is changed and processing is restarted while maintaining the continuity of the main memory data.

Although this method does not affect the user as much as the first method, it still has a large impact on the user because it requires a considerable amount of time to wait for the input/output operation currently being executed to stop.

The third method is to stop and suspend the processing of the arithmetic control units 301 and 302 at each instruction break, and to inhibit and suspend the memory access processing of the memory control unit 101 while the input/output processing is in progress. When memory access is suppressed, the cache memory data in the memory control device 101 is flushed to the main memory device, and when the flushing is completed, the logical connection relationship between the devices is changed to maintain continuity of the main memory data. Leave it as it is and restart the process. With this method, system stoppage from the user's point of view is not much of a problem during the time it takes for cache memory data to be flushed to the main memory device. - There is a risk that frequent run and data overruns will not be able to be brought under control.

If the cache-memory arithmetic processing unit could process memory access from the input/output device normally while writing the cache memory data to the main memory unit, the above method would not be necessary. , when there is a memory access to cache memory data that has already been written to the main memory device, problems occur in processing. The same process as described above can be applied to transition between the seven-stem configuration shown in FIG. 1 and the system configuration shown in FIG.

As described above, such conventional systems have drawbacks such as the lack of means for effectively changing the system configuration.

(Objective of the Invention) An object of the present invention is to eliminate the drawbacks of conventional memory control devices, and also to eliminate the disadvantages of the last part of the cache memory in the process of flushing out cache memory data onto the main memory using the store swap method in the memory control device. Until the line flushing process begins, memory access by input/output processing is allowed for unexposed cache memory data,
Furthermore, by limiting new block allocation in the event of a cache memory miss to only unwritten lines, the present invention aims to reduce memory access suppression time due to input/output processing and improve dynamic change processing of the system configuration.

(Structure of the Invention) According to the present invention, a plurality of arithmetic control devices, a plurality of input/output control devices, a plurality of main memory devices, and a memory access request from the arithmetic control devices and the input/output control device to the main memory device. In the information processing system, the information processing system includes a plurality of memory control devices interposed between the memory control devices, and each memory control device includes a set associative type and store swap type cache memory shared by each of the arithmetic control units and input/output control units. , a circuit that specifies a row of the cache memory and prohibits new block registration to that row; a circuit that specifies a row of the cache memory and outputs the data of that row to the corresponding main memory device; A memory control device characterized in that it includes a circuit for inhibiting memory access from the input/output control device to the memory control device.

(Example) Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 4 shows an embodiment of the present invention. In FIG. 4, one embodiment of the present invention is connected to an arithmetic control device 301 and an input/output control device 401, and further connected to a main memory device 201, and is shared by each of the arithmetic control devices and input/output control devices. set associative method or store Swatzf.

Memory control device 101 having a cache memory of
a circuit 119 that specifies a row of the cache memory and prohibits new block registration to that row; and an output control circuit 1 that outputs data to the cache memory device 201.
23, and a circuit 124 for inhibiting memory access from the input/output control device 401 to the memory control device 101.

Historically, this memory control device 101 has a request reception port circuit 111 connected to the input/output control device 401,
126, a request reception port circuit 110, 127 connected to the arithmetic and control unit 301, and an output control circuit 1.
23, and the request reception port circuit 110, 111.12.
6.127 and the stage 1 request register 112 connected to the exposed column address counter 122, the stage 2 request register 113 connected to the stage 1 request register 112, and the stage 2 request register 113 connected to the stage 1 request register 112;
and a stage 3 request register 114 connected to request register 113 and whose output is further connected to main memory device 201 .

Stage 1 request register 112 includes write data raster 115 . The row designation new allocation prohibition bit 119 . It is connected to the output control circuit 123 and the input/output control device request reception suppression bit 124. The row designation new allocation prohibition bit 119 is connected to the replacement circuit 132. Extrusion control circuit 1
23 is connected to the arithmetic control device, and the input/output control device request reception suppression bit 124 is connected to the input/output control device 40.
Connected to 1.

The write data register 115 is connected to the read data selection circuit 125.
and connected to Cathy memory 131. Address array 130 is connected to address array data selection circuit 117 via address array register 116.

Stage 2 request register 113 is connected to cache memory 131 and replacement circuit 132.

Stage 3 request register 114 is connected to main memory request buffer 120 and stage 1 request register 1.
12. Furthermore, the main memory request buffer 7120 is a cache memo! j l 31 and the write data register 115 . Cache memory 131 is connected to read data selection circuit 125 and main memory device 201 via read data register 118. The successive data selection circuit 125 is the write data register 11
5 and the read data register 118, and supply the selected data to the arithmetic control device 301 and the input/output control device 401.

Next, an example of the operation within the memory control device 101 for normal memory access will be described. When memory access is made to the memory control device 101 by the arithmetic control device 301 or the input/output control device 401, the operation designation code,
Request information such as an address and store data is received by the request reception port circuit 110 or 111.

Next, one piece of request information is selected from the request reception port circuit and sent to the stage 1 request register 112. The stage 1 request register 112 decodes the operation designation code, and thereafter performs operations according to the operation designation.

When the operation designation is a read request, the address array 130 is first checked to see if the required data exists on the cache memory.

When the data exists (referred to as a character memory hit), the corresponding data is read from the cache memory 131 to the read data register 118 and sent to the requesting device. In addition, from the stage 2 request register 113, the referenced cache memory block transfer circuit 132
The results will be reflected in the results.

The operation specification is a write request, and the address array 130
If the corresponding data exists in the cache memory as a result of the index, writing is performed from the write data register 115 to the corresponding data in the cache memo 'J131. Writing to main memory device 201 is not performed at this time.

At this time, the replacement circuit 1
32 is reflected. By the way, address array 1
In 30, modification bits are provided corresponding to cache memory blocks. When this modification bit is on, it indicates that the latest data of the corresponding block is not present in the main memory device 201 but only in the cache memory 131. Qualification bits must be turned on when a write is performed. When a write request exists and corresponding data exists on the cache memory, the data in the address array 130 is read to the address array register 116 and the value of the modification bit is checked. With this modification, when the address array 1
A registration operation to 30 is performed.

When the required data does not exist on the cache memory as a result of address array 130 index in a read request or a write request (referred to as a cache memory miss), the following operations are performed. The stage 2 request register accesses the row placement circuit 132 to determine the row number of the block to be newly allocated.

This row number indicates the address array register 11 in which the data read from the address array 130 is stored.
The address array data of the block to be replaced from stage 3 is selected by the address array data selection circuit 117 and becomes the stage 3 request register 11401 part data. Information in stage 2 request register 113 is also sent to stage 3 request register 114.

A block transfer request is issued from the stage 3 request register 114 to the main memory device 201, and request information in the request to the main memory device is stored in the main memory request buffer 120. The types of this request information include the column address and row address of the cache memory where block transfer data is to be written, and store data when the request from the request source is a write request.

The contents of stage 3 request register 114 are returned to stage 1 request register and address array 130
Newly allocated block information is registered to. When the request from the request source is a write request, the above-mentioned modification and g are turned on at the same time. When the qualification bit of the block of the replaced address array is on, the latest data of the block to be replaced does not exist in the main memory device 201 but exists only in the corresponding block of the cache memory 131. The data needs to be returned to the main memory device. At this time, the request information in the stage 1 request register 112 containing the address t-tr of the replaced block is sent to the stage 2 request register 113, and the address of the replaced block is sent to the main memory device 200 from the stage 3 request register 114. A block loading request is made to the block. At this time, the data to be written to the main storage device 201 is sent from the cache memory 131 via the read data register 118. When the request from the request source is a read request, the main memory device 2
When the block transfer data is read from 01, the data is put into the write data register 115. At this time, the row address and column address of the cache memory where the data is to be written are taken out from the main memory request buffer 120, and the data in the write data register 115 is written into the cache memory 131. Further, the data is sent to the request source via the read data selection circuit 125. When the request from the request source is a write request, when block transfer data is sent from the main memory device 201, store data is extracted from the main memory request buffer 7120, merged with the block transfer data, and stored in the write data register. It is placed in 115.

In the above request processing, since a plurality of requests are processed in a pipeline manner, address interference occurs between request processings, but an address comparison circuit 121 is provided to avoid this. Address comparison circuit 12
1 stores the address currently being processed, and this address and a new stage 1 request register 112
The incoming addresses are compared, and if they match, request processing by the stage 1 request register 112 is inhibited.

Next, a description will be given of how cache memory data is written to the main memory device during dynamic modification according to an embodiment of the present invention.

In this embodiment, the following individual operation functions are provided in the memory control device, and each function is realized by microinstruction control of an arithmetic control device or the like.

The first function is the row-specified new allocation prohibition bit 119. This prohibition bit is provided for each row of the cache memory and can be set or canceled by a request from the request source. When this prohibition and the threshold are set, it is prohibited to use the corresponding line as a target for replacement in the event of a cache-memory miss.

However, when the cache memory is hit, read/write access to the corresponding row is permitted.

In general, many cache memory devices are equipped with a degrade bit corresponding to a row for the purpose of separating faulty cache memory in units of rows, but this degrade bit prevents the corresponding row from being targeted for braces and prevents the cache memory from being targeted for braces. In contrast to the hit suppression, the line designation new allocation prohibition bit performs only the former operation.

The second function is the function of writing cache memory data in line units to the main memory device. This row-by-row printing operation is instructed by a request from a request source, and is controlled by a printing control circuit 123 and a printing column address counter 122. When a row printing request is received from a request source, the printing control circuit 123 is activated and the printing column address counter 122 is initialized.

When the output column address counter 1220 receives a output request with a column address and a row address specified by the request source as an output request, the stage I request register 112 indexes the specified row and column 9 of the address array 130. If the result of the index is that the valid bit or qualification bit of the block is off, the process ends there. The operation when the valid bit and the modification bit are on is that block transfer processing is not performed in response to the cache-memory miss of the normal memory access request, and the address array 130
The same operation is performed except that the valid bit of the corresponding block is turned off. This causes the latest data only on the cache memory to be flushed out to the main memory device.

The third function is the installation of an input/output control device request reception suppression bit 124. This inhibition bit can be set or canceled by a request from the requesting device. The value of this bit is sent to all input/output control devices, and when set, the input/output control device inhibits memory access to the memory control device 101. Since the request acceptance inhibition signal from the memory control device 101 to each requesting device already exists for the purpose of conveying that the request acceptance port circuits 110, 111, etc. are busy, the contents of the input/output control device request acceptance inhibition bit are based on that signal. It is possible to share it with

Next, an example of an operation procedure when the arithmetic and control unit 301 executes a dynamic change from the system configuration of FIG. 3 to the system configuration of FIG. 1 by combining the above functions will be described.

(2) New allocation prohibition bit setting for cache memory row N of the memory control device 101 (assuming that the cache memory is composed of rows 0 to N).

(2) Instructing to write out the cache memory row N of the memory control device 101.

■ After completing row N of ■, set the new allocation prohibition bit for NN-1.

■ Cache memory row N-1 of memory control device 101
Directions for extruding lines.

The following operations ① and ② are repeated until the extrusion of row 1 is completed.

■ Set the input/output control device request reception suppression bit 124 of the memory control device 101.

(2) Instructing the memory control device 101 to skip the cache-memory row 0.

■ After finishing writing line 0 of , change the logical connection status between devices as shown in Figure 1.

■ Cancellation of the new allocation prohibition bit from row N to row 1 of the memory control device 101 and cancellation of the input/output control device request reception inhibition bit.

After the system configuration is changed by the above procedure, the memory control device 10
2 can be updated to the latest state. Third step of the above procedure
In the figure, the arithmetic control device 302 is also the memory control device 101.
If the processing control unit 301 is logically connected to the memory control unit 101, the arithmetic control unit 301 sends a processing suppression request to the arithmetic control unit 302 via the inter-device communication means before step Stop access. Further, when a part of the row of the cache memory in the memory control device 101 is disconnected due to a failure state or the like, that row must be excluded from the list of objects to be flushed out in the above procedure. In the above procedure, the process that requires the most processing time is the process of writing out the cache memory data to the main memory device, but as explained above (effects of the invention), the present invention Compared to the case where all memory accesses of the input/output control device are inhibited while the data is being read out, this inhibition time can be reduced to 1/the number of lines in the cache memory, which reduces input/output processing when the system configuration is dynamically changed. The risk of overrun can be reduced.

[Brief explanation of the drawing]

1, 2, and 3 are diagrams showing various system configurations in a memory control device, and FIG. 4 is a block diagram showing an embodiment of the present invention. 101.102...Mesori control device, 110°111.126.127...Request reception port circuit, 112...Stage 1 request register, 113...°"°・Stage 2 request register. 114...Stage 3 request register, 1
15°゛°°°°Honomi data register, 116...
...Address array register, 117...° Address array data selection circuit, 118... Read data register, 119... Row specification new allocation prohibition bit, 120... ...Main memory request buffer, 121...Address comparison circuit, 122...
...Exposed row address counter, 123...
...Extrusion control circuit, 124...Input/output control device request reception suppression pin l-1125...
Read data selection circuit, 130...Address array, 131...Key, key, mesori, 132...
...Replacement circuit, 201.202.20
3,204... Main memory device, 301.302
... Arithmetic control unit, 401, 402 input/output control unit. 〆、I・−、・）・、t・・。 Representative patent attorney Susumu Uchihara, - Hayabusa! Figure $2r5! J

Claims (1)

[Claims] a plurality of arithmetic control devices, a plurality of input/output control devices, a plurality of main memory devices, and a plurality of memory control devices that mediate memory access requests from the arithmetic control devices and the input/output control devices to the main memory device; In an information processing system having a cache memory of a set associative type or a store swap type that is shared by each of the arithmetic control units and input/output control units in each of the memory control units, specifying a row of the cache memory and a circuit for prohibiting new block registration to the cache memory, a circuit for specifying a line of the cache memory and outputting data of that line to the corresponding main memory device, and a memory access from the input/output control device to the memory control device. What is claimed is: 1. A memory control device comprising: a circuit for suppressing .